Tps 51220 A

TPS51220A
www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
Check for Samples: TPS51220A
1FEATURES
•
2 Input Voltage Range: 4.5 V to 32 V • Powergood Output for Each Channel
• Output Voltage Range: 1 V to 12 V • OCL/OVP/UVP/UVLO Protections
• Selectable Light Load Operation (OVP Disable Option)
(Continuous / Auto Skip / Out-Of-Audio™ Skip) • Thermal Shutdown (Non-Latch)
• Programmable Droop Compensation • Output Discharge Function (Disable Option)
• Voltage Servo Adjustable Soft Start • Integrated Boot Strap MOSFET Switch
• 200-kHz to 1-MHz Fixed-Frequency PWM • QFN-32 (RTV/RSN) Package
• Selectable Current/ D-CAP™ Mode
Architecture APPLICATIONS
• 180° Phase Shift Between Channels • Notebook Computer System and I/O Bus
• Resistor or Inductor DCR Current Sensing • Point of Load in LCD TV, MFP
• Adaptive Zero Crossing Circuit
DESCRIPTION
The TPS51220A is a dual synchronous buck regulator controller with two LDOs. It is optimized for 5-V/3.3-V
system controller, enabling designers to cost effectively complete 2-cell to 4-cell notebook system power supply.
The TPS51220A supports high efficiency, fast transient response, and 99% duty cycle operation. It supports
supply input voltage ranging from 4.5 V to 32 V, and output voltages from 1 V to 12 V. Two types of control
schemes can be chosen depending on the application. Peak current mode supports stability operation with lower
ESR capacitor and output accuracy. The D-CAP mode supports fast transient response. The high duty (99%)
operation and the wide input/output voltage range supports flexible design for small mobile PCs and a wide
variety of other applications. The fixed frequency can be adjusted from 200 kHz to 1 MHz by a resistor, and each
channel runs 180° out-of-phase. The TPS51220A can also synchronize to the external clock, and the interleaving
ratio can be adjusted by its duty. The TPS51220A is available in the 32-pin 5×5/4×4 QFN package and is
specified from –40°C to 85°C.
TYPICAL APPLICATION CIRCUIT

VREG5 VBAT
VBAT Q11 5V/100mA
C12 Q21 C22
C01
C14 C24 L2
L1 PGND PGND
VO2
VO1 Q12
PGND 3.3V
5.0V PGND GND C21
C11 Q22
32 31 30 29 28 27 26 25
V B ST 1
SW 1
VR E G5
D R VL 2
V BS T2
D RV L1
GN D
SW 2
PGND PGND PGND

PGND
1 24
DRVH1 DRVH2
VO1 2 V5SW VIN 23 VBAT
R01
VREG3
3 RF VREG3 22
C03 3.3V/10mA
GND EN1 4 EN1 EN2 21 EN2

TPS51220A
(QFN32)
PGOOD1 5 PGOOD1 PGOOD2 20 PGOOD2
GND
SKIPSEL1 6 SKIPSEL1 SKIPSEL2 19 SKIPSEL2
R14 PowerPAD R24
7 CSP1 CSP2 18
C13 C23
C O MP 1
C OM P2
CSN1
VR EF 2
8 CSN2 17
FU N C
VF B 1
VF B 2
T RIP
EN
9 10 11 12 13 14 15 16
GND
EN VREG5
R23 R21
VO1 VO2
R11
R12 R22
R13 C 02
GND
GND GND GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Out-Of-Audio, D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS51220A
SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
EN VIN
V5SW
4.7V/ 4.5V + + 1.25V + + 4.7V/ 4.5V
VREG5 VREG3
GND
+ V5OK
4.2V/ 3.8V
Ready GND
+
THOK VREF2
150/ 140 GND 1.25V
Deg-C
GND
CLK2
RF OSC
CLK1 GND
1V +5%/ 10% +
PGOOD1
Delay
+
1V -30% + 1V - 5%/ 10%

GND
UVP CLK1
Ready
Fault2
+ OVP
SDN2
FUNC 1V +15%
Fault1
COMP1 Clamp (+) Ramp SDN1
+
Comp
Clamp (-) + PWM
CUR
VFB1 VREG5
D-CAP
1V +
VREF2
VFB-AMP VBST1
+
Enable/
EN1 Ramp Control
Soft-start +
Comp Skip Logic DRVH1
CSN1 CS-AMP
SW1
+
+ OCP XCON
CSP1
100mV VREG5
DRVL1
TRIP AZC
Discharge
Control
GND GND
100mV N-OCP
VREF2 +
OOA GND
Ctrl
SKIPSEL1 GND
Channel-1 Switcher shown
2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links :TPS51220A

TPS51220A
ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
TPS51220A UNIT
VIN –0.3 to 34
VBST1, VBST2 –0.3 to 39
VBST1, VBST2 (3) –0.3 to 7
(2)
SW1, SW2 –7 to 34
Input voltage range V
CSP1, CSP2, CSN1, CSN2 –1 to 13.5
EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2, FUNC –0.3 to 7
V5SW –1 to 7
(4)
V5SW (to VREG5) –7 to 7
DRVH1, DRVH2 –7 to 39
DRVH1, DRVH2 (3) –0.3 to 7
(3)
DRVH1, DRVH2 (duty cycle < 2%) –2 to 7
Output voltage range (2) DRVL1, DRVL2 (duty cycle < 2%) –2 to 7 V
DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2,
–0.3 to 7
PGOOD1, PGOOD2
VREG3 –0.3 to 3.6
TJ Junction temperature 150 °C
Tstg Storage temperature –55 to 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding SW terminal.
(4) When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)

TA < 25°C DERATING FACTOR TA = 85°C
PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING
(W) (mW/°C) (W)
32-pin RTV 1.7 17 0.7
32-pin RSN 2.3 23 0.9
RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
VIN 4.5 32 V
Supply voltage
V5SW –0.8 6
VBST1, VBST2 –0.1 37
DRVH1, DRVH2 –4. 37
DRVH1, DRVH2 (wrt SW1, 2) –0.1 6
DRVH1, DRVH2 (negative overshoot -6 V for t < 20% duration of the -6 37
switching period)
SW1, SW2 –4. 32
I/O voltage V
SW1, SW2 (negative overshoot -6 V for t < 20% duration of the -6 32
switching period)
CSP1, CSP2, CSN1, CSN2 –0.8 13
EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2,
VREG5, RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2, –0.1 6
FUNC
VREG3 –0.1 3.5
TA Operating free-air temperature –40 85 °C
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS51220A
ORDERING INFORMATION
ORDERABLE
TA PACKAGE (1) PINS DEVICE TRANSPORT MEDIA QUANTITY ECO PLAN
NUMBER
TPS51220ARTVT 250
Plastic Quad TPS51220ARTVR 3000 Green (RoHS
-40°C to 85°C 32 Tape and Reel
Flat Pack (QFN) TPS51220ARSNT 250 and no Sb/Br)
TPS51220ARSNR 3000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VEN = 3.3 V, VVIN = 12 V, VV5SW = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN shutdown current, TA = 25°C,
IVINSDN VIN shutdown current 7 15 μA
No Load, EN = 0V, V5SW = 0 V
VIN standby current, TA = 25°C, No Load,
IVINSTBY VIN Standby Current 80 120 μA
EN1 = EN2 = V5SW = 0 V
Vbat standby current, TA = 25°C, No Load
IVBATSTBY VBAT Standby Current 500 μA
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V (1)
V5SW current, TA = 25°C, No Load, TRIP = 5 V 0.8 mA

IV5SW V5SW Supply Current
ENx = 5V, VFBx = 1.05 V TRIP = 0 V 0.9 mA
VREF2 OUTPUT
I(VREF2) < ±10 μA, TA = 25°C 1.98 2.00 2.02
VVREF2 VREF2 Output Voltage V
I(VREF2) < ±100 μA, 4.5V < VIN < 32 V 1.97 2.00 2.03
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C 3.279 3.313 3.347
VVREG3 VREG3 Output Voltage V5SW = 0 V, 0 mA < I(VREG3) < 10 mA, V
3.135 3.300 3.400
5.5 V < VIN < 32 V
IVREG3 VREG3 Output Current VREG3 = 3 V 10 15 20 mA
VREG5 OUTPUT
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C 4.99 5.04 5.09
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA, V
4.90 5.03 5.15
VVREG5 VREG5 Output Voltage 6 V < VIN < 32 V
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
4.50 5.03 5.15 V
5.5 V < VIN < 32 V
V5SW = 0 V, VREG5 = 4.5 V 100 150 200
IVREG5 VREG5 Output Current mA
V5SW = 5 V, VREG5 = 4.5 V 200 300 400
Turning on 4.55 4.7 4.8
VTHV5SW Switchover Threshold V
Hysteresis 0.15 0.20 0.25
tdV5SW Switchover Delay Turning on 7.7 ms
RV5SW 5V SW On-Ressitance I(VREG5) = 100 mA 0.5 Ω
OUTPUT
TA = 25°C, No Load 0.9925 1.000 1.0075
VVFB VFB Regulation Voltage Tolerance V
TA = –40°C to 85°C , No Load 0.990 1.000 1.010
IVFB VFB Input Current VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C –50 50 nA
RDISCHG CSNx Discharge Resistance ENx = 0 V, CSNx = 0.5 V, TA = 25°C 20 40 Ω
(1) Specified by design. Detail external condition follows application circuit of Figure 57.

TPS51220A
ELECTRICAL CHARACTERISTICS (continued)

VOLTAGE TRANSCONDUCTANCE AMPLIFIER
gMv Gain TA = 25°C 500 μS
VID Differential Input Voltage Range –30 30 mV
TA = 0 to 85°C 27 33 μA
ICOMPSINK COMP Maximum Sink Current COMPx = 1.8 V
TA = –40 to 85°C 22 33 μA
ICOMPSRC COMP Maximum Source Current COMPx = 1.8 V –33 –43 μA
VCOMP COMP Clamp Voltage 2.18 2.22 2.26 V
VCOMPN COMP Negative Clamp Voltage 1.73 1.77 1.81 V
CURRENT AMPLIFIER
(2)
TRIP = 0V/2V, CSNx = 5V, TA = 25°C 3.333
GC Gain (2)
TRIP = 3.3V/5V, CSNx = 5V, TA = 25°C 1.667
VIC Common mode Input Voltage Range 0 13 V
VID Differential Input Voltage Range TA = 25°C –75 75 mV
POWERGOOD
PG in from lower 92.5% 95% 97.5%
VTHPG PG threshold PG in from higher 102.5% 105% 107.5%
PG hysteresis 5%
IPG PG sink current PGOOD = 0.5 V 5 mA
IPG(LK) PG leak current PGOOD = 5 V 0 1 µA
tPGDLY PGOOD delay Delay for PG in 0.8 1.0 1.2 ms
SOFTSTART
tSSDYL Soft Start Delay Delay for Soft Start, ENx = Hi to SS-ramp starts 200 μs
tSS Soft Start Time Internal Soft Start 960 μs
FREQUENCY AND DUTY CONTROL
fSW Switching Frequency RF = 330 kΩ 273 303 333 kHz
Lo to Hi 0.7 1.3 2 V
VTHRF RF Threshold
Hysteresis 0.2 V
fSYNC Sync Input Frequency Range (2) 200 1000 kHz
V(DRVH) = 90% to 10%, No Load, CCM/ OOA (2) 120 ns
tON(min) Minimum On Time
V(DRVH) = 90% to 10%, No Load, Auto-skip 160 250 ns
tOFF(min) Minimum Off Time V(DRVH) = 10% to 90%, No Load 290 400 ns
DRVH-off to DRVL-on 10 30 50 ns
tD Dead time
DRVL-off to DRVH-on 30 40 70 ns
(2)
VDTH DRVH-off threshold DRVH to GND 1 V
VDTL DRVL-off threshold DRVL to GND (2) 1 V
(2) Specified by design. Not production tested.

TPS51220A

CURRENT SENSE
RTV package,
28 31 35
TA = 0 to 85°C
TRIP=0V/ 2V, 2V<CSNx<12.6V RSN package ,
28 31 34
Current limit threshold TA = 0 to 85°C
VOCL-ULV mV
(ultra-low voltage)
TA = –40 to 85°C 27 31 37
TA = 0 to 85°C 27 31 36
TRIP=0V/ 2V, 0.95V<CSNx<12.6V
TA = –40 to 85°C 25 31 42
TA = 0 to 85°C 56 60 65
TRIP=3.3V/ 5V, 2V<CSNx<12.6V
Current limit threshold TA = –40 to 85°C 55 60 68
VOCL-LV mV
(low voltage) TA = 0 to 85°C 55 60 67
TRIP=3.3V/ 5V,
0.95V<CSNx<12.6V TA = –40 to 85°C 54 60 72
Positive 5
VZCAJ Auto-Zero cross adjustable offset range 0.95V < CSNx < 12.6V, Auto-skip mV
Negative –5
VZC Zero cross detection comparator Offset 0.95V < CSNx < 12.6V, OOA –4 0 4 mV
Negative current limit threshold TRIP = 0V/2V, 0.95V < CSNx < TA = 0 to 85°C –23 –31 –40
VOCLN-ULV
(ultra-low voltage) 12.6V TA = –40 to 85°C –22 –31 –44
mV
Negative current limit threshold TRIP = 3.3V/5V, 0.95V < CSNx < TA = 0 to 85°C –50 –60 –73
VOCLN-LV
(low voltage) 12.6V TA = –40 to 85°C –49 –60 –77
OUTPUT DRIVERS
Source, V(VBST-DRVH) = 0.1 V 1.7 5
RDRVH DRVH resistance Ω
Sink, V(DRVH-SW) = 0.1 V 1 3
Source, V(VREG5-DRVL) = 0.1 V 1.3 4
RDRVL DRVL resistance Ω
Sink, V(DRVL-GND) = 0.1 V 0.7 2
UVP, OVP AND UVLO
VOVP OVP Trip Threshold OVP detect 110% 115% 120%
tOVPDLY OVP Prop Delay 1.5 μs
VUVP UVP Trip Threshold UVP detect 65% 70% 73%
tUVPDLY UVP Delay 0.8 1 1.2 ms
Wake up 1.7 1.8 1.9 V
VUVREF2 VREF2 UVLO Threshold
Hysteresis 75 100 125 mV
Wake up 3 3.1 3.2
VUVREG3 VREG3 UVLO Threshold V
Wake up 4.1 4.2 4.3 V
VUVREG5 VREG5 UVLO Threshold
Hysteresis 0.35 0.40 0.44 V

TPS51220A

INTERFACE AND LOGIC THRESHOLD
Wake up 0.8 1 1.2
VEN EN Threshold V
IENLK EN leak current EN = 0 V, or EN = 3.3 V -1 1 μA
Wake up 0.45 0.50 0.55
VEN12 EN1/EN2 Threshold V
VEN12SS EN1/EN2 SS Start Threshold SS-ramp start threshold at external soft start 1 V
(3)
VEN12SSEND EN1/EN2 SS End Threshold SS-End threshold at external soft start 2 V
IEN12 EN1/EN2 Source Current VEN1/EN2 = 0V 1.6 2 2.4 μA
Continuous 1.5
Auto Skip 1.9 2.1
VSKIPSEL SKIPSEL1/SKIPSEL2 Setting Voltage V
OOA Skip (min 1/8 Fsw) 3.2 3.4
OOA Skip (min 1/16 Fsw) 3.8
V(OCL-ULV), Discharge ON 1.5
V(OCL-ULV), Discharge OFF 1.9 2.1
VTRIP TRIP Setting Voltage V
V(OCL-LV), Discharge OFF 3.2 3.4
V(OCL-LV), Discharge ON 3.8
Current mode, OVP enable 1.5
D-CAP mode, OVP disable 1.9 2.1
VFUNC FUNC Setting Voltage V
D-CAP mode, OVP enable 3.2 3.4
Current mode, OVP disable 3.8
TRIP = 0 V –1 1
ITRIP TRIP Input Current μA
TRIP = 5 V –1 1
SKIPSELx = 0 V –0.5 0.5
ISKIPSEL SKIPSEL Input Current μA
SKIPSELx = 5 V –0.5 0.5
BOOT STRAP SW
VFBST Forward Voltage VVREG5-VBST, IF = 10 mA, TA = 25°C 0.10 0.20 V
IBSTLK VBST Leakage Current VVBST = 37 V, VSW = 32 V 0.01 1.5 μA
THERMAL SHUTDOWN
Shutdown temperature (3) 150
TSDN Thermal SDN Threshold (3)
°C
Hysteresis 10
(3) Specified by design. Not production tested.

TPS51220A
DEVICE INFORMATION
RSN PACKAGE RTV PACKAGE

(TOP VIEW) (TOP VIEW)
VREG5
VREG5
DRVL1
DRVL2
DRVL1
DRVL2
VBST1
VBST2
VBST1
VBST2
GND
GND
SW1
SW1
SW2
SW2
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
DRVH1 1 24 DRVH2 DRVH1 1 24 DRVH2
V5SW 2 23 VIN V5SW 2 23 VIN
RF 3 22 VREG3 RF 3 22 VREG3
EN1 4 TPS51220A 21 EN2 EN1 4 TPS51220A 21 EN2
PGOOD1 5 20 PGOOD2 PGOOD1 5 20 PGOOD2
SKIPSEL1 6 19 SKIPSEL2 SKIPSEL1 6 19 SKIPSEL2
CSP1 7 18 CSP2 CSP1 7 18 CSP2
CSN1 8 17 CSN2 CSN1 8 17 CSN2
10
12
13
14
15
16
10
12
13
14
15
16
11
11
9
9
VFB1
COMP1
VFB1
COMP1
FUNC
FUNC
VREF2
VFB2
VREF2
VFB2
EN
TRIP
EN
TRIP
COMP2
COMP2
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
DRVH1 1 High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive
O
DRVH2 24 voltage corresponds to VBST to SW voltage.
SW2 25
I/O High-side MOSFET gate driver returns.
SW1 32
Always alive 3.3 V, 10 mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-μF
VREG3 22 O
ceramic capacitance. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
EN1 4 Channel 1 and channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55 V and less than 6 V,
I
EN2 21 or leave floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
PGOOD1 5 Powergood window comparator outputs for channel 1 and channel 2. The recommended applied voltage
O
PGOOD2 20 should be less than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
SKIPSEL1 6 Skip mode selection pin.
GND: Continuous conduction mode
I VREF2: Auto Skip
SKIPSEL2 19
VREG3: OOA Auto Skip, maximum 7 skips (suitable for fsw < 400kHz)
VREG5: OOA Auto Skip, maximum 15 skips (suitable for equal to or greater than 400kHz)
CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
I/O be used to extract voltage drop across DCR. 0.1-μF is a good value to start the design. See the current
CSP2 18 sensing scheme section for more details.
CSN1 8 Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
I
CSN2 17 current sense circuit for 5V or higher output voltage setting. Also, used for output discharge terminal.
VFB1 9 SMPS voltage feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)
I
VFB2 16 GND.
COMP1 10 Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin
to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin for
I
COMP2 15 D-CAP mode, connect R from this pin to VREF2. 10 kΩ is a good value to start the design. 6 kΩ to 20 kΩ
can be chosen. See the D-CAP MODE section for more details.

TPS51220A
PIN FUNCTIONS (continued)

PIN
I/O DESCRIPTION
NAME NO.
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
RF 3 I/O
synchronization.
Control architecture and OVP functions selection pin.
GND: Current mode, OVP enable
FUNC 11 I VREF2: D-CAP mode, OVP disable
VREG3: D-CAP mode, OVP enable
VREG5: Current mode, OVP disable
VREF2 13 O 2-V reference output. Bypass to (signal) GND with 0.22-μF of ceramic capacitance.
Overcurrent trip level and discharge mode selection pin.
GND: V(OCL-ULV) , discharge on
TRIP 14 I VREF2: V(OCL-ULV), discharge off
VREG3: V(OCL-LV), discharge off
VREG5: V(OCL-LV), discharge on
VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6
EN 12 I
V. Connect to GND to disable.
VBST1 31 Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1-μF or
I greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
VBST2 26 pin is an optional.
DRVL1 30
O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver.
DRVL2 27
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function is enabled.
V5SW 2 I
Note: When switch-over is enabled, VREG5 output voltage is approximately equal to the V5SW input
voltage.
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10-μF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
VREG5 29 O when 4.8 V or above is provided.
Note: When switch-over (see above V5SW) is enabled, VREG5 output voltage is approximately equal to
V5SW input voltage.
VIN 23 I Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
GND 28 – Ground

TPS51220A
TYPICAL CHARACTERISTICS
INPUT VOLTAGE SHUTDOWN CURRENT INPUT VOLTAGE SHUTDOWN CURRENT
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
15 15
TA = 25°C VI = 12 V
IVINSDN -– Shutdown Current – mA

IVINSDN -– Shutdown Current – mA
12 12
9 9
6 6
3 3
0 0
5 10 15 20 25 30 -50 0 50 100 150
VI – Input Voltage – V TJ – Junction Temperature – °C
Figure 1. Figure 2.
INPUT VOLTAGE STANDBY CURRENT INPUT VOLTAGE STANDBY CURRENT

vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE
150 150
VI = 12 V TA = 25°C
IVINSTBY – Standby Current – mA
IVINSTBY – Standby Current – mA
120 120
90 90
60 60
30 30
0 0
-50 0 50 100 150 5 10 15 20 25 30
TJ – Junction Temperature – °C VI – Input Voltage – V
Figure 3. Figure 4.

TPS51220A
TYPICAL CHARACTERISTICS (continued)

NO LOAD BATTERY CURRENT NO LOAD BATTERY CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
1.0 1.0
EN = on EN = on
0.9 0.9
EN1 = off EN1 = on
EN2 = on EN2 = on
0.8 0.8
IVBAT – Battery Current – mA

0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
5 10 15 20 25 5 10 15 20 25
VI – Input Voltage – V VI – Input Voltage – V
Figure 5. Figure 6.
BATTERY CURRENT VREF2 OUTPUT VOLTAGE

vs vs
INPUT VOLTAGE OUTPUT CURRENT
1.0 2.02
EN = on VI = 12 V
0.9
EN1 = on
VVREF2 – VREF2 Output Voltage – V
EN2 = off
0.8
2.01
0.7
0.6
0.5 2.00
0.4
0.3
1.99
0.2
0.1
0 1.98
5 10 15 20 25 –100 –50 0 50 100
VI – Input Voltage – V IVREF2 – VREF2 Output Current – mA
Figure 7. Figure 8.

TPS51220A

VREG3 OUTPUT VOLTAGE VREG5 OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
3.40 5.10
VVREG3 – 3.3-V Linear Regulator Output Voltage – V
VVREG5 – 5-V Linear Regulator Output Voltage – V

VI = 12 V VI = 12 V
3.35 5.05
3.30 5.00
3.25 4.95
3.20 4.90
0 2 4 6 8 10 0 20 40 60 80 100
IREG3 – 3-V Linear Regulator Output Current – mA IREG5 – 5-V Linear Regulator Output Current – mA
Figure 9. Figure 10.
SWITCHING FREQUENCY FORWARD VOLTAGE OF BOOST SW

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
330 0.25
VFBST – Forward Voltage Boost Voltage – V
RRF = 330 kW
320
fSW – Switching Frequency – kHz
0.20
310
0.15
300
0.10
290
0.05
280
270 0
-50 0 50 100 150 -50 0 50 100 150
TJ – Junction Temperature – °C TJ – Junction Temperature – °C

TPS51220A

OVP/UVP THRESHOLD VOLTAGE VBST LEAKAGE CURRENT
vs vs
150 1.5
OVP
UVP
IBSTLK – VBST Leakage Current – mA

Voltage Protection Threshold – %
130 1.2
110 0.9
90 0.6
70 0.3
50 0
-50 0 50 100 150 -50 0 50 100 150
CURRENT LIMIT THRESHOLD CURRENT LIMIT THRESHOLD

vs vs
37 66
VCSN (V) VCSN (V)

VOCL-ULV – Current Limit Threshold – mV
VOCL-LV – Current Limit Threshold – mV
35 1 64 1
5 5
12 12
33 62
31 60
29 58
27 56
25 54
-50 0 50 100 150 -50 0 50 100 150


TPS51220A

5-V OUTPUT VOLTAGE 3.3-V OUTPUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
5.2 3.40
Auto-Skip Mode Auto-Skip Mode
5.1 fSW = 330 kHz fSW = 330 kHz
5.0
VO2 – 3.3-V Output Voltage – V

VO1 – 5-V Output Voltage – V
3.35
4.9
4.8
4.7 3.30
4.6
4.5
IO (A) 3.25 IO (A)
4.4
0 0
4 4
4.3
8 8
4.2 3.20
4.5 5.0 5.5 6.0 6.5 7.0 4.5 5.0 5.5 6.0 6.5 7.0
VI – Input Voltage – V VI – Input Voltage – V
5-V EFFICIENCY 5-V EFFICIENCY

vs vs
100 100
Auto-Skip VI = 8 V
80 90
VI = 12 V
VI = 20 V
h – Efficiency – %
60 80
OOA CCM
40 70
20 Current Mode 60 Auto-Skip

VI = 12 V Current Mode
RGV = 18 kW RGV = 18 kW
0 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
IO1 – 5-V Output Current – A IO1 – 5-V Output Current – A

TPS51220A

3.3-V EFFICIENCY 3.3-V EFFICIENCY
vs vs
100
100
VI = 8 V
Auto-Skip 90
80
VI = 12 V VI = 20 V
80
60 CCM
70
OOA
40
60
Auto-Skip
VI = 12 V Current Mode
20 Current Mode 50
RGV = 12 kW
RGV = 12 kW 5.0-V SMPS: ON
5.0-V SMPS: ON
40
0 0.001 0.01 0.1 1 10
0.001 0.01 0.1 1 10
IO2 – 3.3-V Output Current – A
5-V SWITCHING FREQUENCY 3.3-V SWITCHING FREQUENCY

vs vs
400 400
CCM CCM
350 350
300 300
250 250
200 200
150 150
100 100
OOA OOA
50 50
Auto-Skip Auto-Skip
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
IO1 – 5-V Output Current – A IO2 – 3.3-V Output Current – A

TPS51220A

vs vs
5.10 3.40
5.08 3.38
Auto-Skip
5.06 Auto-Skip 3.36 and

OOA
5.04 3.34
5.02 3.32
5.00 3.30
OOA
4.98 3.28 CCM
CCM
4.96 3.26
4.94 VI = 12 V 3.24 VI = 12 V
Current Mode Current Mode
4.92 3.22
4.90 3.20
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

vs vs
5.10
3.40
5.08
3.38
5.06 Auto-Skip Auto-Skip
3.36 and
and
5.04 OOA OOA
3.34
5.02
3.32
5.00
3.30
4.98
CCM 3.28 CCM
4.96 VI = 12 V
3.26 VI = 12 V
Current Mode
4.94 (Non-droop) Current Mode
3.24 (Non-droop)
RGV = 10 kW
4.92 C = 1.8 nF RGV = 9.1 kW
3.22 C = 1.8 nF
4.90
0 1 2 3 4 5 6 7 8 3.20
0 1 2 3 4 5 6 7 8
IO1 – 5-V Output Current – A

TPS51220A

vs vs
5.10 3.40
5.08 3.38 Auto-Skip

Auto-Skip and
5.06 3.36 OOA

5.04 3.34
5.02 3.32
5.00 OOA 3.30
4.98 CCM 3.28 CCM
4.96 3.26
4.94 VI = 12 V 3.24 VI = 12 V
D-CAP Mode D-CAP Mode
4.92 3.22
4.90 3.20
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
5.0-V BODE-PLOT – GAIN AND PHASE 3.3-V BODE-PLOT – GAIN AND PHASE
vs vs
FREQUENCY FREQUENCY
80 180 80 180
Phase Phase
60 135 60 135
40 90 40 90
20 45 20 45
Gain – dB
Gain – dB
Phase – °
Phase – °
Gain Gain
0 0 0 0
–20 45 –20 45
–40 –90 –40 –90

VO= 5.0 V VO= 3.3 V
–60 VI = 12 V –135 –60 VI = 12 V –135
IO = 8 A IO = 8 A
–80 –180 –80 –180

100 1k 10 k 100 k 1M 100 1k 10 k 100 k 1M
f – Frequency – Hz f – Frequency – Hz

TPS51220A

5.0-V SWITCH-OVER WAVEFORMS
VREG5 (100 mV/div)
VO1 (100 mV/div)
2 ms/div
Figure 33.

TPS51220A
TYPICAL CHARACTERISTICS
5.0-V START-UP WAVEFORMS 3.3-V START-UP WAVEFORMS
EN2 (5V/div)
EN1 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD2 (5V/div)
PGOOD1 (5V/div) 1msec/div
1msec/div
5.0-V SOFT-STOP WAVEFORMS 3.3-V SOFT-STOP WAVEFORMS
EN1 (5V/div) EN2 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD1 (5V/div) PGOOD2 (5V/div)
1msec/div
10msec/div 10msec/div
1msec/div

TPS51220A

5.0-V LOAD TRANSIENT RESPONSE 3.3-V LOAD TRANSIENT RESPONSE
VI=12V, Auto-skip VI =12V, Auto-skip

VO1 (100mV/div) VO2 (100mV/div)
SW1 (10V/div) SW2 (10V/div)
100
100 mms/div
s/div IO1 (5A/div)
100 IO2 (5A/div)
100 mms/div
s/div

TPS51220A
DETAILED DESCRIPTION
ENABLE AND SOFT START

When EN is Low, the TPS51220A is in the shutdown state. Only the 3.3-V LDO stays alive, and consumes 7 μA
(typically). When EN becomes High, the TPS51220A is in the standby state. The 2-V reference and the 5-V LDO
become enabled, and consume about 80 μA with no load condition, and are ready to turn on SMPS channels.
Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51220A begins the
softstart sequence, and ramps up the output voltage from zero to the target voltage in 0.96 ms. However, if a
slower soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the
TPS51220A charges the external capacitor with the integrated 2-μA current source. An approximate external
soft-start time would be tEX-SS = CEX / IEN12, which means the time from ENx = 1 V to ENx = 2 V. The recommend
capacitance is more than 2.2 nF.
1) Internal
Soft-start
EN1
Vout1
200ms
960ms
EN1>1V EN1<2V
2) External
Soft-start
EN1
Vout1 External
Soft-start
time
Figure 40. Enable and Soft-start Timing
Table 1. Enable Logic States

EN EN1 EN2 VREG3 VREF2 VREG5 CH1 CH2
GND Don’t Care Don’t Care ON Off Off Off Off
Hi Lo Lo ON ON ON Off Off
Hi Hi Lo ON ON ON ON Off
Hi Lo Hi ON ON ON Off ON
Hi Hi Hi ON ON ON ON ON
PRE-BIASED START-UP
The TPS51220A supports a pre-biased start up by preventing negative inductor current during soft-start when
the output capacitor holds some charge. The initial DRVH signal waits until the voltage feedback signal becomes
greater than the internal reference ramping up by the soft-start function. After that, the start-up occurs in the
same way the soft-start condition fully discharges, regardless of the SKIPSELx selection.

TPS51220A
3.3-V, 10-mA LDO (VREG3)

A 3.3-V, 10-mA, linear regulator is integrated in the TPS51220A. This LDO services some of the analog circuit in
the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-μF (at least 1-μF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
device.
2-V, 100-μA Sink/Source Reference (VREF2)

This voltage is used for the reference of the loop compensation network. Apply a 0.22-μF (at least 0.1-μF), high-
quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the device.
5.0-V, 100-mA LDO (VREG5)

A 5.0-V, 100-mA, linear regulator is integrated in the TPS51220A. This LDO services the main analog supply rail
and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-μF (at least 4.7-
μF), high-quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the device.
VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and a voltage of more than 4.8 V is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after an 7.7-ms delay. When the
V5SW voltage becomes lower than 4.65 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off, and the internal 5V-LDO resumes immediately.
BASIC PWM OPERATIONS

The main control loop of the SMPS is designed as a fixed frequency, pulse width modulation (PWM) controller. It
supports two control schemes; a peak current mode and a proprietary D-CAP mode. Current mode achieves
stable operation with any type of output capacitors, including low ESR capacitor(s) such as ceramic or specialty
polymer capacitors. D-CAP mode does not require an external compensation circuit, and is suitable for relatively
larger ESR capacitor(s) configuration. These control schemes are selected with FUNC pin. See Table 4.
CURRENT MODE
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage decreases, the TPS51220A increases the target inductor current to raise the output voltage.
Alternatively, if the output voltage rises, the TPS51220A decreases the target inductor current to reduce the
output voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The high-
side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the controller
regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each OFF state to
keep the conduction loss minimum.
D-CAP™ MODE
With the D-CAP mode operation, the PWM comparator compares VREF2 with the combination value of the
COMP voltage, VFB-AMP output, and the ramp compensation signal. When the both signals are equal at the
peak of the voltage sense signal, the comparator provides the OFF signal to the high-side MOSFET driver.
Because the compensation network is implemented on the part and the output waveform itself is used as the
error signal, external circuit is simplified. Another advantage is its inherent fast transient response. A trade-off is
a sufficient amount of ESR required in the output capacitor. The D-CAP™ mode is suitable for relatively larger
output ripple voltage application. The inductor current information is used for the overcurrent protection and light
load operation.

TPS51220A
PWM FREQUENCY CONTROL

The TPS51220A has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
1 × 105
fsw éëkHz ùû =
RF ëékΩ ûù (1)
TPS51220A can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF
pin. The set timing of channel 1 initiates at the raising edge (1.3 V typ) of the clock and channel 2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
When the external clock synchronization is selected, the following conditions are required.
• Remove RF resistor
• Add clock signal before EN1 or EN2 turning on
The TPS51220A does NOT support switching frequency change on-the-fly. (neither from the switching frequency
set by the RF resistor to the external clock, nor vice versa)
1000
900
800
700
fSW - Frequency - kHz
600
500
400
300
200
100
0
100 200 300 400 500
RF - Resistance - kW
Figure 41. Switching Frequency vs RF
180 Degrees Phase Shift and Blanking Time

The two channels of the SMPS operate 180 degrees phase shift. This scheme helps in reducing the input RMS
current. As a result, the device provides the benefits of saving the number and power loss of the input bulk
capacitors. To minimize interaction between the two channels caused by switching noise, blanking time is
implemented. The loop comparator output is masked during the blanking time to avoid false turning off the
channel.
There are two cases where the inter-channel communication can take place:
1. One channel's switching node falling edge is close to another channel's switching node rising edge.
2. One channel's switching node falling edge is close to another channel's switching node falling edge.

TPS51220A
In both cases, the TPS51220A shows jitter inherent to the blanking time. Since the device is a fixed frequency
controller, the rising edge of the switching node is settled at the clock cycle. Consequently, jitter is observed at a
period of switching node falling edge. This jitter does not represent small signal instability. In fact, jittering is a
normal action of control loop against timing deviation caused by any accidental event such as noise, or the
blanking time, adjusting back to the regulation point. A small amount of jittering does not harm the voltage
regulation. However; if the user wants a further reduction of jitter, using the external clock synchronization
provides adjustable phase shift between channels to avoid overlapping of switching events. See the PWM
Frequency Control section.
LIGHT LOAD OPERATION

The TPS51220A automatically reduces switching frequency at light load conditions to maintain high efficiency if
Auto Skip or Out-of-Audio™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak reaches a predetermined current, ILL(PEAK), which indicates the
boundary between heavy-load and light-load conditions. Once the top MOSFET is turned on, the TPS51220A
does not allow it to be turned off until it reaches ILL(PEAK). This eventually causes an overvoltage condition to the
output and pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited by the ramp-
down signal ILL(PEAK)RAMP, which starts from 25% of the overcurrent limit setting (IOCL(PEAK): (see the Current
Protection section) toward 5% of IOCL(PEAK) over one switching cycle to prevent causing large ripple. The
transition load point to the light load operation ILL(DC) can be calculated in Equation 2.
I LL(DC) + I LL(PEAK) * 0.5 I IND(RIPPLE)
(2)
1 (V - VOUT ) × VOUT
IIND(RIPPLE) = × IN
L × fSW VIN
where
• fSW is the PWM switching frequency which is determined by RF resistor setting or external clock (3)
ILL(PEAK)RAMP = (0.2 - 0.13 ´ t ´ fSW )´ IOCL(PEAK )
(4)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportionally to the output current from the ILL(DC), as described in Equation 2; while
maintaining the switching synchronization with the clock. Due to the synchronization, the switching waveform in
boundary load condition (close to ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended
operation.
If SKIPSELx is tied to GND, the TPS51220A works on a constant frequency of fSW regardless its load current.
Inductor
Current
ILL(PEAK)
ILL(DC) IIND(RIPPLE)
0 Time
Figure 42. Boundary Between Pulse Skipping and CCM

TPS51220A
ILL(peak) – Inductor Current Limit – A

20% of IOCL ILL(PEAK) Ramp Signal
ILL(PEAK) at
Light Load
7% of IOCL
tON
1/fSW
t – Time
Figure 43. Inductor Current Limit at Pulse Skipping
Table 2. Skip Mode Selection

SKIPSELx GND VREF2 VREG3 VREG5
OOA Skip (maximum 7 OOA Skip (maximum 15 skips, for
OPERATING MODE Continuous Conduction Auto Skip
skips, for <400 kHz) equal to or greater than 400kHz)
OUT OF AUDIO SKIP OPERATION

Out-Of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no load condition while maintaining state-of-the-art high conversion
efficiency. When OOA is selected, the switching frequency is kept higher than audible frequency range in any
load condition. The TPS51220A automatically reduced switching frequency at light-load conditions. The OOA
control circuit monitors the states of both MOSFETs and forces an ON state if the predetermined number of
pulses are skipped. The high-side MOSFET is turned on before the output voltage declines down to the target
value, so that eventually an overvoltage condition is caused. The OOA control circuit detects this overvoltage
condition and begins modulating the skip-mode on time to keep the output voltage.
The TPS51220A supports a wide-switching frequency range, therefore, the OOA skip mode has two selections.
See Table 2. When the 300-kHz switching frequency is selected, a maximum of seven (7) skips (SKIPSEL=3.3
V) makes the lowest frequency at 37.5 kHz. If a 15-skip maximum is chosen, it becomes 18.8 kHz, hence the
maximum 7 skip is suitable for less than 400 kHz, and the maximum 15 skip is 400 kHz or greater.
99% DUTY CYCLE OPERATION

In a low-dropout condition such as 5-V input to 5-V output, the basic control loop attempts to maintain 100% of
the high-side MOSFET ON. However, with the N-channel MOSFET used for the top switch, it is not possible to
use the 100% on-cycle to charge the boot strap capacitor. When high duty is required, the TPS51220A extends
the ON period (by skipping a maximum of three clock cycles and reducing the switching frequency to 25% of the
steady state value) and asserts the OFF state after extended ON.

TPS51220A
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.7Ω for VBSTx to DRVHx, and 1Ω for DRVHx to SWx. When
configured as a floating driver, 5 V of bias voltage is delivered from VREG5 supply. The instantaneous drive
current is supplied by the flying capacitor between VBSTx and SWx pins. The average drive current is equal to
the gate charge at Vgs = 5V times switching frequency. This gate drive current as well as the low-side gate drive
current times 5 V makes the driving power which needs to be dissipated mainly from TPS51220A package. A
dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET
on, and low-side MOSFET off to high-side MOSFET on.
LOW-SIDE DRIVER
The low-side driver is designed to drive high-current low-RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.3Ω for VREG5 to DRVLx and 0.7Ω for DRVLx to GND. The 5-
V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor
connected between VREG5 and GND. The average drive current is also calculated by the gate charge at
Vgs = 5 V times switching frequency.
CURRENT SENSING SCHEME

In order to provide both good accuracy and cost effective solution, the TPS51220A supports external resistor
sensing and inductor DCR sensing. An RC network with high quality X5R or X7R ceramic capacitor should be
used to extract voltage drop across DCR. 0.1μF is a good value to start the design. CSPx and CSNx should be
connected to positive and negative terminal of the sensing device respectively. TPS51220A has an internal
current amplifier. The gain of the current amplifier, Gc, is selected by TRIP terminal. In any setting, the output
signal of the current amplifier becomes 100mV at the OCL setting point. This means that the current sensing
amplifier normalize the current information signal based on the OCL setting. Attaching a RC network
recommended even with a resistor sensing scheme to get an accurate current sensing; see the external parts
selection session for detailed configurations.

TPS51220A
ADAPTIVE ZERO CROSSING

TPS51220A has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
CURRENT PROTECTION
TPS51220A has cycle-by-cycle overcurrent limiting control. If the inductor current becomes larger than the
overcurrent trip level, TPS51220A turns off high-side MOSFET, turns on low-side MOSFET and waits for the next
clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the dc load current at overcurrent threshold, IOCL(DC), can
be calculated as follows;
I OCL(DC) + I OCL(PEAK) * 0.5 I IND(RIPPLE)
(5)
VOCL
I OCL(PEAK) +
RSENSE
where
• RSENSE is resistance of current sensing device
• V(OCL) is the overcurrent trip threshold voltage which is determined by TRIP pin voltages as shown in Table 3
(6)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down, and it ultimately crosses the undervoltage protection threshold and shutdown.
Table 3. OCL Trip and Discharge Selection

TRIP GND VREF2 VREG3 VREG5
V(OCL) (OCL TRIP VOLTAGE) V(OCL-ULV) (ULTRA-LOW VOLTAGE) V(OCL-LV) (LOW VOLTAGE)
DISCHARGE Enable Disable Disable Enable
POWERGOOD
The TPS51220A has powergood output for both switcher channels. The powergood function is activated after
softstart has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the powergood signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the powergood signal becomes low after 1.5μs internal delay. Apply voltage
should be less than 6V and the recommended pull-up resistance value is from 100kΩ to 1MΩ.
OUTPUT DISCHARGE CONTROL

The TPS51220A discharges output when ENx is low. The TPS51220A discharges outputs using an internal
MOSFET which is connected to CSNx and GND. The current capability of these MOSFETs is limited to
discharge the output capacitor slowly. If ENx becomes high during discharge, MOSFETs are turning off, and
some output voltage remains. SMPS changes over to soft-start. The PWM initiates after the target voltage
overtakes the remaining output voltage. This function can be disabled as shown in Table 3.

TPS51220A
OVERVOLTAGE/UNDERVOLTAGE PROTECTION
TPS51220A monitors the output voltage to detect overvoltage and undervoltage. When the output voltage
becomes 15% higher than the target value, the OVP comparator output goes high and the circuit latches as the
high-side MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, TPS51220A latches OFF both high-side and
low-side MOSFETs, and shuts off another channel. This UVP function is enabled after soft-start has completed.
OVP function can be disabled as shown in Table 4. The procedures for restarting from these protection states
are:
1. toggle EN
2. toggle EN1 and EN2 or
3. once hit UVLO
Table 4. FUNC Logic States

FUNC GND VREF2 VREG3 VREG5
OVP Enable Disable Enable Disable
CONTROL Current mode D-CAP mode D-CAP mode Current mode
SCHEME
UVLO PROTECTION
The TPS51220A has undervoltage lockout protections (UVLO) for VREG5, VREG3 and VREF2. When the
voltage is lower than UVLO threshold voltage, TPS51220A shuts off each output as shown inTable 5. This is
non-latch protection.
Table 5. UVLO Protection

CH1/ CH2 VREG5 VREG3 VREF2
VREG5 UVLO Off — On On
VREG3 UVLO Off Off — Off
VREF2 UVLO Off Off On —
THERMAL SHUTDOWN
The TPS51220A monitors the device temperature. If the temperature exceeds the threshold value, TPS51220A
shuts off both SMPS and 5V-LDO, and decreases the VREG3 current limitation to 5 mA (typically). This is non-
latch protection.

TPS51220A
APPLICATION INFORMATION
EXTERNAL PARTS SELECTION

A buck converter using the TPS51220A consists of linear circuits and a switching modulator. Figure 44 and
Figure 45 show basic scheme.
Voltage divider
VIN
Ramp Switching Modulator
R1
comp.
DRVH
VFB Gmv Lx
PWM Rs
Control
+ logic
R2 +
&
+ + Driver DRVL
1.0V ESR
RL
COMP Co
Cc Rgv Gmc CSP

Rgc
+
VREF +
2.0V CSN
Error Amplifier
Figure 44. Simplified Current Mode Functional Blocks
Voltage divider
VIN
Switching Modulator
Ramp
R1
comp.
DRVH
VFB Gmv Lx
PWM Rs
Control
+ logic
R2 +
+ &
+ Driver DRVL
1.0V ESR
RL
COMP Co
Rgv
VREF +
2.0V
Figure 45. Simplified D-CAP Mode Functional Blocks
The external components can be selected by following manner.

1. Determine output voltage dividing resistors. (R1 and R2: shown in Figure 44) using Equation 7 .
R1 + ǒV OUT * 1.0Ǔ R2
(7)
For D-CAP mode, recommended R2 value is from 10kΩ to 20kΩ.
2. Determine switching frequency. Higher frequency allows smaller output capacitances, however, degrade
efficiency due to increase of switching loss. Frequency setting resistor for RF-pin can be calculated by;
RF[kW] + 1 10
5
ƒ sw [kHz] (8)
TPS51220A
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
1 (VIN(TYP) - VOUT ) × VOUT
L= ×
0.33 x IOUT(MAX) x fSW VIN(TYP)
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, V(OCL), and select the sensing resistor.
The OCL trip voltage threshold is determined by TRIP pin setting. To use a larger value improves the S/N
ratio. Determine the sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX)
to 1.7 × IOUT(MAX).
VOCL
R SENSE +
I OCL(PEAK)
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500μS.
I OUT(MAX)
Rgv + 0.1 VOUT 1
I OCL(PEAK) Gmv Vdroop
(11)
I OUT(MAX) V OUT[V]
Rgv[kW] + 200
I OCL(PEAK) Vdroop[mV]
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of fo. For D-CAP mode, Rgv is used for adjusting ramp compensation. 10kΩ is
a good value to start design with. 6kΩ to 20kΩ can be chosen.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
fo, should be kept under 1/3 of the switching frequency.
Gmv Rgv ƒsw
ƒ0 + 5p I OCL(PEAK) V
1 t
OUT Co 3 (13)
Gmv Rgv
Co u 15 I OCL(PEAK) 1
p VOUT ƒsw (14)
For D-CAP mode, fo is determined by the output capacitor’s characteristics as below.
1 ƒsw
ƒ0 + t
2p ESR Co 3 (15)
Co u 3
2p ESR ƒsw (16)
For better jitter performance, a sufficient amount of feedback signal is required at VFBx pin. The
recommended signal level is approximately 30mV per tsw (switching period) of the ramping up rate, and more
than 4 mV of peak-to-peak voltage.

TPS51220A
VFB
signal
30mV
VFBRIPPLE =VoRIPPLE x 1/Vout
tSW = 1/fSW Time

Figure 46. Required voltage feedback ramp signal
7. Calculate Cc. The purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. If
ceramic capacitor(s) is used, there is no need for Cc. If a combination of different capacitors is used, attach a
RC network circuit instead of single capacitance to cancel zeros and poles caused by the output capacitors.
With single capacitance, Cc is given in Equation 17.
Cc + Co ESR
Rgv (17)
For D-CAP mode, basically Cc is not needed.
8. Choose MOSFETs Generally, the on resistance affects efficiency at high load conditions as conduction loss.
For a low output voltage application, the duty ratio is not high enough so that the on resistance of high-side
MOSFET does not affect efficiency; however, switching speed (tr and tf) affects efficiency as switching loss.
As for low-side MOSFET, the switching loss is usually not a main portion of the total loss.
RESISTOR CURRENT SENSING

For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance of resistor, this filter value is calculated using Equation 18.
Cx Rx + Lx
Rs (18)
This equation means time-constant of Cx and Rx should match the one of Lx (ESL) and Rs.
VIN
Ex-resistor
DRVH
L Lx(ESL)
Rs
Control
logic
&
Driver DRVL
Co
CSP
+
Cx Rx
CSN
Figure 47. External Resistor Current Sensing

TPS51220A
INDUCTOR DCR CURRENT SENSING

To use inductor DCR as current sensing resistor (Rs), the configuration needs to change as below. However, the
equation that must be satisfied is the same as the one for the resistor sensing.
VIN
Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
Driver DRVL
Co
Rx
CSP
+
Cx
CSN
Figure 48. Inductor DCR Current Sensing
VIN
Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
Driver DRVL
Co
Rx
CSP
+
Cx Rc
CSN
Figure 49. Inductor DCR Current Sensing With Voltage Divider
TPS51220A has fixed V(OCL) point (60 mV or 31 mV). In order to adjust for DCR, a voltage divider can be
configured a described in Figure 49.
For Rx, Rc and Cx can be calculated as shown below, and overcurrent limitation value can be calculated as
follows:
Lx
Cx × (Rx//Rc ) =
Rs (19)
I OCL(PEAK) + VOCL 1 Rx ) Rc
Rs Rc (20)
Figure 50 shows the compensation technique for the temperature drifts of the inductor DCR value. This scheme
assumes the temperature rise at the thermistor (RNTC) is directly proportional to the temperature rise at the
inductor.

TPS51220A
Inductor
Lx
Rs(DCR)
RNTC
Rx
Rc1
Rc2
CO
CSP
+
Cx
CSN
Figure 50. Inductor DCR Current Sensing With Temperature Compensate
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a PCB layout work using the TPS51220A.
Placement
• Place RC network for CSP1 and CSP2 close to the device pins.
• Place bypass capacitors for VREG5, VREG3 and VREF2 close to the device pins.
• Place frequency-setting resistor close to the device pin.
• Place the compensation circuits for COMP1 and COMP2 close to the device pins.
• Place the voltage setting resistors close to the device pins, especially when D-CAP mode is chosen.
Routing (sensitive analog portion)
• Use separate traces for; see Figure 51
– Output voltage sensing from current sensing (negative-side)
– Output voltage sensing from V5SW input (when VOUT = 5V)
– Current sensing (positive-side) from switch-node
V5SW
R1
VFB
R2
H-FET Inductor
Vout
SW
L-FET
Cout
R
CSP
C
CSN
Figure 51. Sensing Trace Routings
• Use Kelvin sensing traces from the solder pads of the current sensing device (inductor or resistor) to current

TPS51220A
sensing comparator inputs (CSPx and CSNx). (See Figure 52)

Current sensing
Device
RC network
next to IC
Figure 52. Current Sensing Traces
• Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling
• Connect VFB resistor trace to the positive node of the output capacitor.
• Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog
components. Placing a signal GND plane (underneath the IC, and fully covered peripheral components) on
the internal layer for shielding purpose is recommended. (See Figure 53)
• Use a thermal land for PowerPAD™. Five or more vias, with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane, should be used to help dissipation. Do NOT connect the GND-pin to
this thermal land on the surface layer, underneath the package.
Routing (power portion)
• Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive, and keep them away from DRVL.
• Connect SW trace to source terminal of the high-side MOSFET.
• Use power GND for VREG5, VIN and VOUT capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the device GND terminal. (See Figure 53)
0W resistor
GND
#28
GND-pin
To inner To inner
Power-GND Signal-GND
layer plane
Inner Signal-GND plane
Figure 53. GND Layout Example

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VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
APPLICATION CIRCUITS
C14 R16 10mF R26 C24

L1 0.1m F 4.7W 4.7W 0.1 mF L2
PGND PGND
VO1 VO2
Q12 PGND
5.0V/8A 3.3V/8A
PGND GND
Q22
C11 C21
32 31 30 29 28 27 26 25
Copyright © 2008–2013, Texas Instruments Incorporated

PGND PGND PGND PGND
SW 1
SW 2
GN D
1 24
V BS T 1
V BS T2
DR V L1
DR V L2
VR EG5
DRVH1 DRVH2
R01
300k W
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2 mF
TPS51220ARTV
(QFN32)
GND

R14 R24
7.5k W PowerPAD 6.8k W
7 CSP1 CSP2 18
R15 C13 C23 R25
4.3k W 0.1mF CSN1 0.1 mF 4.3k W

8
CSN2 17
V F B1
CO M P 1
FU NC
EN
V R E F2
TR IP
CO MP 2
V FB 2
EN
9 10 11 12 13 14 15 16
GND
VREG5
VREF2 R21
62k W
VO1 C02 VO2
R13 0.22 mF
GND R11 R12 R23 C25 R22
120k W C15 18k W
30k W 12k W 220p F 27k W
100p F
VREF2
GND VREF2
GND GND
Figure 54. Current Mode, DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz
Submit Documentation Feedback

SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013
35
TPS51220A
TPS51220A
Table 6. Current Mode, DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz

SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
C11 2 × 330 μF, 6.3 V, 18 mΩ Sanyo 6TPE330MIL
C12 2 × 10 μF, 25 V Murata GRM32DR71E106K
C21 470 μF, 4.0V, 15 mΩ Sanyo 4TPE470MFL
L1 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M
Q11, Q21 30-V, 12 A, 10.5 mΩ Fairchild FDMS8692
Q12, Q22 30 V, 18 A, 5.4 mΩ Fairchild FDMS8672AS

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VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
C14 R16 10mF R26 C24
L1 0.1m F 4.7W 4.7W 0.1 mF L2
PGND PGND
VO1 VO2
Q12 PGND
5.0V/8A 3.3V/8A
PGND GND
Q22
C11 C21
32 31 30 29 28 27 26 25

PGND PGND PGND PGND
SW 1
SW 2
GN D
1 24
V BS T 1
V BS T2
DR V L1
DR V L2
VR EG5
DRVH1 DRVH2
R01
300k W
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2 mF
TPS51220ARTV
(QFN32)
GND

R14 R24
7 CSP1 CSP2 18
R15 C13 C23 R25
4.3k W 0.1mF CSN1 0.1 mF 4.3k W

8
CSN2 17
V F B1
CO M P 1
FU NC
EN
V R E F2
TR IP
CO MP 2
V FB 2
EN
9 10 11 12 13 14 15 16
GND
VREG5
VREF2 R21
R13 62k W
VO1 C02 VO2
10k W 0.22 mF R23
GND R11 R12
9.1k W
R22
120k W 30k W 27k W
C25
C15 1.8n F
GND
1.8n F
VREF2 VREF2
GND GND
Figure 55. Current Mode (Non-Droop), DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz

37
TPS51220A
TPS51220A
Table 7. Current Mode (Non-droop), DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz

C11 2 x 330 μF, 6.3 V 18 mΩ Sanyo 6TPE330MIL
C12 2 x 10 μF, 25 V Murata GRM32DR71E106K
Q11, Q21 30-V, 12-A, 10.5 mΩ Fairchild FDMS8692
Q12, Q22 30-V, 18-A, 5.4 mΩ Fairchild FDMS8672AS

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VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
C14 R16 10mF R26 C24
L1 0.1m F 4.7W 4.7W 0.1 mF L2
PGND PGND
VO1 VO2
Q12 PGND
5.0V/8A 3.3V/8A
PGND GND
Q22
C11 C21
32 31 30 29 28 27 26 25

PGND PGND PGND PGND
SW 1
SW 2
GN D
1 24
V BS T 1
V BS T2
DR V L1
DR V L2
VR EG5
DRVH1 DRVH2
R01
300k W
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2 mF
TPS51220ARTV
(QFN32)
GND

R14 R24
7 CSP1 CSP2 18
R15 C13 C23 R25
4.3k W 0.1mF CSN1 0.1 mF 4.3k W

8
CSN2 17
V F B1
CO M P 1
FU NC
EN
V R E F2
TR IP
CO MP 2
V FB 2
EN
9 10 11 12 13 14 15 16
GND
VREG5
VREF2 R21
VREG3
62k W
VO1 C02 VO2
R13 0.22 mF
R11 R12 R23 R22
120k W 10k W
30k W 10k W 27k W
VREF2
GND VREF2
GND GND
Figure 56. D-CAP Mode, DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz

39
TPS51220A
TPS51220A
Table 8. D-CAP Mode, DCR Sensing, 5-V/ 8-A, 3.3-V/8-A, 330-kHz

C11 2 x 330 μF, 6.3 V, 18 mΩ Sanyo 6TPE330MIL
Q11, Q21 30 V, 12 A, 10.5 mΩ Fairchild FDMS8692
Q12, Q22 30 V, 18 A, 5.4 mΩ Fairchild FDMS8672AS

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VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
C14 R16 10mF R26 C24
L1 0.1m F 4.7W 4.7W 0.1 mF L2
PGND PGND
VO1 VO2
Q12 PGND
5.0V/5A 3.3V/5A
PGND GND
Q22
C11 C21
32 31 30 29 28 27 26 25

PGND PGND PGND PGND
SW 1
SW 2
GN D
1 24
V BS T 1
V BS T2
DR V L1
DR V L2
VR EG5
DRVH1 DRVH2
R01
330k W
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2 mF
TPS51220ARTV
(QFN32)
GND

R14 R24
7 CSP1 CSP2 18
R15 C13 C23 R25
56k W 0.1mF CSN1 0.1 mF 56k W

8
CSN2 17
V F B1
CO M P 1
FU NC
EN
V R E F2
TR IP
CO MP 2
V FB 2
EN
9 10 11 12 13 14 15 16
GND
VREG5
VREF2 R21
62k W
VO1 C02 VO2
R13 0.22 mF
GND R11 R12 R23 C25 R22
120k W C15 10k W
30k W 10k W 220p F 27k W
100p F
VREF2
GND VREF2
GND GND
Figure 57. Current Mode, DCR Sensing, 5-V/5-A, 3.3-V/5-A, 300-kHz

41
TPS51220A
TPS51220A
Table 9. Current Mode, DCR Sensing, 5-V/5-A, 3.3-V/5-A, 300-kHz

C11 2 × 120 μF, 6.3V, 15 mΩ Panasonic EEFCX0J121R
C21 2 × 220 μF, 4.0 V, 15 mΩ Panasonic EEFCX0G221R
L1 4.0 μH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H
L2 4.0 μH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H
Q11, Q21 30 V, 13.6 A, 9.5 mΩ IR IRF7821
Q12, Q22 30 V, 13.8 A, 5.8 mΩ IR IRF8113
REVISION HISTORY
Changes from Original (December 2008) to Revision A Page
• Changed t(SSDYL) - SoftStart Delay Typical value From: 140 To: 200 ................................................................................... 5
• Changed t(SS) - SoftStart Delay Typical value From: 800 To 960 ......................................................................................... 5
Changes from Revision A (March 2009) to Revision B Page
• Changed SW1 and SW2 Abs Max range From: –5 to 34 To: –7 to 34 ................................................................................ 3
• Changed DRVH1, DRVH2 Abs Max range From: –5 to 39 To: –7 to 39 ............................................................................. 3
• Added a row to the Recommended Operating Conditions table - DRVH1, DRVH2 (negative overshoot -6 V for t <
20% duration of the switching period) .................................................................................................................................. 3
• Added a row to the Recommended Operating Conditions table - SW1, SW2 (negative overshoot -6 V for t < 20%
duration of the switching period ............................................................................................................................................ 3
• Changed the legend of Figure 22 From: VI = 12 V To: Auto-Skip ...................................................................................... 14
• Changed the legend of Figure 27 From RGV = 1 kΩ To: RGV = 10 k .................................................................................. 16
• Changed the time scale of Figure 36 From: 1 mec/div To: 10msec/div ............................................................................. 19
• Changed the time scale of Figure 37 From: 1 mec/div To: 10msec/div ............................................................................. 19
• Added subsection: 180 Degrees Phase Shift and Blanking Time ...................................................................................... 23
Changes from Revision B (October 2009) to Revision C Page
• Added RSN dissipation rating information ............................................................................................................................ 3

• Added RSN package ordering information ........................................................................................................................... 4
• Added RSN package electrical specifications ...................................................................................................................... 6
• Added the RSN package pinout ........................................................................................................................................... 8
Changes from Revision C (November 2009) to Revision D Page
• Changed the device number in the pin package drawings From: TPS51120A To: TPS51220A ......................................... 8
Changes from Revision D (FEBRUARY 2010) to Revision E Page
• Added DRVH1 and DRVH2 parameters to ABSOLUTE MAXIMUM RATINGS table. ......................................................... 3
• Added DRVL1 and DRVL2 parameters to ABSOLUTE MAXIMUM RATINGS table. .......................................................... 3

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS51220ARSNR ACTIVE QFN RSN 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
51220A
TPS51220ARSNT ACTIVE QFN RSN 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
51220A
TPS51220ARTVR ACTIVE WQFN RTV 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
51220A
TPS51220ARTVT ACTIVE WQFN RTV 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
51220A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS51220A :
• Automotive: TPS51220A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51220ARSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS51220ARSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS51220ARSNT QFN RSN 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS51220ARSNT QFN RSN 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS51220ARTVR WQFN RTV 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS51220ARTVR WQFN RTV 32 3000 330.0 12.4 5.25 5.25 1.1 8.0 12.0 Q2
TPS51220ARTVT WQFN RTV 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS51220ARTVT WQFN RTV 32 250 180.0 12.5 5.25 5.25 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51220ARSNR QFN RSN 32 3000 367.0 367.0 35.0
TPS51220ARSNR QFN RSN 32 3000 367.0 367.0 35.0
TPS51220ARSNT QFN RSN 32 250 210.0 185.0 35.0
TPS51220ARSNT QFN RSN 32 250 210.0 185.0 35.0
TPS51220ARTVR WQFN RTV 32 3000 367.0 367.0 35.0
TPS51220ARTVR WQFN RTV 32 3000 338.0 355.0 50.0
TPS51220ARTVT WQFN RTV 32 250 210.0 185.0 35.0
TPS51220ARTVT WQFN RTV 32 250 338.0 355.0 50.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032E SCALE 3.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.15 B
A
4.85
PIN 1 INDEX AREA
5.15
4.85
SIDE WALL LEAD

METAL THICKNESS
0.8 DIM A
0.7 OPTION 1 OPTION 2
C 0.1 0.2
SEATING PLANE
0.05
0.00 0.08 C
2X 3.5 (DIM A) TYP
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17
2X SYMM
33
3.5
0.30
32X
0.18
24 0.1 C A B
1
0.05 C
PIN 1 ID
(OPTIONAL) 32 25
SYMM
0.5
32X
0.3
4225196/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTV0032E WQFN - 0.8 mm max height
( 3.45)
SYMM
32 25
32X (0.6)
1 24
32X (0.24)
(1.475)
28X (0.5)
33 SYMM
(4.8)
( 0.2) TYP
VIA
8 17
(R0.05)
TYP
9 16
(1.475)
(4.8)
LAND PATTERN EXAMPLE

SCALE:18X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4225196/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032E WQFN - 0.8 mm max height
4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)
1 24
32X (0.24)
28X (0.5)
(0.845)
SYMM
33
(4.8)
8 17
METAL
TYP
9 16
SYMM
(4.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225196/A 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013

TYPICAL APPLICATION CIRCUIT

PGND PGND PGND

GND EN1 4 EN1 EN2 21 EN2

GND GND GND

FUNCTIONAL BLOCK DIAGRAM

4.7V/ 4.5V + + 1.25V + + 4.7V/ 4.5V

1V -30% + 1V - 5%/ 10%

Channel-1 Switcher shown

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ABSOLUTE MAXIMUM RATINGS (1)

DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)

RECOMMENDED OPERATING CONDITIONS

Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

V5SW current, TA = 25°C, No Load, TRIP = 5 V 0.8 mA

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ELECTRICAL CHARACTERISTICS (continued)

(2) Specified by design. Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

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ELECTRICAL CHARACTERISTICS (continued)

(3) Specified by design. Not production tested.

Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7

RSN PACKAGE RTV PACKAGE

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PIN FUNCTIONS (continued)

Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9

IVINSDN -– Shutdown Current – mA

VI – Input Voltage – V TJ – Junction Temperature – °C

INPUT VOLTAGE STANDBY CURRENT INPUT VOLTAGE STANDBY CURRENT

IVINSTBY – Standby Current – mA

TJ – Junction Temperature – °C VI – Input Voltage – V

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TYPICAL CHARACTERISTICS (continued)

IVBAT – Battery Current – mA

VI – Input Voltage – V VI – Input Voltage – V

BATTERY CURRENT VREF2 OUTPUT VOLTAGE

VI – Input Voltage – V IVREF2 – VREF2 Output Current – mA

Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11

TYPICAL CHARACTERISTICS (continued)

VVREG5 – 5-V Linear Regulator Output Voltage – V

Figure 9. Figure 10.

SWITCHING FREQUENCY FORWARD VOLTAGE OF BOOST SW

TJ – Junction Temperature – °C TJ – Junction Temperature – °C

Figure 11. Figure 12.

12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated

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TYPICAL CHARACTERISTICS (continued)

IBSTLK – VBST Leakage Current – mA

TJ – Junction Temperature – °C TJ – Junction Temperature – °C

Figure 13. Figure 14.

CURRENT LIMIT THRESHOLD CURRENT LIMIT THRESHOLD