COMPUTER ORGANIZATION AND DESIGN 6th

Edition
The Hardware/Software Interface

Chapter 2
Instructions: Language
of the Computer
 §2.1 Introduction
Instruction Set
◼ The repertoire of instructions of a
computer
◼ Different computers have different
instruction sets
◼ But with many aspects in common
◼ Early computers had very simple
instruction sets
◼ Simplified implementation
◼ Many modern computers also have simple
instruction sets

Chapter 2 — Instructions: Language of the Computer — 2

The MIPS Instruction Set
◼ Used as the example throughout the book
◼ Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
◼ Typical of many modern ISAs
◼ See MIPS Reference Data tear-out card, and
Appendixes B and E
◼ Similar ISAs have a large share of embedded
core market
◼ Applications in consumer electronics, network/storage
equipment, cameras, printers, …

Chapter 2 — Instructions: Language of the Computer — 3

Stored Program Computers
The BIG Picture ◼ Instructions represented in
binary, just like data
◼ Instructions and data stored
in memory
◼ Programs can operate on
programs
◼ e.g., compilers, linkers, …
◼ Binary compatibility allows
compiled programs to work
on different computers
◼ Standardized ISAs

Chapter 2 — Instructions: Language of the Computer — 4

Other instruction sets
◼ Easy to pick up other instruction sets.
◼ Three other popular instruction sets.
1. ARMv7 (similar to MIPS). More than 100 billion chips with
ARM processors manufactured between 2017 and 2020
2. Intel x86, which powers both the PC and the cloud of
the PostPC Era.
3. ARMv8, which extends the address size of the
ARMv7 from 32 bits to 64 bits. Ironically, it is closer
to MIPS than it is to ARMv7.

Chapter 2 — Instructions: Language of the Computer — 5

 MIPS-32 ISA
Registers
❑ Instruction Categories
⚫ Computational
R0 - R31
⚫ Load/Store
⚫ Jump and Branch
⚫ Floating Point
- coprocessor PC
⚫ Memory Management HI
LO
3 Instruction Formats: all 32 bits wide

op rs rt rd sa funct
R format
op rs rt immediate
I format
op jump target
J format
 §2.2 Operations of the Computer Hardware
Arithmetic Operations
◼ Add and subtract, three operands
◼ Two sources and one destination
add a, b, c # a gets b + c
◼ All arithmetic operations have this form
◼ Design Principle 1: Simplicity favors
regularity
◼ Regularity makes implementation simpler
◼ Simplicity enables higher performance at
lower cost

Chapter 2 — Instructions: Language of the Computer — 7

Arithmetic Example
◼ C code:
f = (g + h) - (i + j);

◼ Compiled MIPS code:

add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1

Chapter 2 — Instructions: Language of the Computer — 8

 §2.3 Operands of the Computer Hardware
Register Operands
◼ Arithmetic instructions use register
operands
◼ MIPS has a 32 × 32-bit register file
◼ Use for frequently accessed data
◼ Numbered 0 to 31
◼ 32-bit data called a “word”
◼ Assembler names
◼ $t0, $t1, …, $t9 for temporary values
◼ $s0, $s1, …, $s7 for saved variables
◼ Design Principle 2: Smaller is faster
◼ c.f. main memory: millions of locations

Chapter 2 — Instructions: Language of the Computer — 9

Register Operand Example
◼ C code:
f = (g + h) - (i + j);
◼ f, …, j in $s0, …, $s4

◼ Compiled MIPS code:

add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

Chapter 2 — Instructions: Language of the Computer — 10

Memory Operands
◼ Main memory used for composite data
◼ Arrays, structures, dynamic data
◼ To apply arithmetic operations
◼ Load values from memory into registers
◼ Store result from register to memory
◼ Memory is byte addressed
◼ Each address identifies an 8-bit byte
◼ Words are aligned in memory
◼ Address must be a multiple of 4
◼ MIPS is Big Endian
◼ Most-significant byte at least address of a word
◼ c.f. Little Endian: least-significant byte at least address

Chapter 2 — Instructions: Language of the Computer — 11

Memory Operand Example 1
◼ C code:
g = h + A[8];
◼ g in $s1, h in $s2, base address of A in $s3

◼ Compiled MIPS code:

◼ Index 8 requires offset of 32
◼ 4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0
offset base register

Chapter 2 — Instructions: Language of the Computer — 12

Memory Operand Example 2
◼ C code:
A[12] = h + A[8];
◼ h in $s2, base address of A in $s3

◼ Compiled MIPS code:

◼ Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word

Chapter 2 — Instructions: Language of the Computer — 13

Registers vs. Memory
◼ Registers are faster to access than
memory
◼ Operating on memory data requires loads
and stores
◼ More instructions to be executed
◼ Compiler must use registers for variables
as much as possible
◼ Only spill to memory for less frequently used
variables
◼ Register optimization is important!

Chapter 2 — Instructions: Language of the Computer — 14

Immediate Operands
◼ Constant data specified in an instruction
addi $s3, $s3, 4
◼ No subtract immediate instruction
◼ Just use a negative constant
addi $s2, $s1, -1
◼ Design Principle 3: Make the common
case fast
◼ Small constants are common
◼ Immediate operand avoids a load instruction

Chapter 2 — Instructions: Language of the Computer — 15

The Constant Zero
◼ MIPS register 0 ($zero) is the constant 0
◼ Cannot be overwritten
◼ Useful for common operations
◼ E.g., move between registers
add $t2, $s1, $zero

Chapter 2 — Instructions: Language of the Computer — 16

Sign Extension
◼ Representing a number using more bits
◼ Preserve the numeric value
◼ In MIPS instruction set
◼ addi: extend immediate value
◼ lb, lh: extend loaded byte/halfword
◼ beq, bne: extend the displacement
◼ Replicate the sign bit to the left
◼ c.f. unsigned values: extend with 0s
◼ Examples: 8-bit to 16-bit
◼ +2: 0000 0010 => 0000 0000 0000 0010
◼ –2: 1111 1110 => 1111 1111 1111 1110

Chapter 2 — Instructions: Language of the Computer — 17

 §2.5 Representing Instructions in the Computer
Representing Instructions
◼ Instructions are encoded in binary
◼ Called machine code
◼ MIPS instructions
◼ Encoded as 32-bit instruction words
◼ Small number of formats encoding operation code
(opcode), register numbers, …
◼ Regularity!
◼ Register numbers
◼ $t0 – $t7 are reg’s 8 – 15
◼ $t8 – $t9 are reg’s 24 – 25
◼ $s0 – $s7 are reg’s 16 – 23

Chapter 2 — Instructions: Language of the Computer — 18

Hexadecimal
◼ Base 16
◼ Compact representation of bit strings
◼ 4 bits per hex digit

0 0000 4 0100 8 1000 C 1100

1 0001 5 0101 9 1001 D 1101
2 0010 6 0110 A 1010 E 1110
3 0011 7 0111 B 1011 F 1111

◼ Example: ECA86420
◼ 1110 1100 1010 1000 0110 0100 0010 0000

Chapter 2 — Instructions: Language of the Computer — 19

MIPS R-format Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

◼ Instruction fields
◼ op: operation code (opcode)
◼ rs: first source register number
◼ rt: second source register number
◼ rd: destination register number
◼ shamt: shift amount (00000 for now)
◼ funct: function code (extends opcode)

Chapter 2 — Instructions: Language of the Computer — 20

R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32 decimal

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

Chapter 2 — Instructions: Language of the Computer — 21

MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

◼ Immediate arithmetic and load/store instructions

◼ rt: destination or source register number
◼ Constant: –215 to +215 – 1
◼ Address: offset added to base address in rs
◼ Design Principle 4: Good design demands good
compromises
◼ Different formats complicate decoding, but allow 32-bit
instructions uniformly
◼ Keep formats as similar as possible

Chapter 2 — Instructions: Language of the Computer — 22

MIPS I-format (Immediate) Instructions

op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

◼ Immediate arithmetic and load/store instructions

◼ rt: destination or source register number
◼ Constant: –215 to +215 – 1
◼ Address: offset added to base address in rs
◼ Design Principle 4: Good design demands good
compromises
◼ Different formats complicate decoding, but allow 32-bit
instructions uniformly
◼ Keep formats as similar as possible
Translating MIPS Assembly Language into
Machine Language
A[300] = h + A[300];
is compiled into

lw $t0,1200($t1) # Temporary reg $t0 gets A[300]

add $t0,$s2,$t0 # Temporary reg $t0 gets h + A[300]
sw $t0,1200($t1) # Stores h + A[300] back into A[300]

What is the MIPS machine language code for these three

instructions?
Lw: op 35, rs: 9 for ($t1), rt: 8 ($t0),
The offset to select A[300] (1200 300 4) is found in the final field (address).
Add: 0 for (op) and 32 for (funct). The three register operands (18, 8, and 8)
are found in the second, third, and fourth fields and correspond to $s2, $t0,
and $t0.
sw is 43 as op. The rest of this final instruction is identical to the lw instruction
 §2.6 Logical Operations
Logical Operations
◼ Instructions for bitwise manipulation
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor

◼ Useful for extracting and inserting

groups of bits in a word
Chapter 2 — Instructions: Language of the Computer — 27
Shift Operations
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

◼ shamt: how many positions to shift

◼ Shift left logical
◼ Shift left and fill with 0 bits
◼ sll by i bits multiplies by 2i
◼ Shift right logical
◼ Shift right and fill with 0 bits
◼ srl by i bits divides by 2i (unsigned only)

Chapter 2 — Instructions: Language of the Computer — 28

AND Operations
◼ Useful to mask bits in a word
◼ Select some bits, clear others to 0
and $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 0000 0000 0000 0000 0000 1100 0000 0000

Chapter 2 — Instructions: Language of the Computer — 29

OR Operations
◼ Useful to include bits in a word
◼ Set some bits to 1, leave others unchanged
or $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 0000 0000 0000 0000 0011 1101 1100 0000

Chapter 2 — Instructions: Language of the Computer — 30

NOT Operations
◼ Useful to invert bits in a word
◼ Change 0 to 1, and 1 to 0
◼ MIPS has NOR 3-operand instruction
◼ a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero Register 0: always
read as zero

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 1111 1111 1111 1111 1100 0011 1111 1111

Chapter 2 — Instructions: Language of the Computer — 31

 §2.7 Instructions for Making Decisions
Conditional Operations
◼ Branch to a labeled instruction if a
condition is true
◼ Otherwise, continue sequentially
◼ beq rs, rt, L1
◼ if (rs == rt) branch to instruction labeled L1;
◼ bne rs, rt, L1
◼ if (rs != rt) branch to instruction labeled L1;
◼ j L1
◼ unconditional jump to instruction labeled L1

Chapter 2 — Instructions: Language of the Computer — 32

Compiling If Statements
◼ C code:
if (i==j) f = g+h;
else f = g-h;
◼ f, g, … in $s0, $s1, …
◼ Compiled MIPS code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: …
Assembler calculates addresses

Chapter 2 — Instructions: Language of the Computer — 33

Compiling Loop Statements
◼ C code:
while (save[i] == k) i += 1;
◼ i in $s3, k in $s5, address of save in $s6
◼ Compiled MIPS code:
Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit: …
J is unconditional branch

Chapter 2 — Instructions: Language of the Computer — 34

More Conditional Operations
◼ Set result to 1 if a condition is true
◼ Otherwise, set to 0
◼ slt rd, rs, rt
◼ if (rs < rt) rd = 1; else rd = 0;
◼ slti rt, rs, constant
◼ if (rs < constant) rt = 1; else rt = 0;
◼ Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L

Chapter 2 — Instructions: Language of the Computer — 35

Branch Instruction Design
◼ Why not blt, bge, etc?
◼ Hardware for <, ≥, … slower than =, ≠
◼ Combining with branch involves more work
per instruction, requiring a slower clock
◼ All instructions penalized!
◼ beq and bne are the common case
◼ This is a good design compromise

Chapter 2 — Instructions: Language of the Computer — 36

Signed vs. Unsigned
◼ Signed comparison: slt, slti
◼ Unsigned comparison: sltu, sltui
◼ Example
◼ $s0 = 1111 1111 1111 1111 1111 1111 1111 1111
◼ $s1 = 0000 0000 0000 0000 0000 0000 0000 0001
◼ slt $t0, $s0, $s1 # signed
◼ –1 < +1  $t0 = 1
◼ sltu $t0, $s0, $s1 # unsigned
◼ +4,294,967,295 > +1  $t0 = 0

Chapter 2 — Instructions: Language of the Computer — 37

Byte/Halfword Operations
◼ Could use bitwise operations
◼ MIPS byte/halfword load/store
◼ String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)
◼ Sign extend to 32 bits in rt
lbu rt, offset(rs) lhu rt, offset(rs)
◼ Zero extend to 32 bits in rt
sb rt, offset(rs) sh rt, offset(rs)
◼ Store just rightmost byte/halfword

Chapter 2 — Instructions: Language of the Computer — 38

 §2.8 Supporting Procedures in Computer Hardware
Procedure Calling
◼ Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call

Chapter 2 — Instructions: Language of the Computer — 39

Register Usage
◼ $a0 – $a3: arguments (reg’s 4 – 7)
◼ $v0, $v1: result values (reg’s 2 and 3)
◼ $t0 – $t9: temporaries
◼ Can be overwritten by callee
◼ $s0 – $s7: saved
◼ Must be saved/restored by callee
◼ $gp: global pointer for static data (reg 28)
◼ $sp: stack pointer (reg 29)
◼ $fp: frame pointer (reg 30)
◼ $ra: return address (reg 31)

Chapter 2 — Instructions: Language of the Computer — 40

Procedure Call Instructions
◼ Procedure call: jump and link
jal ProcedureLabel
◼ Address of following instruction put in $ra

◼ Jumps to target address

◼ Procedure return: jump register

jr $ra
◼ Copies $ra to program counter

◼ Can also be used for computed jumps

◼ e.g., for case/switch statements

Chapter 2 — Instructions: Language of the Computer — 41

Leaf Procedure Example
◼ C code:
int leaf_example (int g, h, i, j)
{ int f;
f = (g + h) - (i + j);
return f;
}
◼ Arguments g, …, j in $a0, …, $a3

◼ f in $s0 (hence, need to save $s0 on stack)

◼ Result in $v0

Chapter 2 — Instructions: Language of the Computer — 42

Leaf Procedure Example
◼ MIPS code:
leaf_example:
addi $sp, $sp, -4
Save $s0 on stack
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3 Procedure body
sub $s0, $t0, $t1
add $v0, $s0, $zero Result
lw $s0, 0($sp) Restore $s0
addi $sp, $sp, 4
jr $ra Return

Chapter 2 — Instructions: Language of the Computer — 43

Non-Leaf Procedures
◼ Procedures that call other procedures
◼ For nested call, caller needs to save on the
stack:
◼ Its return address
◼ Any arguments and temporaries needed after
the call
◼ Restore from the stack after the call

Chapter 2 — Instructions: Language of the Computer — 44

Non-Leaf Procedure Example
◼ C code:
int fact (int n)
{
if (n < 1) return f;
else return n * fact(n - 1);
}
◼ Argument n in $a0

◼ Result in $v0

Chapter 2 — Instructions: Language of the Computer — 45

Non-Leaf Procedure Example
◼ MIPS code:
fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return

Chapter 2 — Instructions: Language of the Computer — 46

Local Data on the Stack

◼ Local data allocated by callee

◼ e.g., C automatic variables
◼ Procedure frame (activation record)
◼ Used by some compilers to manage stack storage
Chapter 2 — Instructions: Language of the Computer — 47
Memory Layout
◼ Text: program code
◼ Static data: global
variables
◼ e.g., static variables in C,
constant arrays and strings
◼ $gp initialized to address
allowing ±offsets into this
segment
◼ Dynamic data: heap
◼ E.g., malloc in C, new in
Java
◼ Stack: automatic storage

Chapter 2 — Instructions: Language of the Computer — 48

 §2.9 Communicating with People
Character Data
◼ Byte-encoded character sets
◼ ASCII: 128 characters
◼ 95 graphic, 33 control
◼ Latin-1: 256 characters
◼ ASCII, +96 more graphic characters
◼ Unicode: 32-bit character set
◼ Used in Java, C++ wide characters, …
◼ Most of the world’s alphabets, plus symbols
◼ UTF-8, UTF-16: variable-length encodings

Chapter 2 — Instructions: Language of the Computer — 49

Byte/Halfword Operations
◼ Could use bitwise operations
◼ MIPS byte/halfword load/store
◼ String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)
◼ Sign extend to 32 bits in rt
lbu rt, offset(rs) lhu rt, offset(rs)
◼ Zero extend to 32 bits in rt
sb rt, offset(rs) sh rt, offset(rs)
◼ Store just rightmost byte/halfword

Chapter 2 — Instructions: Language of the Computer — 50

String Copy Example
◼ C code (naïve):
◼ Null-terminated string
void strcpy (char x[], char y[])
{ int i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
◼ Addresses of x, y in $a0, $a1

◼ i in $s0

Chapter 2 — Instructions: Language of the Computer — 51

String Copy Example
◼ MIPS code:
strcpy:
addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
add $s0, $zero, $zero # i = 0
L1: add $t1, $s0, $a1 # addr of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # addr of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 # i = i + 1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return

Chapter 2 — Instructions: Language of the Computer — 52

 §2.10 MIPS Addressing for 32-Bit Immediates and Addresses
32-bit Constants
◼ Most constants are small
◼ 16-bit immediate is sufficient
◼ For the occasional 32-bit constant
lui rt, constant
◼ Copies 16-bit constant to left 16 bits of rt
◼ Clears right 16 bits of rt to 0

lhi $s0, 61 0000 0000 0111 1101 0000 0000 0000 0000

ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000

Chapter 2 — Instructions: Language of the Computer — 53

Branch Addressing
◼ Branch instructions specify
◼ Opcode, two registers, target address
◼ Most branch targets are near branch
◼ Forward or backward

op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

◼ PC-relative addressing
◼ Target address = PC + offset × 4
◼ PC already incremented by 4 by this time
Chapter 2 — Instructions: Language of the Computer — 54
Jump Addressing
◼ Jump (j and jal) targets could be
anywhere in text segment
◼ Encode full address in instruction

op address
6 bits 26 bits

◼ (Pseudo)Direct jump addressing

◼ Target address = PC31…28 : (address × 4)

Chapter 2 — Instructions: Language of the Computer — 55

Target Addressing Example
◼ Loop code from earlier example
◼ Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: … 80024

Chapter 2 — Instructions: Language of the Computer — 56

Addressing Mode Summary

Chapter 2 — Instructions: Language of the Computer — 57

 §2.12 Translating and Starting a Program
Translation and Startup

Many compilers produce

object modules directly

Static linking

Chapter 2 — Instructions: Language of the Computer — 60

Producing an Object Module
◼ Assembler (or compiler) translates program into
machine instructions
◼ Provides information for building a complete
program from the pieces
◼ Header: described contents of object module
◼ Text segment: translated instructions
◼ Static data segment: data allocated for the life of the
program
◼ Relocation info: for contents that depend on absolute
location of loaded program
◼ Symbol table: global definitions and external refs
◼ Debug info: for associating with source code

Chapter 2 — Instructions: Language of the Computer — 61

Linking Object Modules
◼ Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3. Patch location-dependent and external refs
◼ Could leave location dependencies for
fixing by a relocating loader
◼ But with virtual memory, no need to do this
◼ Program can be loaded into absolute location
in virtual memory space

Chapter 2 — Instructions: Language of the Computer — 62

Loading a Program
◼ Load from image file on disk into memory
1. Read header to determine segment sizes
2. Create virtual address space
3. Copy text and initialized data into memory
◼ Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including $sp, $fp, $gp)
6. Jump to startup routine
◼ Copies arguments to $a0, … and calls main
◼ When main returns, do exit syscall

Chapter 2 — Instructions: Language of the Computer — 63

Dynamic Linking
◼ Only link/load library procedure when it is
called
◼ Requires procedure code to be relocatable
◼ Avoids image bloat caused by static linking of
all (transitively) referenced libraries
◼ Automatically picks up new library versions

Chapter 2 — Instructions: Language of the Computer — 64

 Starting Java Applications

Simple portable
instruction set for
the JVM

Compiles
Interprets
bytecodes of
bytecodes
“hot” methods
into native
code for host
machine

Chapter 2 — Instructions: Language of the Computer — 65

 Effect of Compiler Optimization
Compiled with gcc for Pentium 4 under Linux

3 Relative Performance 140000 Instruction count

2.5 120000
100000
2
80000
1.5
60000
1
40000
0.5 20000
0 0
none O1 O2 O3 none O1 O2 O3

180000 Clock Cycles 2 CPI

160000
140000 1.5
120000
100000
1
80000
60000
40000 0.5
20000
0 0
none O1 O2 O3 none O1 O2 O3

Chapter 2 — Instructions: Language of the Computer — 66

Effect of Language and Algorithm
3 Bubblesort Relative Performance
2.5

1.5

0.5

0
C/none C/O1 C/O2 C/O3 Java/int Java/JIT

2.5 Quicksort Relative Performance

2

1.5

0.5

0
C/none C/O1 C/O2 C/O3 Java/int Java/JIT

3000 Quicksort vs. Bubblesort Speedup

2500

2000

1500

1000

500

0
C/none C/O1 C/O2 C/O3 Java/int Java/JIT

Chapter 2 — Instructions: Language of the Computer — 67

Lessons Learnt
◼ Instruction count and CPI are not good
performance indicators in isolation
◼ Compiler optimizations are sensitive to the
algorithm
◼ Java/JIT compiled code is significantly
faster than JVM interpreted
◼ Comparable to optimized C in some cases
◼ Nothing can fix a dumb algorithm!

Chapter 2 — Instructions: Language of the Computer — 68

 §2.16 Real Stuff: ARMv7 (32-bit) Instructions
ARM & MIPS Similarities
◼ ARM: the most popular embedded core
◼ Similar basic set of instructions to MIPS
ARM MIPS
Date announced 1985 1985
Instruction size 32 bits 32 bits
Address space 32-bit flat 32-bit flat
Data alignment Aligned Aligned
Data addressing modes 9 3
Registers 15 × 32-bit 31 × 32-bit
Input/output Memory Memory
mapped mapped

Chapter 2 — Instructions: Language of the Computer — 69

 §2.19 Real Stuff: x86 Instructions
The Intel x86 ISA
◼ Evolution with backward compatibility
◼ 8080 (1974): 8-bit microprocessor
◼ Accumulator, plus 3 index-register pairs
◼ 8086 (1978): 16-bit extension to 8080
◼ Complex instruction set (CISC)
◼ 8087 (1980): floating-point coprocessor
◼ Adds FP instructions and register stack
◼ 80286 (1982): 24-bit addresses, MMU
◼ Segmented memory mapping and protection
◼ 80386 (1985): 32-bit extension (now IA-32)
◼ Additional addressing modes and operations
◼ Paged memory mapping as well as segments

Chapter 2 — Instructions: Language of the Computer — 70

The Intel x86 ISA
◼ Further evolution…
◼ i486 (1989): pipelined, on-chip caches and FPU
◼ Compatible competitors: AMD, Cyrix, …
◼ Pentium (1993): superscalar, 64-bit datapath
◼ Later versions added MMX (Multi-Media eXtension)
instructions
◼ The infamous FDIV bug
◼ Pentium Pro (1995), Pentium II (1997)
◼ New microarchitecture (see Colwell, The Pentium Chronicles)
◼ Pentium III (1999)
◼ Added SSE (Streaming SIMD Extensions) and associated
registers
◼ Pentium 4 (2001)
◼ New microarchitecture
◼ Added SSE2 instructions

Chapter 2 — Instructions: Language of the Computer — 71

The Intel x86 ISA
◼ And further…
◼ AMD64 (2003): extended architecture to 64 bits
◼ EM64T – Extended Memory 64 Technology (2004)
◼ AMD64 adopted by Intel (with refinements)
◼ Added SSE3 instructions
◼ Intel Core (2006)
◼ Added SSE4 instructions, virtual machine support
◼ AMD64 (announced 2007): SSE5 instructions
◼ Intel declined to follow, instead…
◼ Advanced Vector Extension (announced 2008)
◼ Longer SSE registers, more instructions
◼ If Intel didn’t extend with compatibility, its
competitors would!
◼ Technical elegance ≠ market success

Chapter 2 — Instructions: Language of the Computer — 72

 §2.22 Concluding Remarks
Concluding Remarks
◼ Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good compromises
◼ Layers of software/hardware
◼ Compiler, assembler, hardware
◼ MIPS: typical of RISC ISAs
◼ c.f. x86

Chapter 2 — Instructions: Language of the Computer — 73