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LM339-MIL
SNOSD54 – JUNE 2017
LM339-MIL Low-Power Low-Offset Voltage Quad Comparator

1 Features 3 Description
•
1 Wide Supply Voltage Range The LM339-MIL device consists of four independent
precision voltage comparators with an offset voltage
• 2 to 36 VDC or ±1 to ±18 VDC specification as low as 2 mV maximum for all four
• Very-Low Supply Current Drain (0.8 mA) — comparators. These comparators were designed
Independent of Supply Voltage specifically to operate from a single power supply
• Low Input Biasing Current: 25 nA over a wide range of voltages. Operation from split
power supplies is also possible and the low-power
• Low Input Offset Current: ±5 nA
supply current drain is independent of the magnitude
• Offset Voltage: ±3 mV of the power supply voltage. These comparators also
• Input Common-Mode Voltage Range Includes have a unique characteristic in that the input
GND common-mode voltage range includes ground, even
though they are operated from a single power supply
• Differential Input Voltage Range Equal to the
voltage.
Power Supply Voltage
• Low Output Saturation Voltage: 250 mV at 4 mA The LM339-MIL device was designed to directly
interface with TTL and CMOS. When operated from
• Output Voltage Compatible With TTL, DTL, ECL, both plus and minus power supplies, the device
MOS, and CMOS Logic Systems directly interfaces with MOS logic where the low-
• Advantages: power drain of the LM339-MIL is a distinct advantage
– High-Precision Comparators over standard comparators.
– Reduced VOS Drift Overtemperature Device Information(1)
– Eliminates Need for Dual Supplies PART NUMBER PACKAGE BODY SIZE (NOM)
– Allows Sensing Near GND CDIP (14) 19.56 mm × 6.67 mm
– Compatible With All Forms of Logic LM339-MIL SOIC (14) 8.65 mm × 3.91 mm
– Power Drain Suitable for Battery Operation PDIP (14) 19.177 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
• Limit Comparators
• Simple Analog-to-Digital Converters (ADCs)
• Pulse, Squarewave, and Time Delay Generators
• Wide Range VCO; MOS Clock Timers
• Multivibrators and High-Voltage Digital Logic
Gates
Noninverting Comparator With Hysteresis One-Shot Multivibrator With Input Lockout
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM339-MIL
SNOSD54 – JUNE 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 10
2 Applications ........................................................... 1 8.1 Application Information............................................ 10
3 Description ............................................................. 1 8.2 Typical Application .................................................. 10
4 Revision History..................................................... 2 8.3 System Examples ................................................... 11
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 17
6 Specifications......................................................... 4 10 Layout................................................................... 17
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 17
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 17
6.3 Recommended Operating Conditions....................... 5 11 Device and Documentation Support ................. 18
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 18
6.5 Electrical Characteristics........................................... 6 11.2 Receiving Notification of Documentation Updates 18
6.6 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 18
7 Detailed Description .............................................. 8 11.4 Trademarks ........................................................... 18
7.1 Overview ................................................................... 8 11.5 Electrostatic Discharge Caution ............................ 18
7.2 Functional Block Diagram ......................................... 8 11.6 Glossary ................................................................ 18
7.3 Feature Description................................................... 8 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes.......................................... 9 Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES

June 2017 * Initial release.
2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LM339-MIL

LM339-MIL
www.ti.com SNOSD54 – JUNE 2017
5 Pin Configuration and Functions
J, D, and NFF Packages

14-Pin CDIP, SOIC, and PDIP
Top View
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
1 OUTPUT2 O Output, Channel 2
3 V+ P Positive Supply
4 INPUT1- I Inverting Input, Channel 1
5 INPUT1+ I Noninverting Input, Channel 1
12 GND P Ground
Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 3

LM339-MIL
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
MIN MAX UNIT
Supply voltage, V+ 36
Differential input voltage (3) 36 VDC
Input voltage –0.3 36
Input current (VIN ≤ 0.3 VDC) (4) 50 mA
PDIP 1050
Power dissipation (5) Cavity DIP 1190 mW
SOIC package 760
Output short-circuit to GND (6) Continuous
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Refer to RETS139X for military specifications.
(3) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDC below
the magnitude of the negative power supply, if used) (at 25°C).
(4) This input current will only exist when the voltage at any of the input leads is driven negative. It is because of the collector-base junction
of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go
to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive
and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at
25°C).
(5) For operating at high temperatures, the device must be derated based on a 125°C maximum junction temperature and a thermal
resistance of 95°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The low bias
dissipation and the ON-OFF characteristic of the outputs keeps the chip dissipation very small (PD ≤ 100 mW), provided the output
transistors are allowed to saturate.
(6) Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 20 mA independent of the magnitude of V+.
6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±600 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

LM339-MIL
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, single 2 36
V
Supply voltage, dual ±1 ±18
Operating temperature 0 70 °C
6.4 Thermal Information

LM339-MIL
THERMAL METRIC (1) J (CDIP) D (SOIC) NFF (PDIP) UNIT
14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 97.8 94.3 82.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.6 52.4 79 °C/W
RθJB Junction-to-board thermal resistance 87.5 48.8 62.1 °C/W
ψJT Junction-to-top characterization parameter 43.9 14.2 50.9 °C/W
ψJB Junction-to-board characterization parameter 80.3 48.5 62 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 30.1 — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

LM339-MIL
6.5 Electrical Characteristics

(V+ = 5 VDC, TA = 25°C, unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
At output switch point, VO ≃ 1.4 VDC, RS = 0 Ω with V+
from 5 VDC to 30 VDC; and over the full input common- 2 5
mode range (0 VDC to V+ −1.5 VDC), at 25°C.
Input offset voltage At output switch point, VO ≃ 1.4 VDC, RS = 0 Ω with V+ mVDC
from 5 VDC to 30 VDC; and over the full input common-
9
mode range (0 VDC to V+ −1.5 VDC), at 25°C, 0°C ≤
TA ≤ 70°C
IIN(+) or IIN(−) with output in linear range, VCM = 0 V 25 250
Input bias current (1) IIN(+) or IIN(−) with output in linear range, VCM = 0 V, nADC
400
0°C ≤ TA ≤ 70°C
IIN(+)− IIN(−), VCM = 0 V 5 50
Input offset current nADC
IIN(+)− IIN(−), VCM = 0 V, 0°C ≤ TA ≤ 70°C 150
Input common-mode voltage V+ = 30 VDC 0 V+ − 1.5
VDC
range (2) V+ = 30 VDC, 0°C ≤ TA ≤ 70°C V+ – 2
RL = ∞ on all comparators 0.8 2 mADC
Supply current
RL = ∞, V+ = 36 V 1 2.5 mADC
Voltage gain RL ≥ 15 kΩ, V+ = 15 VDC, VO = 1 VDC to 11 VDC 50 200 V/mV
VIN = TTL logic swing, VREF = 1.4 VDC, VRL = 5 VDC,
Large signal response time 300 ns
RL = 5.1 kΩ
Response time (3) VRL = 5 VDC, RL = 5.1 kΩ 1.3 μs
Output sink current VIN(−)= 1 VDC, VIN(+) = 0, VO ≤ 1.5 VDC 6 16 mADC
VIN(−) = 1 VDC, VIN(+) = 0, ISINK ≤ 4 mA 250 400
Saturation voltage VIN(−) = 1 VDC, VIN(+) = 0, ISINK ≤ 4 mA, mVDC
700
0°C ≤ TA ≤ 70°C
VIN(+) = 1 VDC,VIN(−) = 0, VO = 5 VDC 0.1 nADC
Output leakage current VIN(+) = 1 VDC, VIN(−) = 0, VO = 30 VDC,
1 µADC
0°C ≤ TA ≤ 70°C
Keep all VINs ≥ 0 VDC (or V–, if used),
Differential input voltage (4) 36 VDC
0°C ≤ TA ≤ 70°C
(1) The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the
state of the output so no loading change exists on the reference or input lines.
(2) The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end
of the common-mode voltage range is V+ −1.5 V at 25°C, but either or both inputs can go to 30 VDC without damage, independent of the
magnitude of V+.
(3) The response time specified is a 100-mV input step with 5-mV overdrive. For larger overdrive signals 300 ns can be obtained, see
typical performance characteristics section.
(4) Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode
range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow
the magnitude of the negative power supply, if used) (at 25°C).

LM339-MIL
6.6 Typical Characteristics
Figure 1. Supply Current Figure 2. Input Current
Figure 3. Output Saturation Voltage Figure 4. Response Time for Various Input Overdrives—
Negative Transition
Figure 5. Response Time for Various Input Overdrives—

Positive Transition

LM339-MIL
7 Detailed Description
7.1 Overview
The LM339-MIL device is a monolithic quad of independently functioning comparators designed to meet the
requirements for a medium-speed, TTL-compatible comparator for industrial applications. Because no
antisaturation clamps are used on the output, such as a Baker clamp or other active circuitry, the output leakage
current in the OFF state is typically 0.1 nA. This OFF-state current level makes the device ideal for system
applications where switching a node to ground while leaving it totally unaffected in the OFF state is desired.
Other features include single supply, low-voltage operation with an input common mode range from ground up to
approximately one volt below VCC . The output is an uncommitted collector so it may be used with a pullup
resistor and a separate output supply to give switching levels from any voltage up to 36 V down to a V CE SAT
above ground (approximately 100 mV), sinking currents up to 16 mA. The open-collector output configuration
allows the device to be used in wired-OR configurations, such as a window comparators.
The device can also be used as a single pole switch to ground, leaving the switched node unaffected while in the
OFF state. Power dissipation with all four comparators in the OFF state is typically 4 mW from a single 5-V
supply (1 mW/comparator).
7.2 Functional Block Diagram
7.3 Feature Description

The LM339-MIL device is a high-gain, wide bandwidth device which, like most comparators, can easily oscillate if
the output lead is inadvertently allowed to capacitively couple to the inputs through stray capacitance. This shows
up only during the output voltage transition intervals as the comparator changes states. Reducing the input
resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1 to 10 mV) of
positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not
possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the
small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise
and fall times, hysteresis is not required.
The differential input voltage may be larger than V+ without damaging the device. Protection should be provided
to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode can be
used as shown in the Application and Implementation section.
The output of the LM339-MIL device is the uncommitted collector of a grounded-emitter NPN output transistor.
Many collectors can be tied together to provide an output ORing function. An output pullup resistor can be
connected to any available power supply voltage within the permitted supply voltage range and there is no
restriction on this voltage because of the magnitude of the voltage which is applied to the V+ pin. The output can
also be used as a simple SPST switch to ground (when a pullup resistor is not used). The amount of current

LM339-MIL
Feature Description (continued)

which the output device can sink is limited by the drive available (which is independent of V+) and the β of this
device. When the maximum current limit is reached (approximately 16 mA), the output transistor will come out of
saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the
approximately 60-Ω RSAT of the output transistor. The low offset voltage of the output transistor (4 mV) allows the
output to clamp essentially to ground level for small load currents.
7.4 Device Functional Modes

A basic comparator circuit is used for converting analog signals to a digital output. The output is HIGH when the
voltage on the noninverting (+IN) input is greater than the inverting (-IN) input. The output is LOW when the
voltage on the noninverting (+IN) input is less than the inverting (-IN) input. The inverting input (-IN) is also
commonly referred to as the reference, or VREF, input.
All pins of any unused comparators should be tied to the negative supply.
The bias network of the LM339-MIL device establishes a drain current which is independent of the magnitude of
the power supply voltage over the range of from 2 VDC to 30 VDC.

LM339-MIL
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The LM339-MIL device is specified for operation from 2 V to 36 V (±1 V to ±18 V) over the temperature range of
0°C to 70°C. While it may seem like a comparator has a well-defined and somewhat limited functionality as a 1-
bit ADC, a comparator is a versatile component which can be used for many functions.
8.2 Typical Application

8.2.1 Basic Comparator
Figure 6. Basic Comparator Schematic
8.2.1.1 Design Requirements

The basic usage of a comparator is to indicate when a specific analog signal has exceeded some predefined
threshold. In this application, the negative input is tied to a reference voltage, and the positive input is connected
to the input signal. The output is pulled up with a resistor to the logic supply voltage, V+.
For an example application, the supply voltage is 5 V. The input signal varies between 1 V and 3 V. Specifically
as an example, to know when the input exceeds 2.5 V, set the VREF voltage to 2.5 V.
8.2.1.2 Application Curve
VO
Voltage (V)
VIN
0
0 125 250 375 500 625 750 875 1000
Time (µs)
C002
Figure 7. Basic Comparator Response

LM339-MIL
8.3 System Examples
Figure 8. Driving CMOS Figure 9. Driving TTL

(V+ = 5 VDC) (V+ = 5 VDC)
Figure 10. AND Gate Figure 11. OR Gate

(V+ = 5 VDC) (V+ = 5 VDC)
Figure 13. Bi-Stable Multivibrator

(V+= 15 VDC)
Figure 12. One-Shot Multivibrator

(V+= 15 VDC)

LM339-MIL
Figure 14. One-Shot Multivibrator With Input

Lockout
(V+= 15 VDC)
Figure 15. Pulse Generator

(V+= 15 VDC)
Figure 16. Large Fan-In AND Gate

(V+= 15 VDC)
Figure 17. ORing the Outputs

(V+= 15 VDC)

LM339-MIL
(V+= 15 VDC)
Figure 19. Noninverting Comparator with

Hysteresis
(V+= 15 VDC)
Figure 18. Time Delay Generator
Figure 20. Inverting Comparator With Hysteresis Figure 21. Squarewave Oscillator
(V+= 15 VDC) (V+= 15 VDC)

LM339-MIL
Figure 22. Basic Comparator

(V+= 15 VDC)
Figure 23. Limit Comparator
(V+= 15 VDC)
Figure 24. Comparing Input Voltages of Opposite

* Or open-collector logic gate without pullup resistor
Polarity
(V+= 15 VDC) Figure 25. Output Strobing
(V+= 15 VDC)

LM339-MIL
(V+= 15 VDC)
250 mVDC ≤ VC ≤ +50 VDC

700 Hz ≤ fO ≤ 100 kHz
Figure 27. Two-Decade High-Frequency VCO

V+ = +30 VDC
Figure 26. Crystal Controlled Oscillator
Figure 28. Transducer Amplifier Figure 29. Zero Crossing Detector (Single Power
(V+= 15 VDC) Supply)
(V+= 15 VDC)

LM339-MIL
8.3.1 Split-Supply Applications
Figure 30. MOS Clock Driver

(V+ = +15 VDC and V– = −15 VDC)
Figure 31. Zero Crossing Detector

(V+ = +15 VDC and V– = −15 VDC)
Figure 32. Comparator With a Negative Reference
(V+ = +15 VDC and V– = −15 VDC)

LM339-MIL
9 Power Supply Recommendations

Even in low-frequency applications, the device can have internal transients which are extremely quick. For this
reason, bypassing the power supply with a 1-µF capacitor to ground will provide improved performance; the
supply bypass capacitor should be placed as close as possible to the supply pin and have a solid connection to
ground. The bypass capacitors should have a low ESR.
10 Layout
10.1 Layout Guidelines

Try to minimize parasitic impedances on the inputs to avoid oscillation. Any positive feedback used as hysteresis
should place the feedback components as close as possible to the input pins. Ensure that the output pins do not
couple to the inputs which can occur through capacitive coupling if the traces are too close and lead to
oscillations on the output.
The optimum bypass capacitor placement is closest to the V+ and ground pins. Minimize the loop area formed by
the bypass capacitor connection between V+ and ground. The ground pin should be connected to the PCB
ground plane at the pin of the device. The feedback components should be placed as close to the device as
possible minimizing strays.
10.2 Layout Example
Figure 33. Layout Example

LM339-MIL
11 Device and Documentation Support
11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, AN-74 LM139/LM239/LM339 A Quad of Independently Functioning Comparators application
report
11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 30-Sep-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LM339J ACTIVE CDIP J 14 25 Non-RoHS Call TI Level-1-NA-UNLIM 0 to 70 LM339J

& Green
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM339J J CDIP 14 25 502 14 11938 4.32
Pack Materials-Page 1
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
7 8
B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]
C SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE

[0.38]
0 -15 14X .008-.014

TYP [0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A
1 14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
7 8
SYMM
LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING
METAL
SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
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Product Order Technical Tools & Support &

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LM339-MIL Low-Power Low-Offset Voltage Quad Comparator

DATE REVISION NOTES

2 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

Product Folder Links: LM339-MIL

5 Pin Configuration and Functions

J, D, and NFF Packages

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6.2 ESD Ratings

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6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.5 Electrical Characteristics

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6.6 Typical Characteristics

Figure 1. Supply Current Figure 2. Input Current

Figure 5. Response Time for Various Input Overdrives—

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7.2 Functional Block Diagram

7.3 Feature Description

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Feature Description (continued)

7.4 Device Functional Modes

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8 Application and Implementation

8.1 Application Information

8.2 Typical Application

Figure 6. Basic Comparator Schematic

8.2.1.1 Design Requirements

8.2.1.2 Application Curve

Figure 7. Basic Comparator Response

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8.3 System Examples

Figure 8. Driving CMOS Figure 9. Driving TTL

Figure 10. AND Gate Figure 11. OR Gate

Figure 13. Bi-Stable Multivibrator

Figure 12. One-Shot Multivibrator

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Figure 14. One-Shot Multivibrator With Input

Figure 15. Pulse Generator

Figure 16. Large Fan-In AND Gate

Figure 17. ORing the Outputs

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Figure 19. Noninverting Comparator with

Figure 18. Time Delay Generator

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Figure 22. Basic Comparator

Figure 24. Comparing Input Voltages of Opposite

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250 mVDC ≤ VC ≤ +50 VDC

Figure 27. Two-Decade High-Frequency VCO