Unit 4

Operational Amplifier

33.1 Introduction
➢ An operational amplifier, or op-amp, is a very high gain differential amplifier with
high input impedance and low output impedance.
➢ Typical uses of the operational amplifier are to provide voltage amplitude changes
(amplitude and polarity), oscillators, filter circuits, and many types of
instrumentation circuits.
➢ An op-amp contains a number of differential amplifier stages to achieve a very high
voltage gain.
➢ An ideal Operational Amplifier is basically a three-terminal device which
consists of two high impedance inputs, one called the Inverting Input, marked
with a negative or “minus” sign, ( - ) and the other one called the Non-inverting
Input, marked with a positive or “plus” sign ( + ) and one output as shown in fig 1.

Inverting input

Vout
Non Inverting
input

Fig 1 : Symbol of Opamp

3.2 Block Diagram or Stages of opamp

The basic block diagram constitutes mainly four stages as shown in fig 2

Non Inverting
input

Input Stage Intermediate Level Shifting Output

Stage Stage
Stage output
Inverting
input
Dual Input Dual Input Common complementary
Balanced Output unbalanced Collector symmetry push
Differential Output Differential or pull Amplifier
Amplifier Amplifier Emitter
follower
Fig 2 : Block diagram of opamp
1. Input Stage
➢ The input stage consisting of "Dual Input Balanced Output Differential Amplifier"
This stage determines the Input impedence of Operational Amplifier, having two
inputs Inverting and Non Inverting.
➢ In this stage Differential amplifiers with a constant current source is used inorder
to Increase the CMRR (common mode rejection ratio).

2. The Intermediate Stage

➢ This stage also posses two inputs but having only One Output.
➢ It is usually another Differential amplifier, which is driven by the preceding Output.
This stage is commonly used to Increase the gain of amplifier.
➢ In the quiescent condition some dc error voltage may appears on the output of this
stage.

3. The Level Shifting stage

➢ This stage is usually an Emitter Follower circuit in order to shift the error dc Level
of preceding stage.
➢ This stage eliminate the chance of signal distortions.

4. The Output Stage

➢ It is final Stage of an Operational amplifier, it is usually a complementary
symmetry push pull Amplifier.
➢ This Stage Increases the Output voltage swing and the current delivering
capabilities.

3.3 Pin Configuration

➢ Linear integrated opamp are fabricated on a very small silicon chip and are
packed in a suitable case.

Offset Null 1 8 No
Connection

Inverting 2 7
input (-) +Vcc

Non
inverting 3 6
Input(+) Output

-VEE 4 5
Offset Null

Fig 3 : Pin diagram of Opamp

The Dual in line packing(DIP) of opamp has 8 or 14 pins and is most widely used. It
may contain from one to four opamps. Fig 3 shows such a package with 8 pins

3.4 Equivalent Circuit for Ideal Operational Amplifiers

➢ The equivalent circuit of opamp is shown in fig 4.
➢ The output section consists of voltage controlled voltagr source in series with the
output impedance Zout.In fig 4 input resistance Zin is the thevinin equivalent
resistance seen at the input terminals, while the output resistance is seen at the
output. The differential input voltage is given by

Vd=V2-V1

+VCC
I1
V1
Inverting input Zout
Output
Zin
Non inverting
Input
A(V2 –V1)
V2
I2

-VEE

Fig 4 : Equivalent Circuit of Opamp

➢ The opamp senses the difference between the two inputs, multiplies it by gain A and causes the
resulting voltage to appear at the output. Thus, the output voltage Vo is given by

Vo= AOLVd=AOL(V2-V1)

3.5 Op-Amp Parameters

1. Input Offset Voltage (Vio)
➢ If no external input signal is applied to the op-amp at the inverting and non-
inverting input terminals the output must be zero. That is, if Vi = 0, V0 = 0.
➢ But as a result of the given biasing supply voltages, +Vcc and −Vcc, a finite bias
current is drawn by the op-amp, and as a result of unsymmetry on the differential
amplifier configuration, the output will not be zero. This is known as offset.
➢ Since V0 must be zero when Vi = 0, the input-signal must be applied such that
the output offset is cancelled and V0 is made zero. This is known as input offset
voltage.
➢ It is the voltage that must be applied between the two input terminals of an op-
amp to nullify output. This is shown in Fig.5.
 ➢ The value for ideal op-amp. is Vio = 0 V. Practical value ±2mV (typical).

V1 RR1 1

Vout=0
Vio
Vio=V2-V1
VVV1

V2 R2
V2 Fig 5

1. Input Offset Current (Iios)

➢ Though for an ideal op-amp, the input impedance is ∞, it is not so practically.
So the IC draws current from the source of the voltage, however small it may
be.
➢ The algebraic difference between the currents into the inverting and non-
inverting terminals is referred to as input offset current Iio.

Iio = |IB2 − IB1|

+Vcc

Ib1

Vout
Ib2

-VEE

Fig 6

2. Output Bias Current (IB)

This is the average of the currents that flow into the inverting and non-inverting
input terminals of the op-amp.
 𝐈𝐁𝟏 + 𝐈𝐁𝟐
𝑰𝑩 =
𝟐
3. Input Resistance (Ri)
➢ This is the equivalent resistance of the IC measured at either the inverting or
non-inverting input terminal, with the other terminal connected to the ground.
➢ Ideal value = ∞Ω, Practical value = 2 MΩ.

4. Common Mode Rejection Ratio [CMRR]

➢ CMRR is defined as the ratio of the differential voltage gain, Ad, to the
common mode voltage gain, Acm. (cm = common mode)
𝑨
𝑪𝑴𝑹𝑹 = 𝒅
𝑨𝒄𝒎

➢ The differential voltage gain is defined as

𝑽𝒐
𝑨𝒅 =
𝑽𝒊𝒅

Where Vid is the differential input (V1-V2)

Vout

Vc

Fig 7 : Symbol of Opamp

The common mode voltage gain is defined as
𝑽𝒐
𝑨𝒄𝒎 =
𝑽𝒄𝒎
Where Vcm is the common mode input
𝑉1 + 𝑉2
𝑉𝑐𝑚 =
2
➢ Ideal value = ∞, Practical value = 90 db.
 5. Power Supply Rejection Ratio (PSRR)
➢ PSRR is defined as the ratio of change in the input offset voltage Vio with a
change in one of the bias power supplying Vcc, when the other power supply
is held constant.
△𝑽
𝑷𝑺𝑹𝑹 = 𝒊𝒐 µV/V
△𝑽𝒄𝒄 ∆VEE constant

OR

△𝑽𝒊𝒐
𝑷𝑺𝑹𝑹 = µV/V
△𝑽𝑬𝑬 ∆VCC constant

➢ Ideal value = 0, Practical Value = 150 µV/V.

6. Slew Rate (SR)

➢ This is defined as the maximum rate of change of output voltage per unit time.

△𝑽𝟎 V/us
𝑺𝑹 = max
△𝒕

➢ Ideal Value = 0, Practical Value = .01V/µsec.

3.6 Ideal Op-Amp Characteristics

An ideal op-amp is usually considered to have the following properties:

➢ Infinite open-loop gain.

➢ Infinite input impedance Zin, and so zero input current.
➢ Zero input offset voltage.
➢ Infinite voltage range available at the output.
➢ Infinite bandwidth with zero phase shift and infinite slew rate.
➢ Zero output impedance Zout..
➢ Zero noise.
➢ Infinite Common-mode rejection ratio (CMRR).
➢ Infinite Power supply rejection ratio.

3.7 Op Amp Configurations

1. Inverting Configuration
2. Non-Inverting Configuration

1. Inverting Amplifier: Closed Loop Inverting Amplifier

 ➢ An inverting amplifier or inverting voltage controlled voltage source (VCVS) is
a closed loop amplifier in which the input is applied at the inverting terminal as
shown in fig 8.
➢ The output of inverting amplifier is out of phase by 180 o with respect to input.

RF

IF
R1
V2
Vin
I1 IB
Vout
V1

Fig 8 : Inverting amplifier

For an Op-Amp

𝑉𝑜𝑢𝑡
𝐴=
𝑉𝑖𝑑

Vid=V1-V2

𝑉𝑜𝑢𝑡
𝐴=
𝑉1 −𝑉2

𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡
V1 − V2 = = =0
𝐴 ∞

So, V1-V2=0

V1=V2

➢ From the above equation it is clear that the potential difference between two
terminals is zero. We can say that a Virtual Short- circuit exists between two
terminals.
➢ A Virtual short circuit means that whatever is the voltage at non-inverting terminal,
it will automatically appear at the inverting terminal because of the infinite voltage
gain A.

As V1=0 so V2=0

Calculation of Closed Loop Voltage Gain:

Appling KCL at node N in fig 7-

I1=IB+IF

IB ~ 0, because ideal op-amp has an infinite input impedance.

So I1= IF
𝑉𝑖𝑛 − 𝑉2 𝑉2 − 𝑉𝑜𝑢𝑡
=
𝑅1 𝑅𝐹
V2= 0 ,by Virtual ground so

𝑉𝑖𝑛 𝑉𝑜𝑢𝑡
=−
𝑅1 𝑅𝐹
𝑉𝑜𝑢𝑡 𝑅𝐹
= −
𝑉𝑖𝑛 𝑅1

2. Non-Inverting Amplifier: Closed Loop Non-Inverting Amplifier

➢ In a closed loop non-inverting amplifier, the external input signal is applied at

the non-inverting terminal and the inverting terminal is grounded as shown in
fig 9.
➢ The output of non-inverting amplifier is in phase with the input.
RF

IF

R1 V2

Vout
I1 IB
V1
Vin
Fig 9 : Non Inverting amplifier
Calculation of Closed Loop Voltage Gain:

By virtual short concept-

V1=V2
V1=Vin
so V2=Vin ------------------------------(1)

Appling KCL at node N-

I1= IB+IF
IB ~ o because ideal op-amp has an infinite input impedence.

I1=IF

From figure V2= IFRF + Vout

Vin = IFRF + Vout ------------------(2)

𝟎−𝐕𝟐
I F = I 1=
𝐑𝟏

and V2= V1 = Vin

𝐕𝐢𝐧
So, IF = -
𝐑𝟏

𝑉𝑖𝑛
Vin = - 𝑅𝐹 +Vout
𝑅1

𝑅𝐹
Vout= 1+
𝑅1
𝑅𝐹
𝐴𝐹 = 1 +
𝑅1

3.8 Applications of Opamp

1. Unity Gain Amplifier/Voltage Follower

The gain for a closed loop non-inverting amplifier is given by-

 𝑅𝐹
𝐴𝐹 = 1 +
𝑅1

IF
V2

IB
Vout
V1
Vin

Fig 10 : Voltage Follower

Now, Let RF = 0 (short)

R1= ∞ (open) in fig 10

AF=1

So, Vout = Vin

➢ This circuit is called as voltage follower because the output voltage is equal to
and in phase with the input.
➢ Hence Voltage Follower is a special case of the non-inverting amplifier.
➢ Voltage follower is also used as a buffer amplifier.

2. Summer or Adder Circuit-

➢ The input impedance of an op-amp is extremely large, so more than one input
signal can be applied to the inverting amplifier.
➢ Such circuit gives the addition of the applied signals at the output, Hence it is
called as summer or adder circuit.

A basic summing amplifier circuit with three input signals is shown on Figure 11.
 RF

R1
Vin 1 IF
I1
R2 V2
Vin 2
I2 IB
R3
Vin 3 Vout
I3
V1

Fig 11 :Summing amplifier

Appling KCL at Node N,

I1+I2+I3=IF

𝑽𝒊𝒏𝟏 −𝑽𝟏 𝑽𝒊𝒏𝟐 −𝑽𝟏 𝑽𝒊𝒏𝟑 −𝑽𝟏 𝑽𝟏 −𝑽𝒐

+ + =
𝑹𝟏 𝑹𝟐 𝑹𝟑 𝑹𝑭

By virtual ground concept-

V1=V2=0

𝑽𝒊𝒏𝟏 𝑽𝒊𝒏𝟐 𝑽𝒊𝒏𝟑 𝑽

+ + = − 𝑹𝒐
𝑹𝟏 𝑹𝟐 𝑹𝟑 𝑭

𝑹𝑭 𝑹𝑭 𝑹𝑭
V0 = - ( 𝑽𝒊𝒏𝟏 + 𝑽𝒊𝒏𝟐 + 𝑽𝒊𝒏𝟑 )
𝑹𝟏 𝑹𝟐 𝑹𝟑

3. Integrator
➢ The circuit in which the output voltage waveform is the integration of the input
voltage waveform is called as an integrator or integrating amplifier.
 CF

IF
R1 V2
Vin
I1
Vout
V1

Fig 12(a) : Integrator using opamp

Expression for the output voltage-

Appling KCL at node N in fig 12(a),

I1=IB+IF

Due to high input impedance R1 of the op-amp, IB will be negligible.

So, I1=IF
The relation between voltage and current across a capacitor is given by-
𝒅𝑽𝑪
IF=𝑪𝑭
𝒅𝒕

𝒅𝑽𝑪
So, I1=𝑪𝑭
𝒅𝒕

𝑽𝒊𝒏 −𝑽𝟐
I 1= and VC=V2-V0
𝑹𝟏
𝑽𝒊𝒏 −𝑽𝟐 𝒅(𝑽𝟐 −𝑽𝟎 )
So, = CF
𝑹𝟏 𝒅𝒕
By virtual short method-
V1=V2=0
So, we get
𝑽𝒊𝒏 𝒅(−𝑽𝟎 )
= CF
𝑹𝟏 𝒅𝒕
The output voltage can be obtained by integrating the above equation as-

𝟏 𝒕
V0= - ∫ 𝑽 𝒅𝒕
𝑹𝟏 𝑪𝑭 𝟎 𝒊𝒏
+𝑪
 Where C is the integration constant and it is proportional to the output voltage V o
at t=0.

Input and output waveform of integrator

Let us consider a square wave shown in fig 12(b) at the input of ideal integrator and obtain
the corresponding output voltage.

Vin Input Waveform

+A

0
time(t)

-A
T
T/2

output Waveform

time(t)

-At/2
Vo
Fig 12(b): Input and output waveform
ontegrator

4. Differentiator –
➢ A differentiator circuit produces differentiated version of the input voltage applied
to it.
➢ This process is exactly opposite to integration; therefore the components
connected in the integrator have interchanged their positions to produce a
differentiator circuit.
 RF

IF
C1
V2
Vin
I1 IB
Vout
V1

Fig 13(a) : Differentiator using opamp

Expression for the output voltage-

Appling KCL at node N in fig 13(a)
IC=IB+IF
Due to high input impedance R1 of the op-amp, IB will be negligible.
So, IC=IF

𝒅𝑽𝑪
IC=𝑪𝟏
𝒅𝒕
The voltage across C1 is given by

VC=Vin-V2

𝒅(𝑽𝒊𝒏 −𝑽𝟐 )
IC= C1
𝒅𝒕
𝑉2 −𝑉0
and IF=
𝑅𝐹

𝒅(𝑽𝒊𝒏 −𝑽𝟐 ) 𝑽𝟐 −𝑽𝟎

C1 =
𝒅𝒕 𝑹𝑭

By virtual ground concept-

V1=V2=0
 𝑑(𝑉𝑖𝑛 ) 𝐕𝐨
So, C1 =-
𝑑𝑡 𝐑𝐅
Therefore,

𝒅𝑽𝒊𝒏
Vo = -RFC1
𝒅𝒕

Input and output waveform of differentiator

Let us consider a square wave shown in fig 13(b) at the input of ideal differentiator and
obtain the corresponding output voltage.

Vin Input Waveform

+A

0
time(t)
-A
T
T/2
output Waveform

time(t)

Vo
Fig 13(b): Input and output waveform of differentiator

5. Subtractor or Difference Amplifier:

➢ In the difference amplifier the output voltage is proportional to the difference
between the two input voltages.
 RF

IF
R1 V2
V1
I1 IB
Vout
R2
V2 A V1
R3

Fig 14 : Subtractor

➢ Considering Vin1voltage source and Vin2 set to zero.

𝑹𝑭
Vout1 = − 𝑽𝒊𝒏𝟏
𝑹𝟏
By Virtual short method-
V1=V2
Appling voltage divider rule to the input Vin2 loop-
𝑅𝐹
V1= 𝑉 --------------------1
𝑅2 +𝑅𝐹 𝑖𝑛2
𝑽𝟐 𝑽𝟏
I= = -----------------------2
𝑹𝟏 𝑹𝟏

𝑽𝒐𝒖𝒕𝟐 −𝑽𝟐 𝑽𝒐𝒖𝒕𝟐 −𝑽𝟏

I= = -----------3
𝑹𝑭 𝑹𝑭
Equating equation 2 and 3-

𝑅1 +𝑅𝐹
we get, Vout2= 𝑉1
𝐑𝟏
Putting the value of V1 from equation 1-

𝐑𝐅 𝑅𝐹
Vout2 = [1+ ][ 𝑉 ]
𝐑𝟏 𝑅2 +𝑅𝐹 𝑖𝑛2

Using super position principle, we get-

 𝑅𝐹 𝑅 𝑅𝐹
Vout = Vout1 + Vout2 = − 𝑉𝑖𝑛1 + [1+𝑅𝐹 ] [𝑅 𝑉𝑖𝑛2 ]
𝑅1 1 2 +𝑅𝐹
Now, if the resistances are selected such that R1 = R2 then

𝑹𝑭
Vout = (𝑽𝒊𝒏𝟐 − 𝑽𝒊𝒏𝟏 )
𝑹𝟏

This means that the output voltage is proportional to the difference between the two
input voltages. Thus it act as a subtractor or difference amplifier.

Example 3.1 Determine common mode gain of an op-amp, if CMRR = 105 and differential
gain is Ad= 105.
𝑨
Solution 3.1 𝐶𝑀𝑅𝑅 = 𝑨 𝒅
𝒄𝒎
𝐴𝑑 105
𝐴𝐶𝑀 = 𝐶𝑀𝑅𝑅 = =1
105
Example 3.2 The output voltage of a certain op amp circuit changes by 20V in 4 micro
sec. What is slew rate?
△𝑉0 20𝑉
Solution 3.2 𝑆𝑅 = = = 5V/µsec
△𝑡 𝟒µ𝒔𝒆𝒄

Example 3.3 Design a non-inverting amplifier circuit that is capable of providing a

voltage gain of 10. Assume ideal operational amplifier.
𝑅𝐹
Solution 3.3 𝐴𝐹 = 1 + 𝑅1
𝑅𝐹
AF = 10 so =9
𝑅1
RF=9k

IF

R1=1K V2

Vout
I1
V1
IB
Vin

Fig 15 : Non Inverting amplifier

Taking R1 = 1KΩ
R2 = 9KΩ
Example 3.4 A differential amplifier has a common mode gain of 35dB and CMRR of 72
dB. Find the output voltage Vo when the input voltages are 0.16mV and 0.18mV.
𝑨𝒅
Solution 3.4 CMRR =
𝑨𝒄𝒎

Acm = Common mode gain

= 35dB = 56.23

CMRR = 72dB = 3981

𝐴𝑑
3981 =
56.23
Ad= difference mode gain

= 2.238x105

1 1
Common mode signal (VC) = (𝑉1 + 𝑉2 ) = (0.16 + 0.18) = 0.17𝑚𝑉
2 2

Difference mode signal (Vd) = 0.18-0.16 = 0.02mV

V0 =𝐴𝐶 𝑉𝐶 + 𝐴𝑑 𝑉𝑑
= 56.23x0.17+2.238x105x0.02(mV)

V0 =14.035 Volt

Example 3.5 Find out the Vo in the circuit in given fig 16.

1M

IF

1k

Vo
10K

2V
10K

3V

Fig 16
Solution 3.5 The given circuit is the non-inverting adder hence, we have

V0 = AF x V1

𝑹𝑭 𝑽𝒂 +𝑽𝒃
V0 = [1+ ] 𝐗 ( )
𝑹𝟏 𝟐

V0 = 4X 2.5 = 10 Volt

Example 3.6 Find out the output voltage of the following circuit shown in figure17.

10k

1k
-1V

1k
.5V
1k

+1V Vout

Fig 17 :Summing amplifier

Solution 3.6 This is an inverting amplifier

𝑹𝑭 𝑹𝑭 𝑹𝑭
V0 = - ( 𝑽𝟏 + 𝑽𝟐 + 𝑽𝟑 )
𝑹𝟏 𝑹𝟐 𝑹𝟑

𝟏𝟎𝑲 𝟏𝟎𝑲 𝟏𝟎𝑲

=-[ 𝑿−𝟏+ 𝒙𝟎. 𝟓 + 𝑿𝟏]
𝟏𝑲 𝟏𝑲 𝟓𝑲

V0 = - (-10+5+2) = 3 Volts

Example 3.7 Find the output voltage of the following op-amp circuit shown in fig 18.
 RF= 10k

R1=5k

V1

Vout
R2= 5k
V2
R3= 2k

Fig 18

Solution 3.6 Using the Super position principle

1. Output due to V1 only

Let us assume V2=0 and only V1 being applied. This is the inverting amplifier-
𝑅𝐹
V01 = - XV1
𝑅1
10
=- X V1 = -2𝑉1
5
2. Output due to V2 only
Let us assume V1=0 and only V2 being applied. This is the non-inverting
amplifier-
𝑅
V02 = (1+𝑅𝐹) X 𝑉𝐴
1
10𝑘 2𝑘
= (1+ 5𝐾 ) X 5𝐾+2𝐾 X𝑉2
6
= 7 𝑉2
3. Complete outputV0-
6
V0 = V01+V02 = -2𝑉1 +7 𝑉2

Example 3.8 Determine the output voltage for the circuit of Fig 19 with a sinusoidal
input of 2.5mV.
 RF=200k

R1=2k
Vin

Vout

Fig 19

Solution 3.6 The circuit of Fig. uses a 741 op-amp to provide a constant or fixed gain,
Calculated as-

𝑅𝐹 200𝐾Ω
𝐴=− = − = −100
𝑅1 2𝐾Ω

The output voltage is then

𝑉0 = 𝐴𝑉𝑖 = −100(2.5mV) = −250mV = −0.25V

Example 3.9 Calculate the output voltage from the circuit of Fig 20. for an input
of 120 µV.

Rf=240k

R1=2.4k

Vout

120uV
Fig 20
 Solution 3.9 The gain of the op-amp circuit is calculated as-

𝑅𝐹 240𝐾Ω
𝐴=1+ = 1+ = 1 + 100 = 101
𝑅1 2.4𝐾Ω

The output voltage is then

𝑉0 = 𝐴𝑉𝑖 = 101(120µ𝑉) = 12.12mV

Example 3.10 Calculate the output voltage using the circuit of Fig. 21 for resistor
components of value Rf =470 kΩ, R1 =4.3 kΩ, R2= 33 k, Ω and R3= 33 k Ω for an input
of 80µV.
RF
RF
RF

R1
R2
R3

Vout
Vin

Fig 21

Solution 3.10 The amplifier gain is calculated to be

𝑅𝐹 𝑅𝐹 𝑅𝐹
𝐴 = 𝐴1 𝐴2 𝐴3 = (1 + ) (− ) (− )
𝑅1 𝑅2 𝑅3

=
470𝐾Ω 470𝐾Ω 470𝐾Ω
= (1 + ) (− ) (− )
4.3𝐾Ω 33𝐾Ω 33𝐾Ω

= (110.3)(−14.2)(−14.2) = 22.2 × 103

So that 𝑉0 = 𝐴𝑉𝑖 = 22.2 × 103 (80µ𝑉) = 1.78𝑉

Example 3.11 Calculate the output voltage for the circuit of Fig 22. The inputs are𝑉1 =
50𝑚𝑉 sin 1000𝑡 and 𝑉2 = 10𝑚𝑉 sin 3000𝑡.
 330k

33k
V1 +9V

10k
V2

Vout

-9V
Fig 22

Solution 3.11 The output voltage is

330𝐾Ω 330𝐾Ω
𝑉0 = − ( 𝑉1 + 𝑉 ) = −(10𝑉1 + 33𝑉2 )
33𝐾Ω 10𝐾Ω 2

= −[10(50mV sin(1000𝑡) + 33(10mV) sin(3000𝑡)]

= −[0.5 sin(1000𝑡) + 0.33 sin(3000𝑡)]

Example 3.12 Determine the output for the circuit of Fig23. with components 𝑅𝐹 =
1𝑀Ω, 𝑅1 = 100𝐾Ω, 𝑅2 = 50𝐾Ω, 𝑅3 = 500𝐾Ω.
RF
RF

R1
R2
V1 Vout
V2

Fig 20
Solution 3.13 The output voltage is calculated to be
 1𝑀Ω 1𝑀Ω 1𝑀Ω
𝑉0 = − ( 𝑉2 − × 𝑉)
50𝐾Ω 500𝑘Ω 100𝐾Ω 1

= −(20𝑉2 − 20𝑉1 ) = −20(𝑉2 − 𝑉1 )

Previous Year UPTU Questions

1. How op-amp act as a Differentiator? Derive its output voltage expression.

2. Define CMRR, Slew rate and concept of virtual ground in op-amp.
3. Explain the ideal characteristics of op-amp. Also derive the expression for voltage
gain for inverting amplifier.
4. Derive the expression for voltage gain for non-inverting amplifier.
5. How op-amp act as a Integrator? Derive its output voltage expression.
6. Sketch the three input inverting summing circuit and derive an expression for an
output voltage.
7. Explain Virtual ground in an op-amp. Write the characteristics of ideal op-amp.
8. Derive the output voltage expression for subtractor?
9. Define input bias current, input offset voltage for an op-amp.
10. Draw and explain various stages of op-amp? Also draw the equivalent circuit of
op-amp.
11. What do you mean by unity gain amplifier(Voltage follower)?