Esp32-H2 Datasheet en

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ESP32-H2
Datasheet
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Bluetooth® Low Energy and IEEE 802.15.4 SoC
(supporting Bluetooth 5 (LE), Bluetooth Mesh, Thread, Matter
and Zigbee)
Including:
ESP32-H2FH2 (2 MB In-Package Flash)
ESP32-H2FH4 (4 MB In-Package Flash)

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Pre-release v0.5
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Espressif Systems
Copyright © 2023
www.espressif.com
Product Overview
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ESP32-H2 is an ultra-low-power Internet of Things (IoT) solution offering multiple protocol support on a single
chip. It integrates a 2.4 GHz transceiver compliant with Bluetooth ® Low Energy and IEEE 802.15.4-based
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technologies, supporting Bluetooth 5 (LE), Bluetooth mesh, Thread, Matter, and Zigbee. It has:
• A Bluetooth LE subsystem that supports features • Reliable security features ensured by

of Bluetooth 5 and Bluetooth mesh
– Cryptographic hardware accelerators that
• An IEEE 802.15.4 subsystem that supports support AES-128/256, Hash, RSA, HMAC,
Thread and Zigbee ECC, digital signature and secure boot
• Radio protocols coexistence in 2.4 GHz band
– Random number generator
• State-of-the-art power and RF performance
– Permission control on accessing internal
• 32-bit RISC-V single-core processor with a memory, external memory, and peripherals
• 320 KB of SRAM, 128 KB of ROM, 4 KB LP

memory, and 2 MB or 4 MB in-package flash
inside
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four-stage pipeline that operates at up to 96 MHz
– External memory encryption and decryption
• Rich set of peripheral interfaces and GPIOs, ideal

for various scenarios and complex applications
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Espressif Systems 1 ESP32-H2 Datasheet (Pre-release v0.5)

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Block Diagram
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Espressif’s ESP32-H2 Bluetooth®Low Energy + IEEE 802.15.4 SoC
Core System Wireless MAC and RF

Baseband
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2.4 GHz Balun + Switch
RISC-V
32-bit
Bluetooth LE Bluetooth LE
Microprocessor 2.4 GHz Transmitter
Baseband Link Controller
Cache SRAM 2.4 GHz Receiver

LP 802.15.4 802.15.4
Memory Baseband MAC
JTAG ROM Clock Generator
Peripherals Power Management

⚙ ⚙ ⚙
SPI I2C HP GPIO LP IO Power Management Unit
PARLIO
TWAI®
GDMA
⚙
⚙
I2S
PCNT
SOC ETM
⚙
⚙
UART
RMT
eFuse
Controller
IN ⚙
⚙
RTC Watchdog
Timer
RTC Timer
System Timer
⚙
SHA
AES
⚙
⚙
Security
RSA
Digital ⚙
Signature
⚙
ECC
HMAC
⚙
⚙
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⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙
LEDC MCPWM ADC Timer Group TRNG ECDSA TEE
⚙ Temperature ⚙ Brown-out ⚙ Secure⚙ Flash ⚙

USB Serial / JTAG APM
Sensor Detector Boot Encryption
Modules having power in specific power modes:

Active
Active, Modem-sleep
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Active, Modem-sleep, Light-sleep ⚙ Optional in Light-sleep

All modes
Block Diagram of ESP32-H2

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Features
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Bluetooth – 3 × SPI
– 2 × UART
• Bluetooth Low Energy (Bluetooth 5.3 certified)
– 2 × I2C
• Bluetooth mesh
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– 1 × I2S
• Bluetooth Low Energy long range (Coded PHY,
125 Kbps and 500 Kbps) – Remote control peripheral, with 2 transmit
channels and 2 receive channels
• Bluetooth Low Energy high speed (2 Mbps)
• Bluetooth Low Energy advertising extensions – LED PWM controller, with up to 6 channels
and multiple advertising sets – Motor control PWM (MCPWM)
• Simultaneous Broadcaster, Observer, Peripheral – Pulse count controller (PCNT)

and Central
– 1 × TWAI® controller compatible with ISO
• Multiple connections 11898-1 (CAN Specification 2.0)
• LE power control
IEEE 802.15.4
• IEEE Standard 802.15.4-2015 compliant
• Supports 250 Kbps data rate in 2.4 GHz band

IN – Full-speed USB Serial/JTAG controller
– General DMA controller (GDMA), with 3

transmit channels and 3 receive channels
– SoC event task matrix (ETM)
– Parallel IO (PARLIO) controller

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and OQPSK PHY
• Analog interfaces:
• Supports Thread 1.3
– 1 × 12-bit SAR ADC, up to 5 channels
• Supports Zigbee 3.0
– 1 × temperature sensor
• Supports Matter
• Timers:
• Supports other application-layer protocols
(HomeKit, MQTT, etc) – 2 × 54-bit general-purpose timer
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– 1 × 52-bit system timer

CPU and Memory
– 3 × watchdog timers
• 32-bit RISC-V single-core processor, up to 96
MHz Security
• 128 KB ROM • Secure boot
• 320 KB SRAM • Flash encryption
• 4 KB LP Memory
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• 4096-bit OTP, up to 1792 bits for users

• 2 MB or 4 MB in-package flash • Cryptographic hardware acceleration:
– AES-128/256 (FIPS PUB 197, against DPA

Advanced Peripheral Interfaces
attack)
• 19 × programmable GPIOs
– ECB/CBC/CFB/OFB/CTR (FIPS PUB
• Digital interfaces: 800-38A)

– SHA Accelerator (FIPS PUB 180-4) – Digital signature
– RSA Accelerator
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– HMAC
– ECC Accelerator
• Access permission management (APM)
– ECDSA (Elliptic Curve Digital Signature
Algorithm) • Random Number Generator (RNG)
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Applications (A Non-exhaustive List)
With ultra-low power consumption, ESP32-H2 is an ideal choice for IoT devices in the following areas:
• Smart Home – Baby monitor
– Light control • Consumer Electronics
– Smart button – Smart watch and bracelet

– Smart plug – Over-the-top (OTT) devices
– Indoor positioning
– Meter reading systems
– Security systems
– HVAC systems
• Industrial Automation
IN – Logger toys and proximity sensing toys
– Gaming consoles
– Wireless remote controls
• Smart Agriculture
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– Smart greenhouse
– Industrial robot
– Smart irrigation
– Mesh network
– Agricultural robot
– Human machine interface (HMI)
– Livestock tracking
– Industrial field bus
– Asset management • Retail and Catering
– Personnel tracking – Service robot

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• Health Care • Generic Low-power IoT Sensor Hubs
– Health monitor • Generic Low-power IoT Data Loggers
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf
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Contents
Contents
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Product Overview 1
Block Diagram 2
Features 3
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Applications 4
1 ESP32-H2 Series Comparison 9

1.1 Nomenclature 9
1.2 Comparison 9
2 Pin Definition 10
2.1 Pin Layout 10
2.2 Pin Description 10
2.3 Power Scheme 11
2.4
3
3.1
Strapping Pins
2.4.1
2.4.2
2.4.3
Chip Boot Mode Control
ROM Messages Printing Control
JTAG Signal Source Control
Functional Description
CPU and Memory
IN 12
13
13
14
16
16
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3.1.1 CPU 16
3.1.2 Internal Memory 16
3.1.3 Cache 16
3.2 System Clocks 16
3.2.1 CPU Clock 16
3.2.2 RTC Clock 17
3.3 Access Permission Management 17
3.3.1 Access Permission Management (APM) 17
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3.3.2 Timeout Protection 17

3.4 Analog Peripherals 17
3.4.1 Analog-to-Digital Converter (ADC) 18
3.4.2 Temperature Sensor 18
3.5 Digital Peripherals 18
3.5.1 General Purpose Input/Output Interface (GPIO) 18
3.5.2 Serial Peripheral Interface (SPI) 19
3.5.3 Universal Asynchronous Receiver Transmitter (UART) 20
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3.5.4 I2C Interface 20

3.5.5 I2S Interface 20
3.5.6 Remote Control Peripheral 20
3.5.7 LED PWM Controller 20
3.5.8 General DMA Controller 21
3.5.9 USB Serial/JTAG Controller 21
3.5.10 SoC Event Task Matrix (ETM) 21

Contents
3.5.11 Motor Control PWM (MCPWM) 22

3.5.12 Pulse Count Controller (PCNT) 22
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®
3.5.13 TWAI Controller 22
3.5.14 Parallel IO (PARLIO) Controller 22
3.6 Radio 23
3.6.1 2.4 GHz Receiver 23
3.6.2 2.4 GHz Transmitter 23
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3.6.3 Clock Generator 23
3.7 Bluetooth Low Energy 23
3.7.1 Bluetooth LE PHY 24
3.7.2 Bluetooth LE Link Controller 24
3.8 802.15.4 24
3.8.1 802.15.4 PHY 24
3.8.2 802.15.4 MAC 25
3.9 Radio Protocols Coexistence 25
3.10 Low-power Management 25
3.11
3.12
3.13
3.14
Timers
3.11.1 General Purpose Timers
3.11.2 System Timer
3.11.3 Watchdog Timers
Cryptographic Hardware Accelerators
Physical Security Features
Peripheral Pin Configurations
IN 25
25
26
26
26
27
27
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4 Electrical Characteristics 30
4.1 Absolute Maximum Ratings 30
4.2 Recommended Operating Conditions 30
4.3 VDD_SPI Output Characteristics 31
4.4 DC Characteristics (3.3 V, 25 °C) 31
4.5 Current Consumption Characteristics 31
4.5.1 Current Consumption in Active Mode 31
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4.5.2 Current Consumption in Other Modes 32
5 RF Characteristics 34
5.1 Bluetooth 5 (LE) Radio 34
5.1.1 Bluetooth LE RF Transmitter (TX) Characteristics 34
5.1.2 Bluetooth LE RF Receiver (RX) Characteristics 35
5.2 802.15.4 Radio 37
5.2.1 802.15.4 RF Transmitter (TX) Characteristics 38
5.2.2 802.15.4 RF Receiver (RX) Characteristics 38
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6 Packaging 39
7 Related Documentation and Resources 40
Revision History 41

List of Tables
List of Tables
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1-1 ESP32-H2 Series Comparison 9
2-1 Pin Description 10
2-2 Description of ESP32-H2 Power Supply Pins 11
2-3 Description of ESP32-H2 Power-up and Reset Timing Parameters 12
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2-4 Default Configuration of Strapping Pins 12
2-5 Boot Mode Control 13
2-6 ROM Message Printing Control 13
2-7 JTAG Signal Source Control 14
2-8 Parameter Descriptions of the Setup and Hold Time for the Strapping Pin 15
3-1 IO MUX Pin Functions 18
3-2 Peripheral Pin Configurations 27
4-1 Absolute Maximum Ratings 30
4-2 Recommended Operating Conditions 30
4-3 VDD_SPI Output Characteristics 31
4-4
4-5
4-6
4-7
4-8
4-8
5-1
DC Characteristics (3.3 V, 25 °C)
Current Consumption in Modem-sleep Mode

Current Consumption in Low-Power Modes
Current Consumption in Low-Power Modes
Bluetooth LE RF Characteristics
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Current Consumption for Bluetooth LE in Active Mode
Current Consumption for 802.15.4 in Active Mode
31
32
32
32
32
33
34
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5-2 Bluetooth LE - Transmitter Characteristics - 1 Mbps 34
5-3 Bluetooth LE - Transmitter Characteristics - 2 Mbps 34
5-4 Bluetooth LE - Transmitter Characteristics - 125 Kbps 35
5-5 Bluetooth LE - Transmitter Characteristics - 500 Kbps 35
5-6 Bluetooth LE - Receiver Characteristics - 1 Mbps 36
5-7 Bluetooth LE - Receiver Characteristics - 2 Mbps 36
5-8 Bluetooth LE - Receiver Characteristics - 125 Kbps 37
5-9 Bluetooth LE - Receiver Characteristics - 500 Kbps 37
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5-10 802.15.4 RF Characteristics 38

5-11 802.15.4 Transmitter Characteristics - 250 Kbps 38
5-12 802.15.4 Receiver Characteristics - 250 Kbps 38
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List of Figures
List of Figures
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1-1 ESP32-H2 Series Nomenclature 9
2-1 ESP32-H2 Pin Layout (Top View) 10
2-2 ESP32-H2 Power-up and Reset Timing 12
2-3 Setup and Hold Times for the Strapping Pin 15
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6-1 QFN32 (4×4 mm) Package 39
IN
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1 ESP32-H2 Series Comparison
1 ESP32-H2 Series Comparison
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1.1 Nomenclature
ESP32-H2 F H x
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Flash
Flash temperature
H: High temperature
N: Normal temperature
IN In-package flash
Chip series
Figure 1-1. ESP32-H2 Series Nomenclature

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1.2 Comparison
Table 1-1. ESP32-H2 Series Comparison
Ordering Code In-package Flash Ambient Temperature (°C) SPI Voltage Package
ESP32-H2FH2 2 MB (Quad SPI) –40 ∼ 105 3.3 V QFN32
ESP32-H2FH4 4 MB (Quad SPI) –40 ∼ 105 3.3 V QFN32
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2 Pin Definition
2 Pin Definition
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2.1 Pin Layout
VDD3P3
VDD3P3
VDD3P3
XTAL_N
GPIO27
GPIO26
XTAL_P
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ANT
32
31
30
29
28
27
26
25
VDD3P3 1 24 GPIO25
VDD3P3 2 23 U0TXD
GPIO0 3 22 U0RXD
GPIO1 4 21 GPIO22
MTMS
MTDO
MTCK
5
7
IN
ESP32-H2
20 VDDPST2
19 VDDA_PMU
18 VBAT
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MTDI 8 17 CHIP_EN
GPIO8 10
GPIO9 11
GPIO10 12
GPO11 13
GPIO12 14
XTAL_32K_P 15
XTAL_32K_N 16
9
VDDPST1
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Figure 2-1. ESP32-H2 Pin Layout (Top View)
2.2 Pin Description
Table 2-1. Pin Description
Name No. Type1 Power Supply Pin Function

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VDD3P3 1 PA — Analog power supply (3.3 V)

GPIO0 3 I/O/T VDDPST1 GPIO0, FSPIQ
GPIO1 4 I/O/T VDDPST1 GPIO1, FSPICS0, ADC1_CH0
MTMS 5 I/O/T VDDPST1 GPIO2, FSPIWP, ADC1_CH1, MTMS
MTDO 6 I/O/T VDDPST1 GPIO3, FSPIHD, ADC1_CH2, MTDO

2 Pin Definition
Name No. Type Power Supply Pin Function

MTCK 7 I/O/T VDDPST1 GPIO4, FSPICLK, ADC1_CH3, MTCK
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MTDI 8 I/O/T VDDPST1 GPIO5, FSPID, ADC1_CH4, MTDI
VDDPST1 9 PIO — 3.3 V IO power supply
GPIO8 10 I/O/T VDDPST1 GPIO8
GPIO9 11 I/O/T VDDPST1 GPIO9
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GPIO10 12 I/O/T VDDPST1 GPIO10, ZCD0
GPIO11 13 I/O/T VDDPST1 GPIO11, ZCD1
GPIO12 14 I/O/T VDDA_PMU/VBAT GPIO12
XTAL_32K_P 15 I/O/T VDDA_PMU/VBAT GPIO13, XTAL_32K_P
XTAL_32K_N 16 I/O/T VDDA_PMU/VBAT GPIO14, XTAL_32K_N
High: on, enables the chip. Low: off, the chip powers
CHIP_EN 17 I VBAT
off. Note: Do not leave the CHIP_EN pin floating.
Analog power supply or battery power supply (3.0 ~
VBAT 18 PA —
3.6 V)
VDDA_PMU 19 PA — Analog power supply (3.3 V)
VDDPST2
GPIO22
U0RXD
U0TXD
GPIO25
GPIO26
GPIO27
20
21
22
23
24
25
26
PIO
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
—
VDDPST2
VDDPST2
VDDPST2
VDDPST2
VDDPST2
VDDPST2
IN 3.3 V IO power supply
GPIO22
GPIO23, FSPICS1, U0RXD
GPIO24, FSPICS2, U0TXD
GPIO25, FSPICS3
GPIO26, FSPICS4, USB_D-
GPIO27, FSPICS5, USB_D+
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VDD3P3 27 PA — Analog Power supply (3.3 V)
XTAL_N 28 — — External crystal output
XTAL_P 29 — — External crystal input
ANT 32 I/O — RF input and output
GND 33 G — Ground
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1
PA : analog power supply; PD : digital power supply; PIO : IO pin power supply; I: input; O: output; T: high
impedance.
2.3 Power Scheme
Table 2-2. Description of ESP32-H2 Power Supply Pins
Type Pin Name Power Supply to

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VDDPST1 Group0 IO1

PIO
VDDPST2 Group1 IO1
VDDA_PMU
PA VDD3P3 Analog System
VBAT
1
For a complete list of IO pins powered by VDDPST1 and VDDPST2, see Table 2-1.

2 Pin Definition
Notes on CHIP_EN:
Figure 2-2 shows the power-up and reset timing of ESP32-H2. Details about the parameters are listed in Table
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2-3.
t0 t1
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2.8 V
Power Supply Pins
VIL_nRST
CHIP_EN
Figure 2-2. ESP32-H2 Power-up and Reset Timing
t0
t1
Description
CHIP_EN
IN
Table 2-3. Description of ESP32-H2 Power-up and Reset Timing Parameters
Parameter
*
Time between bringing up the power supply pins and activating
Duration of CHIP_EN signal level < VIL_nRST (see Table 4-4) to

reset the chip
Min (µs)
50
50
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*
For a complete list of power supply pins, see Table 2-2.
2.4 Strapping Pins

At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to
load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work
as normal function pins.
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ESP32-H2 has the following parameters controlled by the given strapping pins at chip reset:
• Chip boot mode – GPIO8 and GPIO9
• ROM message printing – GPIO8
• JTAG signal source – GPIO25
GPIO9 is connected to the chip’s internal weak pull-up resistor at chip reset. This resistor determines the default
bit value of GPIO9. Also, the resistor determines the bit value if GPIO9 is connected to an external
high-impedance circuit.
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Table 2-4. Default Configuration of Strapping Pins
Strapping Pin Default Config Bit Value

GPIO8 Floating –
GPIO9 Pull-up 1
GPIO25 Floating –

2 Pin Definition
To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If the
ESP32-H2 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by the host
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MCU.
All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping
pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in
any other way. It makes the strapping pin values available during the entire chip operation, and the pins are freed
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up to be used as regular IOs after reset.
2.4.1 Chip Boot Mode Control

After the reset is released, the combination of GPIO8 and GPIO9 controls the boot mode. See Table 2-5 Boot
Mode Control.
Table 2-5. Boot Mode Control
Boot Mode GPIO8 GPIO9

Default Config – (Floating) 1 (Pull-up)
SPI Boot
Download Boot
IN
Invalid combination
1
1
Any value
1
0
1
0
0
This combination triggers unexpected behav-

ior and should be avoided.
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2.4.2 ROM Messages Printing Control
During the ROM boot stage of SPI Boot mode, GPIO8, LP_AON_STORE4_REG[0] and
EFUSE_UART_PRINT_CONTROL jointly control the printing of ROM messages.
Table 2-6. ROM Message Printing Control
Register1 eFuse2 GPIO8 ROM Message Printing

3
0 (0b00) x ROM messages are always printed to UART0 dur-
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ing boot
0 Print is enabled during boot
0 1 (0b01)
1 Print is disabled during boot
0 Print is disabled during boot
2 (0b10)
1 Print is enabled during boot
3 (0b11) x Print is disabled during boot
1 x x Print is disabled during boot
1
Register: LP_AON_STORE4_REG[0]
2
eFuse: EFUSE_UART_PRINT_CONTROL
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3
x: x indicates that the value has no effect on the result and can be ignored.
ROM message is printed to UART0 and USB Serial/JTAG Controller by default during power-on. Users can
disable the printing to USB Serial/JTAG Controller by setting the eFuse bit
EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT.

2 Pin Definition
Note that if EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT is set to 0 to print to USB, but the USB Serial/JTAG
Controller has been disabled, then ROM messages will not be printed to USB Serial/JTAG Controller.
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Detailed description about the above-mentioned registers can be found in
ESP32-H2 Technical Reference Manual
2.4.3 JTAG Signal Source Control
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The strapping pin GPIO25 can be used to control the source of JTAG signals during the early boot process. This
pin does not have any internal pull resistors and the strapping value must be controlled by the external circuit that
cannot be in a high impedance state.
As Table 2-7 shows, GPIO25 is used in combination with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and
EFUSE_JTAG_SEL_ENABLE.
Table 2-7. JTAG Signal Source Control
eFuse 1a eFuse 2b eFuse 3c GPIO25 JTAG Signal Source

0 Ignored USB Serial/JTAG Controller
a
0
0
1
1
0
1
0
1
1
Ignored
Ignored
Ignored
eFuse 1: EFUSE_DIS_PAD_JTAG
IN
0
1
Ignored
Ignored
Ignored
JTAG pins MTDI, MTCK, MTMS, and MTDO
USB Serial/JTAG Controller
JTAG pins MTDI, MTCK, MTMS, and MTDO
USB Serial/JTAG Controller
JTAG is disabled
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b
eFuse 2: EFUSE_DIS_USB_JTAG
c
eFuse 3: EFUSE_JTAG_SEL_ENABLE
Detailed description about the above-mentioned registers can be found in

ESP32-H2 Technical Reference Manual
Figure 2-3 shows the setup and hold time for the strapping pin before and after the CHIP_EN signal goes high.
Details about the parameters are listed in Table 2-8.
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2 Pin Definition
t0 t1
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VIL_nRST
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CHIP_EN
VIH
Strapping pin
Figure 2-3. Setup and Hold Times for the Strapping Pin
Parameter
t0
Description
IN
Table 2-8. Parameter Descriptions of the Setup and Hold Time for the Strapping Pin
Setup time before CHIP_EN goes from low to high

Min
(ms)
0
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t1 Hold time after CHIP_EN goes high 3
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3 Functional Description
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3.1 CPU and Memory
3.1.1 CPU
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ESP32-H2 has a low-power 32-bit RISC-V single-core microprocessor with the following features:
• Four-stage pipeline that supports a clock frequency of up to 96 MHz
• RV32IMAC instruction set architecture
• 32-bit multiplier and 32-bit divider
• Up to 32 vectored interrupts at 15 priority levels
• Up to 4 hardware breakpoints/watchpoints
• Up to 16 PMP/PMA regions
• JTAG for debugging
• Compliant with RISC-V debug specification v0.13
• Compliant with RISC-V Trace Specification v1.0
3.1.2 Internal Memory

ESP32-H2’s internal memory includes:
IN
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• 128 KB of ROM: for booting and core functions
• 320 KB of SRAM: for data and instructions.
• LP memory: 4 KB of SRAM that can be accessed by the CPU. It can retain data in Deep-sleep mode
• 4 Kbit of eFuse: 1792 bits are reserved for user data, such as encryption key and device ID
• 2 MB or 4 MB of in-package flash
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3.1.3 Cache
ESP32-H2 has an eight-way set associative cache. This cache is read-only and has the following features:
• Size: 16 KB
• Block size: 32 bytes
• Pre-load function
• Lock function
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• Critical word first and early restart
3.2 System Clocks

3.2.1 CPU Clock
The CPU clock has four possible sources:

• External main crystal clock
• Internal fast RC oscillator (typically about 17.5 MHz, and adjustable)
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• 96 MHz PLL clock
• 64 MHz PLL clock
The application can select the clock source from the four clocks above. The selected clock source drives the
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CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock
source would be the external main crystal clock.
Note:
ESP32-H2 is unable to operate without an external main crystal clock.
3.2.2 RTC Clock

The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible
sources:
• XTAL32K_CLK (32 kHz): external crystal clock
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• RC_SLOW_CLK (150 kHz by default): internal slow RC oscillator with adjustable frequency
• OSC_SLOW_CLK (32 kHz by default): external slow clock input through XTAL_32K_P
The RTC fast clock is used for RTC peripherals and sensor controllers. It has three possible sources:
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• External main crystal clock divided by 2
• RC_FAST_CLK (8 MHz by default): internal fast RC oscillator with adjustable frequency
• PLL_LP_CLK (8 MHz): internal PLL clock, with reference clock XTAL32K_CLK
3.3 Access Permission Management

3.3.1 Access Permission Management (APM)
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ESP32-H2 integrates an APM module to manage access permissions. The module compares information
transmitted over the bus with predefined configurations and decides if to grant access.
3.3.2 Timeout Protection

ESP32-H2 integrates 3 timeout protection modules in CPU peripherals, HP peripherals and LP peripherals,
respectively, against bus being stuck. These modules have the following features:
• Integrate a 16-bit timeout counter for each timeout period

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• Support for interrupts
• Exception records
3.4 Analog Peripherals

3.4.1 Analog-to-Digital Converter (ADC)
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ESP32-H2 integrates one 12-bit SAR ADC which supports measurements on 5 channels (analog-enabled
pins).
3.4.2 Temperature Sensor
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The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via
an ADC into a digital value.
The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O
load. Generally, the chip’s internal temperature is higher than the ambient temperature.
3.5 Digital Peripherals

3.5.1 General Purpose Input/Output Interface (GPIO)
IN
ESP32-H2 has 19 GPIO pins which can be assigned various functions by configuring corresponding registers.
Besides digital signals, some GPIOs can be also used for analog functions, such as ADC.
All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are
configured as an input, the input value can be read by software through the register. Input GPIOs can also be set
to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting
and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other
functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state.
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The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide
highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while
peripheral output signals can be configured to any IO pins. Table 3-1 shows the IO MUX functions of each pin.
For more information about IO MUX and GPIO matrix, please refer to Chapter IO MUX and GPIO Matrix (GPIO,
IO_MUX) in ESP32-H2 Technical Reference Manual.
Table 3-1. IO MUX Pin Functions

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Name No. Function 0 Function 1 Function 2 Reset Notes

GPIO0 3 GPIO0 GPIO0 FSPIQ 0 —
GPIO1 4 GPIO1 GPIO1 FSPICS0 0 R
MTMS 5 MTMS GPIO2 FSPIWP 1 R
MTDO 6 MTDO GPIO3 FSPIHD 1 R
MTCK 7 MTCK GPIO4 FSPICLK 1* R
MTDI 8 MTDI GPIO5 FSPID 1 R
GPIO8 10 GPIO8 GPIO8 — 1 —
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GPIO10 12 GPIO10 GPIO10 — 0 R
GPIO11 13 GPIO11 GPIO11 — 0 R
XTAL_32K_P 15 GPIO13 GPIO13 — 0 R
XTAL_32K_N 16 GPIO14 GPIO14 — 0 R

Name No. Function 0 Function 1 Function 2 Reset Notes

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U0RXD 22 U0RXD GPIO23 FSPICS1 3 —
U0TXD 23 U0TXD GPIO24 FSPICS2 4 —
GPIO25 24 GPIO25 GPIO25 FSPICS3 1 —
GPIO26 25 GPIO26 GPIO26 FSPICS4 1 R, USB
AR
GPIO27 26 GPIO27 GPIO27 FSPICS5 3* R, USB
Reset
The default configuration of each pin after reset:
• 0 - input disabled, in high impedance state (IE = 0)
• 1 - input enabled, in high impedance state (IE = 1)
• 2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
• 3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
IN
• 4 - output enabled, pull-up registor enabled (OE = 1, WPU = 1)
• 1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is

0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
1, input enabled, in high impedance state (IE = 1)
• 3* - input enabled, pull-up resistor enabled (IE = 1, WPU = 0, USB_WPU = 1). See details in Notes
IM
We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power
consumption. You may add pull-up and pull-down resistors in your PCB design, or enable internal pull-up and
pull-down resistors during software initialization.
Notes
• R - These pins have analog functions.
• USB - The pull-up value of a USB pin is controlled by the pin’s pull-up value together with the USB pull-up
value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be enabled. The pull-up resistors of
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USB pins are controlled by the USB_SERIAL_JTAG_DP_PULLUP bit.
3.5.2 Serial Peripheral Interface (SPI)

ESP32-H2 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can only be configured to operate
in SPI memory mode, while SPI2 can be configured to operate in both SPI memory and general-purpose SPI
modes.
• SPI Memory mode

PR
In SPI memory mode, SPI0, SPI1 and SPI2 interface with in-package flash. Data is transferred in bytes. Up
to four-line SDR reads and writes are supported. The clock frequency is configurable to a maximum of 64
MHz in SDR mode.
• SPI2 General-purpose SPI (GP-SPI) mode
When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master

and slave modes. The host’s clock frequency is configurable. Data is transferred in bytes. The clock
polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can be connected to GDMA.
Y
– In master mode, the clock frequency is 48 MHz at most, and the four modes of SPI transfer format are
supported.
– In slave mode, the clock frequency is 48 MHz at most, and the four modes of SPI transfer format are
also supported.
AR
3.5.3 Universal Asynchronous Receiver Transmitter (UART)
ESP32-H2 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous
communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow
control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces are connected
to GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU.
3.5.4 I2C Interface

ESP32-H2 has two I2C bus interfaces which are used for I2C master mode or slave mode, depending on the
user’s configuration. The I2C interfaces support:
• Standard mode (100 Kbit/s)
• Fast mode (400 Kbit/s) IN

• Up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)
• 7-bit and 10-bit addressing mode

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• Double addressing mode
• 7-bit broadcast address
Users can configure instruction registers to control the I2C interfaces for more flexibility.
3.5.5 I2S Interface

ESP32-H2 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex
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mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK
clock frequency, from 10 kHz up to 40 MHz, is supported.
The I2S interface supports TDM PCM, TDM MSB alignment, TDM standard, and PDM TX interface. It connects
to the GDMA controller.
3.5.6 Remote Control Peripheral

The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels
of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and
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other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive
waveform.
3.5.7 LED PWM Controller

The LED PWM controller can generate independent digital waveform on six channels. The LED PWM controller
supports:

• Generating digital waveform with configurable periods and duty cycle. The resolution of duty cycle can be
up to 20 bits.
Y
• Multiple clock sources, including 96 MHz PLL clock, 64 MHz PLL clock, external main crystal clock, and
internal fast RC oscillator.
• Operation when the CPU is in Light-sleep mode.
AR
• Gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator.
• Up to 16 duty cycle ranges for gamma curve generation, each can be independently configured in terms of
duty cycle direction (increase or decrease), step size, the number of steps, and step frequency
3.5.8 General DMA Controller

ESP32-H2 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and
three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller
supports fixed priority arbiter or round robin arbiter among these channels.
The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and
3.5.9 USB Serial/JTAG Controller

IN
memory-to-memory data transfer at a high speed. All channels can access internal RAM.
Peripherals on ESP32-H2 with DMA feature are SPI2, UHCI0, I2S, PARLIO, AES, SHA, and ADC.
ESP32-H2 integrates a USB Serial/JTAG controller. This controller has the following features:
• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not
IM
support the faster 480 Mbit/s high-speed transfer mode)
• CDC-ACM virtual serial port and JTAG adapter functionality
• Programming the chip’s flash
• CPU debugging with compact JTAG instructions
• A full-speed USB PHY integrated in the chip

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3.5.10 SoC Event Task Matrix (ETM)

ESP32-H2 integrates a SOC ETM with multiple channels. Each input event on channels is mapped to an output
task. Events are generated by peripherals, while tasks are received by peripherals. The SOC ETM has the
following features:
• up to 50 mapping channels, each connected to an event and a task and controlled independently
• an event or a task can be mapped to any tasks or events in the matrix. That is to say, one event can be
mapped to different tasks via multiple channels, or different events can be mapped to the same task via
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their individual channels
• peripherals supporting ETM include GPIO, LED PWM, general-purpose timers, RTC Watchdog Timer,
system timer, RMT, MCPWM, temperature sensor, ADC, I2S, GDMA, and PMU

3.5.11 Motor Control PWM (MCPWM)
Y
ESP32-H2 integrates a MCPWM that can be used to drive digital motors and smart light. This controller has a
clock divider (prescaler), three PWM timers, three PWM operators, and a dedicated capture submodule.
PWM timers are used to generate timing references. The PWM operators generate desired waveform based on
the timing references. By configuration, a PWM operator can use the timing reference of any PWM timer, and use
the same timing reference with other PwM operators. PWM operators can also use different PWM timers’ values
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to produce independent PWM signals. PWM timers can be synchronized.
3.5.12 Pulse Count Controller (PCNT)

The pulse count controller (PCNT) in ESP32-H2 captures pulses and counts pulse edges in seven modes. It has
the following features:
• Four independent pulse counters (units) that count from 1 to 65535
• Each unit consists of two independent channels sharing one pulse counter
• All channels have input pulse signals (e.g. sig_ch0_un) with their corresponding control signals (e.g.
ctrl_ch0_un)
(ctrl_ch0_un and ctrl_ch1_un) on each unit
• Each channel has the following parameters:

IN
• Independently filter glitches of input pulse signals (sig_ch0_un and sig_ch1_un) and control signals
1. Selection between counting on positive or negative edges of the input pulse signal
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2. Configuration to Increment, Decrement, or Disable counter mode for control signal’s high and low
states
3.5.13 TWAI® Controller

ESP32-H2 has one TWAI® controllers with the following features:
• Compatible with ISO 11898-1 protocol (CAN Specification 2.0)
• Standard frame format (11-bit ID) and extended frame format (29-bit ID)
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• Bit rates from 1 Kbit/s to 1 Mbit/s
• Multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
• 64-byte receive FIFO
• Acceptance filter (single and dual filter modes)
• Error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture
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3.5.14 Parallel IO (PARLIO) Controller

ESP32-H2 contains a Parallel IO controller (PARLIO) capable of transferring data between external devices and
internal memory on a parallel bus through GDMA. It is composed of a TX unit and a RX unit, which are fixed as a
transmitter and a receiver respectively. With the two units combined, PARLIO achieves full-duplex
communication.

Due to the flexibility of IO data, PARLIO can function as a general interface to connect various peripherals. For
example, a peer-to-peer transfer can be achieved by taking SPI as the master device and PARLIO as the slave
Y
device.
3.6 Radio
The ESP32-H2 radio consists of the following blocks:
AR
• 2.4 GHz receiver
• 2.4 GHz transmitter
• Bias and regulators
• Balun and transmit-receive switch
• Clock generator
3.6.1 2.4 GHz Receiver
IN
The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to baseband signals and converts them to the digital
domain with two high-resolution ADCs. To adapt to varying signal channel conditions, ESP32-H2 integrates RF
filters, Automatic Gain Control (AGC), DC offset cancellation circuits, and baseband filters.
3.6.2 2.4 GHz Transmitter

The 2.4 GHz transmitter modulates the baseband signals to the 2.4 GHz RF signal, and drives the antenna with a
IM
CMOS power amplifier.
Additional calibrations are integrated to cancel any radio imperfections, such as:
• Carrier leakage
• I/Q amplitude/phase matching
These built-in calibration routines reduce the cost, time, and specialized equipment required for product
testing.
EL
3.6.3 Clock Generator

The clock generator produces clock signals of 2.4 GHz for both the receiver and the transmitter. All components
of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and
dividers.
The clock generator has built-in calibration and self-test circuits. Clock phases and phase noise are optimized on
chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter.
PR
3.7 Bluetooth Low Energy

ESP32-H2 includes a Bluetooth Low Energy subsystem that integrates a link controller, an RF/modem block and
a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Bluetooth mesh.

3.7.1 Bluetooth LE PHY
Y
ESP32-H2’s Bluetooth Low Energy PHY supports:
• 1 Mbps PHY
• 2 Mbps PHY for higher data rates
• Coded PHY for longer range (125 Kbps and 500 Kbps)
AR
• HW Listen before talk (LBT)
3.7.2 Bluetooth LE Link Controller

ESP32-H2’s Bluetooth Low Energy Link Controller supports:
• LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data
• Multiple advertisement sets
• Simultaneous advertising and scanning
• Channel selection algorithm #2
• LE power control
• Connection parameter update

IN
• Multiple connections in simultaneous central and peripheral roles
• Adaptive frequency hopping and channel assessment

IM
• High duty cycle non-connectable advertising
• LE privacy 1.2
• LE data packet length extension
• Link layer extended scanner filter policies
• Low duty cycle connectable directed advertising
• Link layer encryption

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• LE Ping
3.8 802.15.4
ESP32-H2 includes an IEEE Standard 802.15.4 subsystem that integrates PHY and MAC layers. It supports
various software stacks includes Thread, Zigbee, Matter, HomeKit, MQTT and so on.
3.8.1 802.15.4 PHY

PR
ESP32-H2 ’s 802.15.4 PHY supports:
• O-QPSK PHY in 2.4 GHz
• 250 Kbps data rate
• RSSI and LQI supported

3.8.2 802.15.4 MAC
Y
ESP32-H2 supports most key features defined in IEEE Standard 802.15.4-2015, includes:
• CSMA/CA
• Active scan and energy detect
• HW frame filter
AR
• HW auto acknowledge
• HW auto frame pending
• Coordinated sampled listening (CSL)
3.9 Radio Protocols Coexistence

ESP32-H2 has a 2.4 GHz radio protocols coexistence controller (COEX) for radio resource management. This
controller supports:
• External coexistence as a slave device

IN
• The coexistence of Bluetooth and IEEE 802.15.4 protocols inside the chip
• External coexistence as a master device
• Multiple external coexistence modes (1-wire PTA, 2-wire PTA and 3-wire PTA)
3.10 Low-power Management

IM
With the use of advanced power-management technologies, ESP32-H2 can switch between different power
modes.
• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
• Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wireless base band
and radio are disabled, but Wireless connection can remain active.
• Light-sleep mode: The CPU is paused. Any wake-up events (host, RTC timer, or external interrupts) will
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wake up the chip. Wireless base band and radio are disabled, but Wireless connection can remain active.
CPU (excluding SRAM) and most peripherals (See ESP32-H2 Block Diagram) can also be powered down
to further reduce the power consumption.
• Deep-sleep mode: CPU (including SRAM) and most peripherals (See ESP32-H2 Block Diagram) are
powered down. Only the LP memory is powered on. Wireless connection data are stored in the LP
memory.
For power consumption in different power modes, please refer to Section 4.5.
PR
3.11 Timers
3.11.1 General Purpose Timers
ESP32-H2 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and
54-bit auto-reload-capable up/down-timers.

The timers’ features are summarized as follows:
• A 16-bit clock prescaler, from 1 to 65536
Y
• A 54-bit time-base counter programmable to be incrementing or decrementing
• Able to read real-time value of the time-base counter
• Halting and resuming the time-base counter
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• Programmable alarm generation
• Level interrupt generation
3.11.2 System Timer

ESP32-H2 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system
timer has the following features:
• Counters with a fixed clock frequency of 16 MHz
• Three types of independent interrupts generated according to alarm value
• Two alarm modes: target mode and period mode
IN
• 52-bit target alarm value and 26-bit periodic alarm value
• Automatic reload of counter value
• Counters can be stalled if the CPU is stalled or in OCD mode

IM
3.11.3 Watchdog Timers
The ESP32-H2 contains three watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT).
During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order
to detect and recover from booting errors.
Watchdog timers have the following features:

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• Four stages, each with a programmable timeout value. Each stage can be configured, enabled and
disabled separately
• Interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage
• 32-bit expiry counter
• Write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
• Flash boot protection

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If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.
3.12 Cryptographic Hardware Accelerators

ESP32-H2 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB
197, against DPA attack), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB

180-4), RSA3072, and ECC accelerator. The chip also supports independent arithmetic, such as large-number
multiplication and large-number modular multiplication. The maximum operation length for RSA and
Y
large-number modular multiplication is 3072 bits. The maximum operator length for large-number multiplication
is 1536 bits.
This chip is also equipped with ECDSA accelerator that supports generating and verifying ECDSA signatures,
which offers higher security compared to software implementation.
AR
3.13 Physical Security Features
• Transparent off-package flash encryption (AES-XTS algorithm) with software inaccessible key prevents
unauthorized readout of user application code or data.
• Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)
can be booted.
• HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity
verification and other purposes.
IN
• Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity
verification.
• TEE controller provides four security modes for masters in the system. Hardware resources can be granted
different access permissions by APM module in these four modes, so as to establish a security boundary
between the four modes.
IM
3.14 Peripheral Pin Configurations
Table 3-2. Peripheral Pin Configurations
Interface Signal Pin Function

ADC ADC1_CH0 GPIO1 12-bit SAR ADC
ADC1_CH1 MTMS
ADC1_CH2 MTDO
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ADC1_CH3 MTCK
ADC1_CH4 MTDI
JTAG MTDI MTDI JTAG for software debugging
MTCK MTCK
MTMS MTMS
MTDO MTDO
UART U0RXD_in U0RXD Two UART channels with hardware flow control
U0CTS_in Any GPIO pins and GDMA
U0DSR_in
PR
U0TXD_out U0TXD
U0RTS_out Any GPIO pins
U0DTR_out
U1RXD_in
U1CTS_in
U1DSR_in


U1TXD_out
Y
U1RTS_out
U1DTR_out
I2C I2CEXT0_SCL_in Any GPIO pins One I2C channel in slave or master mode
I2CEXT0_SDA_in
AR
I2CEXT0_SCL_out
I2CEXT0_SDA_out
LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels
I2S I2SO_BCK_in Any GPIO pins Stereo input and output from/to the audiocodec
I2S_MCLK_in
I2SO_WS_in
I2SI_SD_in
I2SI_BCK_in
I2SI_WS_in
I2SO_BCK_out
Remote Control
I2S_MCLK_out
I2SO_WS_out
I2SO_SD_out
I2SI_BCK_out
I2SI_WS_out
I2SO_SD1_out
RMT_SIG_IN0~1
IN
Any GPIO pins Two channels for an IR transceiver of various
IM
Peripheral RMT_SIG_OUT0~1 waveforms
SPI2 FSPICLK_in/_out_mux Any GPIO pins • Master mode and slave mode of SPI, Dual
FSPICS0_in/_out SPI, Quad SPI, and QPI
FSPICS1~5_out • Connection to in-package flash, RAM, and
FSPID_in/_out other SPI devices
FSPIQ_in/_out • Four modes of SPI transfer format
FSPIWP_in/_out • Configurable SPI frequency
FSPIHD_in/_out • 64-byte FIFO or GDMA buffer
EL
TWAI® TWAI0_RX Any GPIO pins Compatible with ISO 11898-1 protocol (CAN
Specification 2.0)
TWAI0_TX
TWAI0_BUS_OFF_ON
TWAI0_CLKOUT
TWAI0_STANDBY
Pulse counter PCNT_SIG_CH0_in0~3 Any GPIO pins Capture pulse and count pulse edges in seven
modes
PR
PCNT_SIG_CH1_in0~3
PCNT_CTRL_CH0_in0~3
PCNT_CTRL_CH1_in0~3


MCPWM PWM0_SYNC0~2_in Any GPIO pins 1 MCPWM input and output pins. Signals include:
Y
• PWM differential output signals
• fault input signals to be detected
• input signals to be captured
• external clock synchronization signals
AR
PWM0_out0a
PWM0_out0b
PWM0_out1a
PWM0_F0~2_in
PWM0_out1b
PWM0_out2a
PWM0_out2b
PWM0_CAP0~2_in
PARLIO PARL_RX_DATA0~7 Any GPIO pins A module for parallel data transfer, with
PARL_TX_DATA0~7
IN • 8 pins to receive parallel data
• 8 pins to transmit parallel data
• 1 receiver clock pin (clock input and output)
• 2 transmitter clock pins (clock input and out-
put)
IM
PARL_RX_CLK_in/_out
PARL_TX_CLK_in/_out
USB Serial/JTAG USB_D- GPIO26 USB-to-serial converter, and USB-to-JTAG
USB_D+ GPIO27 converter. Note: the pin functions of USB_D+ and
USB_D- are interchangeable.
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PR

4 Electrical Characteristics
Y
The values presented in this section are preliminary and may change with the final release of this
datasheet.
4.1 Absolute Maximum Ratings
AR
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device.
Table 4-1. Absolute Maximum Ratings
Symbol Parameter Min Max Unit

VDD3P3, VBAT, VDDA_PMU, Voltage applied to power supply pins
–0.3 3.6 V
VDDPST1, VDDPST2 per power domain
TST ORE Storage temperature –40 150 °C
4.2 Recommended Operating Conditions
Symbol
VDD3P3, VBAT, VDDA_PMU,
IN
Table 4-2. Recommended Operating Conditions
Parameter Min Typ Max Unit

IM
Power Supply Pin 3.0 3.3 3.6 V
VDDPST1, VDDPST2
IV DD 1 Current delivered by external power supply 0.35 — — A
TA Ambient temperature -40 — 105 °C
1
If you use a single power supply, the recommended output current is 350 mA or more.
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PR

4.3 VDD_SPI Output Characteristics
Y
Table 4-3. VDD_SPI Output Characteristics
Symbol Parameter Typ Unit

RSP I On-resistance in 3.3 V mode 7.5 Ω
AR
In real-life applications, when VDD_SPI works in 3.3 V output mode, VDDPST2 may be affected by
RSP I . For example, when VDDPST2 is used to drive a 3.3 V flash, it should comply with the following
specifications:
VDDPST2 > VDD_flash_min + I_flash_max * RSP I
Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the
maximum current.
For more information, please refer to section 2.3 Power Scheme.
4.4 DC Characteristics (3.3 V, 25 °C)
Symbol
CIN
VIH
VIL
Parameter
Pin capacitance
High-level input voltage
Low-level input voltage
IN
Table 4-4. DC Characteristics (3.3 V, 25 °C)
Min
0.75 × VDD
—
1
–0.3
Typ
—
—
2
Max
1
VDD + 0.3
0.25 × VDD
—
1
Unit
pF
V
V
IM
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
2 1
VOH High-level output voltage 0.8 × VDD — — V
2 1
VOL Low-level output voltage — — 0.1 × VDD V
1
High-level source current (VDD = 3.3 V,
IOH — 40 — mA
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1= 3.3 V, VOL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
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RP U Pull-up resistor — 45 — kΩ
RP D Pull-down resistor — 45 — kΩ
1 1
VIH_nRST Chip reset release voltage 0.75 × VDD — VDD + 0.3 V
1
VIL_nRST Chip reset voltage –0.3 — 0.25 × VDD V
1
VDD is the I/O voltage for a particular power domain of pins.
2
VOH and VOL are measured using high-impedance load.
4.5 Current Consumption Characteristics

PR
4.5.1 Current Consumption in Active Mode

The current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.
TX current consumption is rated at a 100% duty cycle.
RX current consumption is rated when the peripherals are disabled and the CPU idle.

Table 4-5. Current Consumption for Bluetooth LE in Active Mode
Y
Work Mode RF Condition Description Peak (mA)
Bluetooth LE @ 20.0 dBm 148
TX Bluetooth LE @ 9.0 dBm 76
Active (RF working) Bluetooth LE @ 0 dBm 38
Bluetooth LE @ –24.0 dBm 26
AR
RX Bluetooth LE 25
Table 4-6. Current Consumption for 802.15.4 in Active Mode
Work Mode RF Condition Description Peak (mA)

802.15.4 @ 20.0 dBm 153
TX 802.15.4 @ 9.0 dBm 75
Active (RF working) 802.15.4 @ 0 dBm 38
802.15.4 @ –24.0 dBm 26
RX
4.5.2 Current Consumption in Other Modes

IN
802.15.4
Table 4-7. Current Consumption in Modem-sleep Mode
CPU Frequency
Typ (mA)
27
IM
All Peripherals All Peripherals
Mode (MHz) Description
Clocks Disabled Clocks Enabled1
CPU is running 9 13.5
32
CPU is idle 7.5 12
CPU is running 11.5 17
48
CPU is idle 9 14.5
Modem-sleep2
CPU is running 12.5 18.5
64
CPU is idle 9.5 15.5
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CPU is running 15 23
96
CPU is idle 10 18
1
In practice, the current consumption might be different depending on which peripherals are
enabled.
2
In Modem-sleep mode, the consumption might be higher when accessing flash.
Table 4-8. Current Consumption in Low-Power Modes

PR
Mode Description Typ (µA)

CPU and wireless communication modules are powered down, pe-
75
Light-sleep ripheral clocks are disabled, and all GPIOs are high-impedance
CPU, wireless communication modules and peripherals are pow-
32
ered down, and all GPIOs are high-impedance
Deep-sleep RTC timer and LP memory are powered on 5

Table 4-8. Current Consumption in Low-Power Modes
Y
Mode Description Typ (µA)
Power off CHIP_EN is set to low level, the chip is powered off 1
AR
IN
IM
EL
PR

5 RF Characteristics
Y
This section contains tables with RF characteristics of the Espressif product.
The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. The
front-end circuit is a 0 Ω resistor.
AR
Devices should operate in the center frequency range allocated by regional regulatory authorities. The target
center frequency range and the target transmit power are configurable by software. See ESP RF Test Tool and
Test Guide for instructions.
Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient temperature.
5.1 Bluetooth 5 (LE) Radio
Table 5-1. Bluetooth LE RF Characteristics
Name
IN
Center frequency range of operating channel
RF transmit power range
5.1.1 Bluetooth LE RF Transmitter (TX) Characteristics

Description
2402 ~ 2480 MHz
–24.0 ~ 20.0 dBm
IM
Table 5-2. Bluetooth LE - Transmitter Characteristics - 1 Mbps
Parameter Description Min Typ Max Unit

Max. |fn |n=0, 1, 2, 3, ...k — 1.5 — kHz
Max. |f0 − fn |n=2, 3, 4, ...k — 2.8 — kHz
Carrier frequency offset and drift
Max. |fn − fn−5 |n=6, 7, 8, ...k — 1.3 — kHz
|f1 − f0 | — 2.3 — kHz
∆ F 1avg — 251.8 — kHz
EL
Modulation characteristics Min. ∆ F 2max (for at least

— 217.0 — kHz
99.9% of all ∆ F 2max )
∆ F 2avg /∆ F 1avg — 0.87 — —
± 2 MHz offset — –28 — dBm
In-band emissions ± 3 MHz offset — –32 — dBm
> ± 3 MHz offset — –34 — dBm
Table 5-3. Bluetooth LE - Transmitter Characteristics - 2 Mbps

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Max. |fn |n=0, 1, 2, 3, ...k — 3.3 — kHz
Max. |f0 − fn |n=2, 3, 4, ...k — 3.3 — kHz
Max. |fn − fn−5 |n=6, 7, 8, ...k — 1.6 — kHz
|f1 − f0 | — 2.3 — kHz
Cont’d on next page

Table 5-3 – cont’d from previous page

Y
∆ F 1avg — 499.9 — kHz
Modulation characteristics Min. ∆ F 2max (for at least
— 492.0 — kHz
99.9% of all ∆ F 2max )
∆ F 2avg /∆ F 1avg — 0.90 — —
AR
Table 5-4. Bluetooth LE - Transmitter Characteristics - 125 Kbps

Max. |fn |n=0, 1, 2, 3, ...k — 1.0 — kHz
Max. |f0 − fn |n=1, 2, 3, ...k — 0.5 — kHz
|f0 − f3 | — 0.4 — kHz
Modulation characteristics
In-band emissions
∆ F 1avg
IN
Max. |fn − fn−3 |n=7, 8, 9, ...k
Min. ∆ F 1max (for at least

99.9% of all ∆ F 1max )
± 2 MHz offset
± 3 MHz offset
> ± 3 MHz offset
—
—
—
—
—
0.9
250.5
234.0
–23
–34
–42
—
—
—
—
—
kHz
kHz
kHz
dBm
dBm
dBm
IM
Table 5-5. Bluetooth LE - Transmitter Characteristics - 500 Kbps

Max. |fn |n=0, 1, 2, 3, ...k — 2.3 — kHz
Max. |f0 − fn |n=1, 2, 3, ...k — 0.7 — kHz
|f0 − f3 | — 0.3 — kHz
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Max. |fn − fn−3 |n=7, 8, 9, ...k — 1.1 — kHz

∆ F 2avg — 230.6 — kHz
Modulation characteristics
Min. ∆ F 2max (for at least
— 221.8 — kHz
99.9% of all ∆ F 2max )
PR
Note that the In-band emissions in Table 5-2 and Table 5-5 above are tested at 15 dBm of TX power. However,
the test result still meets the Bluetooth SIG standard even if the TX power is increased up to 20 dBm.
5.1.2 Bluetooth LE RF Receiver (RX) Characteristics

Table 5-6. Bluetooth LE - Receiver Characteristics - 1 Mbps
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Sensitivity @30.8% PER — — –99.0 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel F = F0 MHz — 4 — dB
F = F0 + 1 MHz — 2 — dB
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F = F0 – 1 MHz — 0 — dB
F = F0 + 2 MHz — –29 — dB
F = F0 – 2 MHz — –29 — dB
Adjacent channel
C/I and receiver F = F0 + 3 MHz — –35 — dB
selectivity performance F = F0 – 3 MHz — –36 — dB
F ≥ F0 + 4 MHz — –30 — dB
F ≤ F0 – 4 MHz — –36 — dB
Image frequency — — –30 — dB
Adjacent channel to F = Fimage + 1 MHz — –32 — dB
image frequency
Out-of-band blocking performance
Intermodulation
IN
F = Fimage – 1 MHz
30 MHz ~ 2000 MHz
2003 MHz ~ 2399 MHz
2484 MHz ~ 2997 MHz
3000 MHz ~ 12.75 GHz
—
—
—
—
—
—
—
–35
–16
–12
–16
–35
0
—
—
—
—
—
—
dB
dBm
dBm
dBm
dBm
dBm
IM
Table 5-7. Bluetooth LE - Receiver Characteristics - 2 Mbps

F = F0 + 2 MHz — 1 — dB
F = F0 – 2 MHz — –2 — dB
EL
F = F0 + 4 MHz — –27 — dB
F = F0 – 4 MHz — –32 — dB
Adjacent channel
F ≥ F0 + 8 MHz — –36 — dB
F ≤ F0 – 8 MHz — –36 — dB
PR
image frequency F = Fimage – 2 MHz — 1 — dB

30 MHz ~ 2000 MHz — –17 — dBm
Out-of-band blocking performance 2003 MHz ~ 2399 MHz — –27 — dBm
2484 MHz ~ 2997 MHz — –17 — dBm
3000 MHz ~ 12.75 GHz — 0 — dBm
Intermodulation — — –27 — dBm

Y
Table 5-8. Bluetooth LE - Receiver Characteristics - 125 Kbps

AR
F = F0 + 1 MHz — –4 — dB
F = F0 – 1 MHz — –6 — dB
F = F0 + 2 MHz — –31 — dB
F = F0 – 2 MHz — –34 — dB
Adjacent channel
F ≥ F0 + 4 MHz — –35 — dB
F ≤ F0 – 4 MHz — –48 — dB
Parameter
Image frequency
Adjacent channel to
image frequency
IN
—
F = Fimage + 1 MHz
F = Fimage – 1 MHz
—
—
—
Table 5-9. Bluetooth LE - Receiver Characteristics - 500 Kbps
Description Min
–39
–38
–39
Typ
—
—
—
Max
dB
dB
dB
Unit
IM
F = F0 + 1 MHz — –1 — dB
F = F0 – 1 MHz — –4 — dB
F = F0 + 2 MHz — –28 — dB
F = F0 – 2 MHz — –29 — dB
Adjacent channel
EL

F ≥ F0 + 4 MHz — –33 — dB
F ≤ F0 – 4 MHz — –41 — dB
image frequency F = Fimage – 1 MHz — –38 — dB
PR
5.2 802.15.4 Radio

Table 5-10. 802.15.4 RF Characteristics
Y
Name Description
Center frequency range of operating channel 2405 ~ 2480 MHz
1
Zigbee in the 2.4 GHz range supports 16 channels at 5 MHz spacing from
channel 11 to channel 26.
AR
5.2.1 802.15.4 RF Transmitter (TX) Characteristics
Table 5-11. 802.15.4 Transmitter Characteristics - 250 Kbps
Parameter Min Typ Max Unit

RF transmit power range –24.0 — 20.0 dBm
EVM — 3.5% — —
5.2.2 802.15.4 RF Receiver (RX) Characteristics
Parameter
Sensitivity @1% PER
Maximum received signal @1% PER
IN
Table 5-12. 802.15.4 Receiver Characteristics - 250 Kbps
Description
—
—
F = F0 + 5 MHz
Min
—
—
—
Typ
–102.5
31
8
Max
—
—
—
Unit
dBm
dBm
dB
IM
Adjacent channel
F = F0 – 5 MHz — 43 — dB
Relative jamming level
F = F0 + 10 MHz — 49 — dB
Alternate channel
F = F0 – 10 MHz — 54 — dB
EL
PR

6 Packaging
6 Packaging
Y
• For information about tape, reel, and chip marking, please refer to Espressif Chip Packaging Information.
• The pins of the chip are numbered in anti-clockwise order starting from Pin 1 in the top view. For pin
numbers and pin names, see also Figure 2-1 ESP32-H2 Pin Layout (Top View).
AR
IN
IM
Figure 6-1. QFN32 (4×4 mm) Package
EL
PR

7 Related Documentation and Resources
7 Related Documentation and Resources
Y
Related Documentation
• ESP32-H2 Technical Reference Manual – Detailed information on how to use the ESP32-H2 memory and peripherals.
• ESP32-H2 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-H2 into your hardware product.
• Certificates
AR
https://espressif.com/en/support/documents/certificates
• ESP32-H2 Product/Process Change Notifications (PCN)
https://espressif.com/en/support/documents/pcns?keys=ESP32-H2
• ESP32-H2 Advisories – Information on security, bugs, compatibility, component reliability.
https://espressif.com/en/support/documents/advisories?keys=ESP32-H2
• Documentation Updates and Update Notification Subscription
https://espressif.com/en/support/download/documents
Developer Zone
IN
• ESP-IDF Programming Guide for ESP32-H2 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
https://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
https://esp32.com/
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
IM
https://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
https://espressif.com/en/support/download/sdks-demos
Products
• ESP32-H2 Series SoCs – Browse through all ESP32-H2 SoCs.
https://espressif.com/en/products/socs?id=ESP32-H2
• ESP32-H2 Series Modules – Browse through all ESP32-H2-based modules.
EL
https://espressif.com/en/products/modules?id=ESP32-H2
• ESP32-H2 Series DevKits – Browse through all ESP32-H2-based devkits.
https://espressif.com/en/products/devkits?id=ESP32-H2
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
https://products.espressif.com/#/product-selector?language=en
Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
PR
(Online stores), Become Our Supplier, Comments & Suggestions.

https://espressif.com/en/contact-us/sales-questions

Revision History
Revision History
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Date Version Release notes
2023-05-24 v0.5 Preliminary release
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IN
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PR

Y
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IN
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Disclaimer and Copyright Notice

Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO
WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
PR
All liability, including liability for infringement of any proprietary rights, relating to use of information
in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property
www.espressif.com of their respective owners, and are hereby acknowledged.
Copyright © 2023 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.

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ESP32-H2FH4 (4 MB In-Package Flash)

• A Bluetooth LE subsystem that supports features • Reliable security features ensured by

• 320 KB of SRAM, 128 KB of ROM, 4 KB LP

• Rich set of peripheral interfaces and GPIOs, ideal

Espressif Systems 1 ESP32-H2 Datasheet (Pre-release v0.5)

Core System Wireless MAC and RF

Cache SRAM 2.4 GHz Receiver

Peripherals Power Management

⚙ Temperature ⚙ Brown-out ⚙ Secure⚙ Flash ⚙

Modules having power in specific power modes:

Active, Modem-sleep, Light-sleep ⚙ Optional in Light-sleep

Block Diagram of ESP32-H2

Espressif Systems 2 ESP32-H2 Datasheet (Pre-release v0.5)

and multiple advertising sets – Motor control PWM (MCPWM)

• Simultaneous Broadcaster, Observer, Peripheral – Pulse count controller (PCNT)

• IEEE Standard 802.15.4-2015 compliant

• Supports 250 Kbps data rate in 2.4 GHz band

– General DMA controller (GDMA), with 3

– SoC event task matrix (ETM)

– Parallel IO (PARLIO) controller

– 1 × 52-bit system timer

• 4096-bit OTP, up to 1792 bits for users

– AES-128/256 (FIPS PUB 197, against DPA

Espressif Systems 3 ESP32-H2 Datasheet (Pre-release v0.5)

• Smart Home – Baby monitor

– Light control • Consumer Electronics

– Smart button – Smart watch and bracelet

– Meter reading systems

– Wireless remote controls

– Asset management • Retail and Catering

– Personnel tracking – Service robot

• Health Care • Generic Low-power IoT Sensor Hubs

– Health monitor • Generic Low-power IoT Data Loggers

Espressif Systems 4 ESP32-H2 Datasheet (Pre-release v0.5)

1 ESP32-H2 Series Comparison 9

3.3.2 Timeout Protection 17

3.5.4 I2C Interface 20

Espressif Systems 5 ESP32-H2 Datasheet (Pre-release v0.5)

3.5.11 Motor Control PWM (MCPWM) 22

4.5.2 Current Consumption in Other Modes 32

7 Related Documentation and Resources 40

Espressif Systems 6 ESP32-H2 Datasheet (Pre-release v0.5)

Current Consumption in Modem-sleep Mode

5-10 802.15.4 RF Characteristics 38

Espressif Systems 7 ESP32-H2 Datasheet (Pre-release v0.5)

Espressif Systems 8 ESP32-H2 Datasheet (Pre-release v0.5)

1 ESP32-H2 Series Comparison

Figure 1-1. ESP32-H2 Series Nomenclature

Table 1-1. ESP32-H2 Series Comparison

Espressif Systems 9 ESP32-H2 Datasheet (Pre-release v0.5)

Figure 2-1. ESP32-H2 Pin Layout (Top View)

2.2 Pin Description

Table 2-1. Pin Description

Name No. Type1 Power Supply Pin Function

VDD3P3 1 PA — Analog power supply (3.3 V)

Espressif Systems 10 ESP32-H2 Datasheet (Pre-release v0.5)

Name No. Type Power Supply Pin Function

2.3 Power Scheme