MBEYA UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST)

ORDINARY DIPLOMA IN MECHATRONICS ENGINEERING

DEPARTMENT: MECHANICAL AND INDUSTRIAL ENGINEERING.
MODULE NAME: INDUSTRIAL ELECTRONICS.
MODULE CODE: EE 6275.
NAME OF SUPERVISOR: MR. CUTHBERT JOHN KARAWA.
LEVEL: UQF6 SECOND YEAR.
ACTIVITY: CLASS ASSIGNMENT 2.
GROUP NAME: GROUP 1.
TASK; To discuss about Methods of Analog-to-Digital Conversion.

S/N. NAME OF STUDENT REGISTRATION

NUMBER
1. PROSPER D RIGHENDA 22100123090039
2. MESHACK C MASEHE 22100123090023
3. SELEMANI C ABDALLAH 22100123090027
4. FRANK MAHENGE 22100123010014
5. BENSON A MUSHI 22100123010071
6. STEVE MKUYU 22100123090031
7. DISMASS B ALLAN 22100123090008
8. MATHIAS L MATHIAS 22100123570019
 Analog-to-digital conversion is the process by which an analog quantity is converted to digital form. It
is necessary when measured quantities must be in digital form for processing or for display or storage.

The two important ADC parameters are resolution, which is the number of bits, and throughput, which
is the sampling rate an ADC can handle in units of samples per second (sps).

There are four methods used to comvert analog to digital signal which are;-

 a flash ADC
 dual-slope ADC
 a successive-approximation ADC and
 a delta-sigma ADC

Flash (Simultaneous) Analog-to-Digital Converter

The flash method utilizes special high-speed comparators that compare reference voltages with the
analog input voltage. When the input voltage exceeds the reference voltage for a given comparator, a
HIGH is generated.

In general, 2n − 1 comparators are required for conversion to an n-bit binary code, The number of bits
used in an ADC is its resolution.

chief advantage is that it provides a fast conversion time because of a high throughput, measured in
samples per second (sps).

one of the disadvantages of the flash ADC is having large number of comparators necessary for a
reasonable-sized binary number. Example 3-bit converter that uses seven comparator circuits, A 4-bit
converter of this type requires fifteen comparators.

The reference voltage for each comparator is set by the resistive voltage-divider circuit. The output of
each comparator is connected to an input of the priority encoder. The encoder is enabled by a pulse on
the EN input, and a 3-bit code representing the value of the input appears on the encoder’s outputs. The
binary code is determined by the highest-order input having a HIGH level.
The frequency of the enable pulses and the number of bits in the binary code determine the accuracy
with which the sequence of binary codes represents the input of the ADC. The signal is sampled each
time the enable pulse is active.

Dual-Slope Analog-to-Digital Converter

Another method is dual slope, This method is common in digital voltmeters and other types of
measurement instruments. Having A ramp generator (integrator) that used to produce the dual-slope
characteristic. Consider block diagram below;-
Now consider the illustration of dual slope conversion below step by step; -

At start we assume that the counter is reset and the output of the integrator is zero. Again assume
that a positive input voltage is applied to the input through the switch (SW) as selected by the control
logic.

So, the inverting input of A1 is at virtual ground, we assume that Vin is constant for a period of time,
there will be constant current through the input resistor R and therefore through the capacitor C.
Capacitor C will charge linearly because the current is constant, and as a result, there will be a negative-
going linear voltage ramp on the output of A1, consider Figure 12–16(a) below; -

When the counter reaches a specified count (n), it will be reset (R), and the control logic will switch the
negative reference voltage (-VREF) to the input of A1 , as shown in Figure 12–16(b).
At this point the capacitor is charged to a negative voltage (-V) proportional to the input analog voltage.
Now the capacitor discharges linearly because of the constant current from the -VREF, as shown in
Figure 12–16(c)

This linear discharge produces a positive-going ramp on the A1 output, starting at -V and having a
constant slope that is independent of the charge voltage. As the capacitor discharges, the counter
advances from its RESET state. The time it takes the capacitor to discharge to zero depends on the initial
voltage -V (proportional to Vin) because the discharge rate (slope) is constant.

When the integrator (A1 ) output voltage reaches zero, the comparator (A2 ) switches to the LOW
state and disables the clock to the counter. The binary count is latched, thus completing one conversion
cycle. The binary count is proportional to Vin because the time it takes the capacitor to discharge
depends only on -V, and the counter records this interval of time.

Successive-Approximation Analog-to-Digital Converter

This is one of the most widely used methods of analog-to-digital conversion .

 It has a much faster conversion time than the dual-slope conversion, but it is slower than the flash
method. It also has a fixed conversion time that is the same for any value of the analog input. Figure 12–
17 shows a basic block diagram of a 4-bit successive approximation ADC.

It consists of a DAC, a successive-approximation register (SAR), and a comparator. The basic operation
is as follows: The input bits of the DAC are enabled (made equal to a 1) one at a time, starting with the
most significant bit (MSB).

As each bit is enabled, the comparator produces an output that indicates whether the input signal
voltage is greater or less than the output of the DAC. If the DAC output is greater than the input signal,
the comparator’s output is LOW, causing the bit in the register to reset.

If the output is less than the input signal, the 1 bit is retained in the register. The system does this with
the MSB first, then the next most significant bit, then the next, and so on. After all the bits of the DAC
have been tried, the conversion cycle is complete

In order to better understand the operation of the successive-approximation ADC, let’s take a specific
example of a 4-bit conversion. Figure 12–18 illustrates the step-by-step conversion of a constant input
voltage (5.1 V in this case).

Let’s assume that the DAC has the following output characteristics:

Vout = 8 V for the 2 power 3 bit (MSB),

Vout = 4 V for the 2 power 2 bit,

Vout = 2 V for the 2 power 1 bit, and

Vout = 1 V for the 2 power 0 bit (LSB).

Figure 12–18(a); - Shows the first step in the conversion cycle with the MSB = 1. The output of the DAC
is 8 V. Since this is greater than the input of 5.1 V, the output of the comparator is LOW, causing the
MSB in the SAR to be reset to a 0.

Figure 12–18(b); - Shows the second step in the conversion cycle with the 2 power 2 bit equal to a 1. The
output of the DAC is 4 V. Since this is less than the input of 5.1 V, the output of the comparator switches
to a HIGH, causing this bit to be retained in the SAR.

Figure 12–18(c); - Shows the third step in the conversion cycle with the 2 power 1 bit equal to a 1. The
output of the DAC is 6 V because there is a 1 on the 2 power 2 bit input and on the 21 bit input; 4 V + 2 V
= 6 V. Since this is greater than the input of 5.1 V, the output of the comparator switches to a LOW,
causing this bit to be reset to a 0.

Figure 12–18(d); - Shows the fourth and final step in the conversion cycle with the 20 bit equal to a 1.
The output of the DAC is 5 V because there is a 1 on the 2 power 2 bit input and on the 2 power 0 bit
input; 4 V + 1 V = 5 V. The four bits have all been tried, thus completing the conversion cycle.

At this point the binary code in the register is 0101, which is approximately the binary value of the
input of 5.1 V. Additional bits will produce an even more accurate result. Another conversion cycle now
begins, and the basic process is repeated. The SAR is cleared at the beginning of each cycle.

Sigma-Delta Analog-to-Digital Converter

Sigma-delta is a widely used method of analog-to-digital conversion, particularly in telecom-

munications using audio signals.
 The method is based on delta modulation where the difference between two successive samples
(increase or decrease) is quantized; other ADC methods were based on the absolute value of a sample.
Delta modulation is a 1-bit quantization method.

The output of a delta modulator is a single-bit data stream where the relative number of 1s and 0s
indicates the level or amplitude of the input signal. The number of 1s over a given number of clock
cycles establishes the signal amplitude during that interval. A maximum number of 1s corresponds to
the maximum positive input voltage. A number of 1s equal to one-half the maximum corresponds to an
input voltage of zero. No 1s (all 0s) corresponds to the maximum negative input voltage.

This is illustrated in a simplified way in Figure 12–20. For example, assume that 4096 1s occur during
the interval when the input signal is a positive maximum. Since zero is the midpoint of the dynamic
range of the input signal, 2048 1s occur during the interval when the input signal is zero. There are no 1s
during the interval when the input signal is a negative maximum.

For signal levels in between, the number of 1s is proportional to the level.

The Sigma-Delta ADC Functional Block Diagram

The basic block diagram in Figure 12–21 accomplishes the conversion illustrated in Figure 12–20. The
analog input signal and the analog signal from the converted quantized bit stream from the DAC in the
feedback loop are applied to the summation point.

The difference signal out of the summation is integrated, and the 1-bit ADC increases or decreases the
number of 1s depending on the difference signal.

This action attempts to keep the quantized signal that is fed back equal to the incoming analog signal.
The 1-bit quantizer is essentially a comparator followed by a latch.
 To complete the sigma-delta conversion process using one particular approach, the single bit data
stream is converted to a series of binary codes, as shown in Figure 12–22. The counter counts the 1s in
the quantized data stream for successive intervals.

The code in the counter then represents the amplitude of the analog input signal for each interval.
These codes are shifted out into the latch for temporary storage. What comes out of the latch is a series
of n-bit codes, which completely represent the analog signal.

during conversion of ADC errors can be generated, now let’s see how; -

Analog-to-Digital Conversion Errors

we use a 4-bit conversion to illustrate the principles. Let’s assume that the test input is an ideal linear
ramp.

 Missing Code

The stairstep output in Figure 12–24(a) indicates that the binary code 1001 does not appear on the
output of the ADC.

Notice that the 1000 value stays for two intervals and then the output jumps to the 1010 value. In a
flash ADC, for example, a failure of one of the op-amp comparators can cause a missing-code error.
  Incorrect Code

The stairstep output in Figure 12–24(b) indicates that several of the binary code words coming out of
the ADC are incorrect. Analysis indicates that the 21 -bit line is stuck in the LOW (0) state in this
particular case.

 Offset

Offset conditions are shown in 12–24(c). In this situation the ADC interprets the analog input voltage as
greater than its actual value

THANK YOU FOR LISTENING