LDO Regulator, 100 mA,

18V, 1 mA IQ, with PG

NCV8711
The NCV8711 device is based on unique combination of features −
very low quiescent current, fast transient response and high input and
output voltage ranges. The NCV8711 is CMOS LDO regulator
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designed for up to 18 V input voltage and 100 mA output current.
Quiescent current of only 1 mA makes this device ideal solution for
battery− powered, always−on systems. Several fixed output voltage
versions are available as well as the adjustable version. MARKING DIAGRAMS
The device (version B) implements power good circuit (PG) which 5
indicates that output voltage is in regulation. This signal could be used TSOP−5
CASE 483 XXXAYWG
for power sequencing or as a microcontroller reset. 5
SN SUFFIX G
1
Internal short circuit and over temperature protections saves the
1
device against overload conditions.
XXX = Specific Device Code
Features A = Assembly Location
Y = Year
• Operating Input Voltage Range: 2.7 V to 18 V W = Work Week
• Output Voltage: 1.2 V to 17 V G = Pb−Free Package
• Capable of Sourcing 140 mA Peak Output Current (Note: Microdot may be in either location)
• Very Low Quiescent Current: 1 mA typ.
• Low Dropout: 215 mV typ. at 100 mA WDFNW6 (2x2) 1
CASE 511DW XX M
• Output Voltage Accuracy ±1% MTW SUFFIX
• Power Good Output (Version B)
XX = Specific Device Code
• Stable with Small 1 mF Ceramic Capacitors M = Date Code
• Built−in Soft Start Circuit to Suppress Inrush Current
• Over−Current and Thermal Shutdown Protections
• Available in Small TSOP−5 and WDFNW6 (2x2) Packages PIN ASSIGNMENTS
TSOP−5
• These Devices are Pb−Free and are RoHS Compliant
IN 1 5 OUT
Typical Applications
GND 2
• Body Control Modules
EN 4 NC/ADJ/PG
• LED Lighting 3

• On Board Charger CASE 483

• General Purpose Automotive WDFNW6 (2x2)

OUT 1 6 IN
NC/ADJ 2 EP 5 NC/PG
GND 3 4 EN

CASE511DW
(Top Views)

ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.

© Semiconductor Components Industries, LLC, 2020 1 Publication Order Number:

September, 2020 − Rev. 2 NCV8711/D
 NCV8711

TYPICAL APPLICATION SCHEMATICS

VIN=6−18V VOUT=5.0V VIN=6−18V VOUT=5V

IN OUT IN OUT
C IN COUT C IN NCV8711A ADJ C OUT
NCV8711A 5.0V R1 C FF 1mF
1mF 1mF 1mF 2M4
TSOP−5 / WDFN−6 ON TSOP−5 / WDFN−6 1nF
ON
1.2V
EN NC EN GND ADJ
GND
OFF OFF R2
750k

Figure 1. Fixed Output Voltage Application (No PG) Figure 2. Adjustable Output Voltage Application (No PG)

VIN=6−18V VOUT=5.0V VIN=6−18V VOUT=5V

IN OUT IN OUT
C IN COUT C IN COUT
1mF NCV8711B 5.0V 1mF NCV8711B ADJ R1 C FF 1mF
R PG 1mF 2M4 1nF
TSOP−5 / WDFN−6 Only WDFN−6
100k 1.2V
NC ADJ R PG
ON ON
100k
EN GND PG PG EN GND PG R2
750k
OFF OFF

PG

Figure 3. Fixed Output Voltage Application with PG Figure 4. Adjustable Output Voltage Application with PG

V OUT + V ADJ @ 1 ) ǒ R1
R2
Ǔ) I ADJ @ R 1

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2
 NCV8711

SIMPLIFIED BLOCK DIAGRAMS

IN OUT
UVLO Comparator

Current limit
UVLO

1.95 V

I EN−PU = 300nA
V CCEN V REF
1.2V
V−REFERENCE
AND SOFT−START EA
RADJ1

V FB =1.2V
EN ADJ
Enable

EN Comparator RADJ2

THERMAL GND
0.9 V
SHUTDOWN

PG Comparator PG

DEGLITCH
NC
DELAY TMR
93% of V REF

Note: Blue objects are valid for ADJ version

Green objects are valid for FIX version
Brown objects are valid for B version (with PG)
Figure 5. Internal Block Diagram

PIN DESCRIPTION
Pin No. TSOP−5 Pin No. WDFNW6 Pin Name Description
1 6 IN Power supply input pin.
2 3 GND Ground pin.
5 1 OUT LDO output pin.
3 4 EN Enable input pin (high − enabled, low − disabled). If this pin is connected to IN pin
or if it is left unconnected (pull−up resistor is not required) the device is enabled.

4 (Note 1) 2 ADJ Adjust input pin. Connect it to the output resistor divider or directly to the OUT pin.
4 (Note 1) 5 PG Power good output pin. Could be left unconnected or could be connected to GND
if not needed. High level for power ok, low level for fail.

4 (Note 1) 2, 5 NC Not internally connected. This pin can be tied to the ground plane to improve
thermal dissipation.

NA EP EPAD Connect the exposed pad to GND.

1. Pin function depends on device version.

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 NCV8711

MAXIMUM RATINGS
Rating Symbol Value Unit

VIN Voltage (Note 2) VIN −0.3 to 22 V

VOUT Voltage VOUT −0.3 to [(VIN + 0.3) or 22 V; whichever is lower] V

EN Voltage VEN −0.3 to (VIN + 0.3) V

ADJ Voltage VFB/ADJ −0.3 to 5.5 V

PG Voltage VPG −0.3 to (VIN + 0.3) V

Output Current IOUT Internally limited mA

PG Current IPG 3 mA

Maximum Junction Temperature TJ(MAX) 150 °C

Storage Temperature TSTG −55 to 150 °C

ESD Capability, Human Body Model (Note 3) ESDHBM 2000 V

ESD Capability, Charged Device Model (Note 3) ESDCDM 1000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001, EIA/JESD22−A114 (AEC−Q100−002)
ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS−002, EIA/JESD22−C101 (AEC−Q100−011D)

THERMAL CHARACTERISTICS (Note 4)

Characteristic Symbol WDFNW6 2x2 TSOP−5 Unit
Thermal Resistance, Junction−to−Air RthJA 63 147 °C/W
Thermal Resistance, Junction−to−Case (top) RthJCt 204 82 °C/W
Thermal Resistance, Junction−to−Case (bottom) RthJCb 15 N/A °C/W
Thermal Resistance, Junction−to−Board (top) RthJBt 47 113 °C/W
Thermal Characterization Parameter, Junction−to−Case (top) PsiJCt 4 22 °C/W
Thermal Characterization Parameter, Junction−to−Board [FEM] PsiJB 46 113 °C/W
4. Measured according to JEDEC board specification (board 1S2P, Cu layer thickness 1 oz, Cu area 650 mm2, no airflow). Detailed description
of the board can be found in JESD51−7.

ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6)
Parameter Test Conditions Symbol Min Typ Max Unit
Recommended Input Voltage VIN 2.7 − 18 V
Output Voltage Accuracy TJ = −40°C to +85°C VOUT −1 − 1 %
TJ = −40°C to +125°C −1 − 2
ADJ Reference Voltage ADJ version only VADJ − 1.2 − V
ADJ Input Current VADJ = 1.2 V IADJ −0.1 0.01 0.1 mA
Line Regulation VIN = VOUT−NOM + 1 V to 18 V and VIN ≥ 2.7 V DVO(DVI) − − 0.2 %VOUT
Load Regulation IOUT = 0.1 mA to 100 mA DVO(DIO) − − 0.4 %VOUT
Quiescent Current (version A) VIN = VOUT−NOM + 1 V to 18 V, IOUT = 0 mA IQ − 1.3 2.5 mA
Quiescent Current (version B) VIN = VOUT−NOM + 1 V to 18 V, IOUT = 0 mA − 1.8 3.0
Ground Current IOUT = 100 mA IGND − 325 450 mA
Shutdown Current (Note 10) VEN = 0 V, IOUT = 0 mA, VIN = 18 V ISHDN − 0.35 1.5 mA
Output Current Limit VOUT = VOUT−NOM − 100 mV IOLIM 140 250 450 mA
Short Circuit Current VOUT = 0 V IOSC 140 250 450 mA
Dropout Voltage (Note 7) IOUT = 100 mA VDO − 215 355 mV

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 NCV8711

ELECTRICAL CHARACTERISTICS (VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF
(effective capacitance – Note 5), TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified) (Note 6) (continued)
Parameter Test Conditions Symbol Min Typ Max Unit
Power Supply Ripple Rejection VIN = VOUT−NOM + 2 V 10 Hz PSRR − 80 − dB
IOUT = 10 mA
10 kHz − 70 −
100 kHz − 42 −
1 MHz − 48 −
Output Noise f = 10 Hz to 100 kHz, VOUT−NOM = 5.0 V VN − 240 − mVRMS
EN Threshold VEN rising VEN−TH 0.7 0.9 1.05 V
EN Hysteresis VEN falling VEN−HY 0.01 0.1 0.2 V
EN Internal Pull−up Current VEN = 1 V, VIN = 5.5 V IEN−PU 0.01 0.3 1 mA
EN Input Leakage Current VEN = 18 V, VIN = 18 V IEN−LK −1 0.05 1 mA
Start−up time (Note 8) VOUT−NOM ≤ 3.3 V tSTART 100 250 500 ms
VOUT−NOM > 3.3 V 300 600 1000
Internal UVLO Threshold Ramp VIN up until output is turned on VIUL−TH 1.6 1.95 2.6 V
Internal UVLO Hysteresis Ramp VIN down until output is turned off VIUL−HY 0.05 0.2 0.3 V
PG Threshold (Note 9) VOUT falling VPG−TH 90 93 96 %
PG Hysteresis (Note 9) VOUT rising VPG−HY 0.1 2 4 %
PG Deglitch Time (Note 9) tPG−DG 75 160 270 ms
PG Delay Time (Note 9) tPG−DLY 120 320 600 ms
PG Output Low Level Voltage (Note 9) IPG = 1 mA VPG−OL − 0.2 0.4 V
PG Output Leakage Current (Note 9) VPG = 18 V IPG−LK − 0.01 1 mA
Thermal Shutdown Temperature Temperature rising from TJ = +25°C TSD − 165 − °C
Thermal Shutdown Hysteresis Temperature falling from TSD TSDH − 20 − °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more
information.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
7. Dropout measured when the output voltage falls 100 mV below the nominal output voltage. Limits are valid for all voltage versions.
8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of VOUT−NOM.
9. Applicable only to version B (device option with power good output). PG threshold and PG hysteresis are expressed in percentage of nominal
output voltage.
10. Shutdown current includes EN Internal Pull−up Current.

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 NCV8711

TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified

2.0%
VIN = (VOUT-NOM+ 1 V) to 18 V, VIN ≥ 2.7 V High limit 2.5
IOUT = 1 to 100 mA High limit
1.5% 2.3

QUIESCENT CURRENT, IQ (mA)

Version-B
(V)

1.0% 2.1 (with PG)

OUT

VOUT-NOM= 15 V VOUT-NOM= 5 V
1.9
OUTPUT VOLTAGE, V

0.5%
1.7
0.0%
VOUT-NOM= 1.2 V 1.5 Version-A
-0.5% (non PG)
Low limit 1.3
-1.0%
1.1
-1.5% VIN = 18 V
0.9
IOUT= 0 mA
-2.0% 0.7
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE, TJ ( °C) JUNCTION TEMPERATURE, TJ ( °C)
Figure 6. Output Voltage vs. Temperature Figure 7. Quiescent Current vs. Temperature

1.6 1.10

1.4 High limit ENABLE THRESHOLD VOLTAGE, VEN -TH (V) 1.05
High limit
Note: 1.00
SHUTDOWN CURRENT, I SHDN ( μA)

1.2
Shutdown current is measured at IN pin 0.95
and includes EN pin pull-up current.
1.0
0.90

0.8 0.85

0.6 0.80

0.75
0.4 Low limit
0.70
0.2 VIN = 18 V
0.65
VEN = 0 V
0.0 0.60
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE, T J ( °C) JUNCTION TEMPERATURE, TJ (°C)

Figure 8. Shutdown Current vs. Temperature Figure 9. Enable Threshold Voltage vs.
Temperature
1.6

0.10
1.4 High limit
ENABLE PULL - UP CURRENT, I EN-PU ( μA)

1.2
0.08
ADJ INPUT CURRENT, I ADJ (μA)

High limit
1.0
0.06
0.8

0.6 0.04

0.4
0.02
0.2
VEN = 1 V
0.0 0.00
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 10. Enable Internal Pull−Up Current vs. Figure 11. ADJ Input Current vs. Temperature
Temperature

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 NCV8711

TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified

400
High limit
350
VOUT = VOUT-NOM - 100 mV

DROPOUT VOLTAGE, V DROP (mV)

300 IOUT = 100 mA
All output voltage versions
250

200

150

100

50

0
-40 -20 0 20 40 60 80 100 120

JUNCTION TEMPERATURE, TJ ( °C)

Figure 12. Dropout Voltage vs. Temperature

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 NCV8711

TYPICAL CHARACTERISTICS
VIN = VOUT−NOM + 1 V and VIN ≥ 2.7 V, VEN = 1.2 V, IOUT = 1 mA, COUT = 1.0 mF, ADJ tied to OUT, TJ = 25°C, unless otherwise specified

Figure 13. PSRR − FIX−3.3 V, COUT = 1 mF, Figure 14. PSRR − FIX−3.3 V, VIN = 4.3 V, IOUT =
IOUT = 100 mA 100 mA

Figure 15. PSRR − FIX−3.3 V, VIN = 8.3 V, IOUT = Figure 16. Noise – FIX − 5.0 V, IOUT = 10 mA,
100 mA Different COUT

Figure 17. Noise – ADJ−set−5.0 V with Figure 18. Noise – FIX, IOUT = 10 mA,
Different CFF and FIX − 5.0 V COUT = 1 mF, Different VOUT

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 NCV8711

ORDERING INFORMATION
Part Number Marking Voltage Option (VOUT−NOM) Version Package Shipping
NCV8711ASNADJT1G GGA ADJ
NCV8711ASN300T1G GGC 3.0 V TSOP−5
Without PG 3000 / Tape & Reel
NCV8711ASN330T1G GGD 3.3 V (Pb−Free)

NCV8711ASN500T1G GGE 5.0 V

NCV8711BMTWADJTBG GA ADJ
NCV8711BMTW300TBG GC 3.0 V WDFNW6
With PG 3000 / Tape & Reel
NCV8711BMTW330TBG GD 3.3 V (Pb−Free)

NCV8711BMTW500TBG GE 5.0 V

NOTE: To order other package, voltage version or PG / non PG variant, please contact your ON Semiconductor sales representative.

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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSOP−5
CASE 483
5 ISSUE N
1 DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5 D 5X Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X 0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4 FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X 0.20 T S
B FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3 EXCEED 0.15 PER SIDE. DIMENSION A.
K 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
B TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
A A
MILLIMETERS
TOP VIEW DIM MIN MAX
A 2.85 3.15
B 1.35 1.65
DETAIL Z C 0.90 1.10
J D 0.25 0.50
G 0.95 BSC
C H 0.01 0.10
0.05 J 0.10 0.26
H SEATING K 0.20 0.60
C PLANE
END VIEW M 0_ 10 _
SIDE VIEW S 2.50 3.00

GENERIC
SOLDERING FOOTPRINT*
MARKING DIAGRAM*
1.9
0.074 5 5
0.95
0.037 XXXAYWG XXX MG
G G
1 1
Analog Discrete/Logic

2.4 XXX = Specific Device Code XXX = Specific Device Code

0.094 A = Assembly Location M = Date Code
Y = Year G = Pb−Free Package
1.0 W = Work Week
0.039 G = Pb−Free Package
(Note: Microdot may be in either location)
0.7 *This information is generic. Please refer to
0.028 SCALE 10:1 ǒinches
mm Ǔ
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
*For additional information on our Pb−Free strategy and soldering may or may not be present.
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ARB18753C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−5 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

WDFNW6 2x2, 0.65P

CASE 511DW
ISSUE B
DATE 15 JUN 2018
SCALE 4:1

GENERIC
MARKING DIAGRAM*

XXMG
G

M = Month Code
G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON79327G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: WDFNW6 2x2, 0.65P PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2018 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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