US010158044B2

(12) United States Patent (10) Patent No.: US 10 , 158,044 B2

Jain et al. (45 ) Date of Patent: * Dec . 18 , 2018
(54 ) EPITAXY TECHNIQUE FOR GROWING
SEMICONDUCTOR COMPOUNDS
(58) CPC
Field ..of....Classification Search
.. HOIL 33 /0062 – 33/0079 ; HOIL 33/0025 ;
(71 ) Applicant: Sensor Electronic Technology, Inc., HO1L 33/002 ; HO1L 33 /30 – 33 /325 ;
Columbia , SC (US) (Continued )

(56 ) References Cited

Wenhong Sun , Lexington , SC (US) ;
Jinwei Yang , Columbia , SC (US ); U . S . PATENT DOCUMENTS
Maxim S . Shatalov , Columbia , SC 5 ,306 ,924 A 4 / 1994 Usami et al.
(US); Alexander Dobrinsky ,
Loudonville , NY (US); Remigijus 5 ,880 ,491 A * 3/ 1999 Soref .................... B82Y 20 /00
Gaska, Columbia , SC (US ); Michael 257/ 18
Shur , Latham , NY (US ) (Continued )
( 73 ) Assignee : Sensor Electronic Technology, Inc., FOREIGN PATENT DOCUMENTS
Columbia, SC (US) CN 101277563 A 10 /2008
( * ) Notice : JP 2010153450 8 /2010
KR 100363241 2 / 2003
patent is extended or adjusted under 35 KR 1020100033644 3 / 2010
U .S . C . 154(b ) by 0 days. KR 1020100100567 9 / 2010

claimer . OTHER PUBLICATIONS

Allen , E ., U .S . Appl. No. 13 /756 ,806 , Final Office Action 2 , dated
(21) Appl. No.: 15 /391,922 Jan . 4 , 2017 , 25 pages .
( 22 ) Filed : Dec . 28 , 2016 (Continued )
(65) Prior Publication Data Primary Examiner — Kevin M Picardat
US 2017/0104132 A1 Apr. 13, 2017 (74 ) Attorney , Agent, or Firm — LaBatt, LLC
Related U . S . Application Data
(63) Continuation - in -part of application No. 13/692,191, (57) ABSTRACT
filed on Dec . 3, 2012 , now Pat. No . 9 ,831,382 . A solution for fabricating a semiconductor structure is
( Continued ) provided . The semiconductor structure includes a plurality
of semiconductor layers grown over a substrate using a set
(51) Int . Cl. of epitaxial growth periods. During each epitaxial growth
HOIL 31 /072 ( 2012 .01) period , a first semiconductor layer having one of: a tensile
HO1L 33 /32 ( 2010 .01) stress or a compressive stress is grown followed by growth
(Continued ) of a second semiconductor layer having the other of: the
(52 ) U .S. CI. tensile stress or the compressive stress directly on the first
CPC .......... HOIL 33 /32 (2013 .01); HOIL 21/0237 semiconductor layer.
( 2013 .01 ); HOIL 21 /0254 ( 2013 .01 );
(Continued ) 20 Claims, 15 Drawing Sheets

40B Compressive Layer 18B

Tensile Layer 20B
O pony powy 42B
Compressive Layer 18A
A42A
Tensile Layer 20A
 Kwon et al., “ Multiscale Modeling and Simulation of Composite
Bai et al., Reduction of threading dislocation densities in AIN,
sapphire epilayers driven by growth mole modification , Applied

pulse- flow method on Sapphire, Applied Physics Letters, 2007 , pp .

Hsu et al., Growth and characteristics of self- assembly defect-free

Mathis, et al., “ Modeling of threading dislocation reduction in

Mitrofanov et al ., High quality UV AlGaN/ AlGaN distributed

Ohba et al., Growth of AIN on sapphire substrates by using a thin

Ponchet et al., Lateral modulations in zeronetstrained GalnAsP

Sang et al., Reduction in threading dislocation densities in AIN

Acord et al., In situ Stress measurements during MOCVD growth of

 US 10 ,Page
158,3044 B2

( 56 ) References Cited Allen , E ., U . S . Appl. No . 13 /756 ,806 , Non -Final Office Action 2 ,
dated May 5 , 2016 , 23 pages.
OTHER PUBLICATIONS Allen , E ., U .S . Appl. No. 13 /756 ,806 , Final Office Action 1, dated
Sep . 1 , 2015 , 38 pages.
Zhang et al., Crack - free thick AlGaN grown on sapphire using Allen , E ., U .S . Appl. No. 13/ 756 , 806 , Non -Final Office Action 1,
AIN / AIGaN superlattices for strain management, Applied Physics dated Dec . 9 , 2014 , 28 pages.
Letters , May 2002 , pp . 3542 - 3544 , vol. 80 No. 19 , American Jinzhu , C ., Application No. 201380013532 .2 , Office Action
Institute of Physics . English translation , dated Apr. 7 , 2016 , 12 pages .
Zhang et al., Growth of Highly Conductive n - Type AIO :76a0 : 3N Choi, International Application No . PCT/US2012 /067590 , Search
Film by Using AIN Buffer with Periodical Variation of V /III Ratio , Report and Written Opinion, dated Mar. 26 , 2013 , 11 pages.
Chinese Phys. Lett., 2008 , pp . 4449 - 4452 , vol. 25 No. 12 , Chinese Choi, International Application No . PCT/US2013 /024310 , Search
Physical Society and IOP Publishing Ltd . [ 18 ]. Report and Written Opinion , dated May 15 , 2013 , 9 pages.
Zhang et al., Improvement of AIN Film Quality by Controlling the Webb, V., U . S . Appl. No. 13 /692 ,191, Notice of Allowance, dated
Coalescence of Nucleation Islands in Plasma- Assisted Molecular Aug. 1, 2017 , 22 pages .
Beam Epitaxy , Chinese Phys. Lett., 2010 , pp . 058101- 1-058101 -3 , Jinzhu , C ., Application No . 201380013532 .2 , Rejection Decision
vol. 27 No. 5 , Chinese Physical Society and IOP Publishing Ltd . (with English translation ), dated Apr. 13 , 2017 , 10 pages .
(Chen ). Jinzhu , C ., Application No. 201380013532.2 , Notification of Reex
Zhang et al., Pulsed atomic layer epitaxy of quaternary AlInGaN amination , Board Opinion (with English translation ), dated Jan . 24 ,
layers , Applied Physics Letters , Aug. 2001 , pp . 925 - 927, vol. 79 No . 2018, 12 pages .
7 , American Institute of Physics Allen III, E ., U .S . Appl. No. 13 /756 ,806 , Interview Summary, dated
Webb , V ., U . S . Appl. No. 13/692 , 191 , Final Office Action 2 , dated May 18 , 2018 , 4 pages .
May 19 , 2016 , 21 pages . Nadav, O ., U .S . Appl. No . 13 / 756 ,806 , Ex Parte Quayle Action , Sep .
Webb , V., U .S . Appl. No . 13/692, 191, Non - Final Office Action 2 , 6 , 2018 , 4 pages .
dated Sep . 9 , 2015 , 29 pages. Picardat. K ., U . S. Appl.No. 16 /021,347, Office Action 1 , dated Oct.
Webb , V ., U . S . Appl. No. 13/692 , 191, Final Office Action 1 , dated 4 , 2018 , 5 pages.
Jan . 23 , 2015, 17 pages. Nadav, O ., U .S . Appl. No. 13 /756 ,806 , dated Oct. 11, 2018 , 5 pages .
Webb , V ., U . S . Appl. No. 13 /692, 191, Non - Final Office Action 1,
dated Jun. 20 , 2014 , 18 pages . * cited by examiner
 atent Dec . 18 , 2018 Sheet 1 of 15 US 10 ,158 ,044 B2

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 atent Dec . 18 , 2018 Sheet 8 of 15 US 10 ,158 ,044 B2

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U . S . Patent Dec . 18, 2018 Sheet 10 of 15 US 10 , 158,044 B2

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U . S . Patent Dec . 18, 2018 Sheet 11 of 15 US 10 , 158 ,044 B2

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U . S . Patent Dec . 18, 2018 Sheet 15 of 15 US 10 ,158 ,044 B2

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 US 10 , 158 ,044 B2
EPITAXY TECHNIQUE FOR GROWING While the superlattice approaches allow some control of
SEMICONDUCTOR COMPOUNDS tensile and compressive stresses in epitaxially grown nitride
semiconductor layers , the approaches do not enable epitaxial
REFERENCE TO RELATED APPLICATIONS growth of nitride based semiconductor layers with uniform
5 composition . To grow such layers , variation of nitrogen and
The current application is a continuation -in -part of U .S . aluminum vacancies has been explored . For example, FIGS.
application Ser. No. 13/692 ,191, which was filed on 3 Dec . multilayer
1B and 1Cbuffers
illustrate one approach for fabricating AIN
according to the prior art. In particular ,
2012 , which claims the benefit of U .S . Provisional Appli
cation No . 61/ 566 ,606 , which was filed on 3 Dec . 2011 , both FIG . 1B shows the gas flow sequence used for NHz pulse
of which are hereby incorporated by reference . 10 flow growth , while FIG . 1C shows a schematic structure of
the AIN buffer. In a first step , an AlN nucleation layer and
GOVERNMENT LICENSE RIGHTS an initial AlN layer are deposited using NH pulse -flow
growth . A low threading dislocation density was achieved by
This invention was made with government support under a coalescence process of the AlN nucleation layer. For
contract no . W911NF - 10 -2 -0023 awarded by the Defense 15 example , as observed from a cross -sectional transmission
Advanced Research Projects Agency (DARPA ). The gov electron microscope ( TEM ) image , edge -type and screw
ernment has certain rights in the invention . type dislocation densities of an AlGaN layer on an AIN
buffer layer were reported as 3 .2x109 and 3.5x108 cm -?,
TECHNICAL FIELD respectively .
20
The disclosure relates generally to growing semiconduc SUMMARY OF THE INVENTION
tor compounds, and more particularly, to an epitaxy tech
nique for such growth , which can result in a low stress Aspects of the invention provide a solution for fabricating
compound . a semiconductor structure . The semiconductor structure
25 includes a plurality of semiconductor layers grown over a
BACKGROUND ART substrate using a set of epitaxial growth periods . During
each epitaxial growth period , a first semiconductor layer
For light emitting devices , such as light emitting diodes having one of: a tensile stress or a compressive stress is
(LEDs) and especially deep ultraviolet LEDs (DUV LEDs), grown followed by growth of a second semiconductor layer
minimizing a dislocation density and a number of cracks in 30 having the other of: the tensile stress or the compressive
the semiconductor layers increases the efficiency of the stress directly on the first semiconductor layer. In this
device . To this extent, several approaches have sought to manner, the overall residual stress for the plurality of semi
grow low -defect semiconductor layers on patterned sub - conductor layers can be approximately zero , which can
strates . These approaches typically rely on reducing stresses result in the semiconductor structure having a reduced
present in epitaxially grown semiconductor layers . 35 number of cracks and / or threading dislocations than prior art
For example , one approach to reduce stress accumulation approaches .
in an epitaxially grown layer relies on patterning the under - A first aspect of the invention provides a method of
lying substrate using microchannel epitaxy MCE
( ). Using fabricating a semiconductor structure , the method compris
MCE , a narrow channel is used as a nucleation center ing: growing a plurality of semiconductor layers over a
containing low defect information from the substrate . An 40 substrate using a set of epitaxial growth periods, wherein
opening in a mask acts as a microchannel, which transfers each epitaxial growth period includes : epitaxially growing a
crystal information to the overgrown layer, while the mask first semiconductor layer having one of: a tensile stress or a
prevents dislocations from transferring to the overgrown compressive stress ; and epitaxially growing a second semi
layer. As a result, the overgrown layer can become disloca conductor layer having the other of: the tensile stress or the
tion free . The three -dimensional structure of the MCE also 45 compressive stress directly on the first semiconductor layer.
provides another advantage to stress release . The residual A second aspect of the invention provides a semiconduc
stress can be released effectively since the overgrown layer tor structure including: a substrate ; and a plurality of semi
easily deforms. In another approach , a mask is applied at a conductor layers on the substrate , the plurality of semicon
location of a large concentration of dislocation densities to ductor layers including a set of periods, each period
block their further propagation . 50 including : a first semiconductor layer, wherein the first
Other approaches rely on epitaxially growing a group III semiconductor layer has one of: a tensile stress or a com
nitride based semiconductor superlattice . The superlattice pressive stress, and a second semiconductor layer directly on
structure mitigates the strain difference between an alumi- the first semiconductor layer , wherein the second semicon
num nitride (AIN )/ sapphire template and the subsequent ductor layer has the other of: the tensile stress or the
thick Al,Ga - N (where 0 <xsl) layers . For devices such as 55 compressive stress .
DUV LEDs, thick AlGaN epitaxial layers (e .g., of the order A third aspect of the invention provides a method of
of a few micrometers ) are desirable to reduce current crowd- fabricating a semiconductor structure, the method compris
ing . Using a superlattice approach , an AIN / AlGaN superla - ing : growing a plurality of group III nitride semiconductor
ttice was grown to reduce biaxial tensile strain and a 3 .0 -um layers over a substrate using a set of epitaxial growth
thick Al , Ga, N was grown on sapphire without any 60 periods, wherein each epitaxial growth period includes :
cracks . Similarly , a superlattice structure shown in FIG . 1A epitaxially growing a first group III nitride semiconductor
can comprise a periodic structure with each element 2A - 2D layer having one of: a tensile stress or a compressive stress ;
composed of alternating sublayers of semiconductor mate and epitaxially growing a second group III nitride semicon
rials with different polarizations and different accumulated ductor layer having the other of: the tensile stress or the
stresses in the sublayers. Such a superlattice can be used to 65 compressive stress directly on the first semiconductor layer,
minimize the dislocation density due to varying stresses in wherein the epitaxially growing the first semiconductor
the sublayers of the superlattice elements. layer and the epitaxially growing the second semiconductor
 US 10 , 158 ,044 B2
layer use molar ratios of group V precursors to group III the group III -V materials system . In a more particular
precursors that differ by at least ten percent. embodiment, the semiconductor layers are formed of group
The illustrative aspects of the invention are designed to III nitride materials. Group III nitride materials comprise
solve one or more of the problems herein described and/or one or more group III elements ( e. g., boron (B ), aluminum
one or more other problems not discussed . 5 (Al), gallium (Ga), and indium ( In )) and nitrogen (N ) , such
that BwAl ,Ga In , N , where OsW , X , Y , Zs1, and W + X + Y +
BRIEF DESCRIPTION OF THE DRAWINGS Z = 1 . Illustrative group III nitride materials include AIN ,
GaN , InN , BN , ALGAN , AllnN , AIBN , AIGaInN , AlGaBN ,
These and other features of the disclosure will be more AllnBN , and AlGaInBN with any molar fraction of group III
readily understood from the following detailed description 10 elements .
of the various aspects of the invention taken in conjunction The substrate can comprise any type of substrate exhib
with the accompanying drawings that depict various aspects iting a lattice mismatch with the semiconductor layer grown
of the invention . thereon . To this extent, the substrate can have a lattice
FIGS. 1A - 1C show approaches for reducing dislocation constant that is different from a lattice constant correspond
density according to the prior art. 15 ing to one of the semiconductor layers epitaxially grown
FIG . 2 shows illustrative plots of the lattice constants a thereon . As used herein , a substrate is lattice mismatched
and c as a function of the V /III ratio for an AIN layer with a semiconductor layer when the lattice constants differ
according to an embodiment. by more than one percent ( e. g ., as calculated by the lattice
FIG . 3 shows illustrative plots of stress and strain as a constant of the semiconductor layer minus the lattice con
function of the V / III ratio for an AIN layer according to an 20 stant of the substrate divided by the lattice constant of the
embodiment. semiconductor layer ). In an embodiment, the substrate is an
FIGS. 4A -4G show illustrative structures according to insulatingmaterial, such as sapphire or silicon carbide (SIC ).
embodiments . However, the substrate can comprise any suitable material,
FIGS. 5A and 5B show illustrative bright field optical such as silicon ( Si), a nitride substrate (e . g ., AIN , GAN , BN ,
microscope images of layers according to an embodiment. 25 AlGaN , and/ or the like), an oxide substrate ( e. g ., aluminum
FIG . 6 shows an illustrative plot of a ( 102) XRD rocking oxynitride, zinc oxide (Zno ), lithium gallate (LiGao , ),
curve FWHM as a function of layer thickness according to lithium aluminate (LiA10 , ), magnesium aluminate
an embodiment. (MgA1,02), scandium magnesium aluminum oxide (ScM
FIG . 7 shows a possible mechanism for the reduction of gA104 ), and /or the like ), and /or other related materials.
dislocation density provided by a growth procedure 30 The layer (s) grown as described herein can be imple
described herein . mented as part of any type of semiconductor device . In an
FIGS. 8A and 8B show illustrative patterns of a surface of embodiment, the semiconductor device is an emitting
a compressive layer with a tensile layer grown thereon device . In a more particular embodiment, the emitting
according to embodiments. device is configured to operate as a light emitting diode
FIGS. 9A and 9B show illustrative patterning arrange - 35 (LED ), such as a conventional or super luminescent LED .
ments according to embodiments . Similarly , the emitting device can be configured to operate
FIG . 10 shows an illustrative flow diagram for fabricating as a laser , such as a laser diode (LD ). In another embodi
a circuit according to an embodiment. ment, the semiconductor device is configured to operate as
It is noted that the drawings may not be to scale . The a photodetector, photomultiplier, and/ or the like . Regardless ,
drawings are intended to depict only typical aspects of the 40 electromagnetic radiation emitted or detected by the device
invention , and therefore should notbe considered as limiting can comprise a peak wavelength within any range of wave
the scope of the invention. In the drawings , like numbering lengths, including visible light, ultraviolet radiation , deep
represents like elements between the drawings. ultraviolet radiation , infrared light, and/ or the like.
Aspects of the invention utilize an ability to selectively
DETAILED DESCRIPTION OF THE 45 grow a layer exhibiting either tensile or compressive
INVENTION residual stress depending on the deposition conditions . For
example , a change in a set of the deposition conditions for
As indicated above, aspects of the invention provide a growing an aluminum nitride (AIN ) epitaxial layer on a
solution for fabricating a semiconductor structure . The semi- foreign substrate can result in the layer exhibiting either
conductor structure includes a plurality of semiconductor 50 tensile or compressive residual stress . In an embodiment, the
layers grown over a substrate using a set of epitaxial growth set of deposition conditions includes a molar ratio of group
periods . During each epitaxial growth period , a first semi- V precursors to group III precursors (V /III ratio ), which can
conductor layer having one of: a tensile stress or a com - be altered during the growth of a group III - V semiconductor
pressive stress is grown followed by growth of a second layer.
semiconductor layer having the other of: the tensile stress or 55 To this extent, FIG . 2 shows illustrative plots of the lattice
the compressive stress directly on the first semiconductor constants a and c as a function of the V / III ratio for an AIN
layer. In this manner, the overall residual stress for the layer according to an embodiment. Different lattice direc
plurality of semiconductor layers can be approximately zero , tions can result in different tensile and compressive proper
which can result in the semiconductor structure having a ties for the AlN layer. For example , for a low V /III ratio
reduced number of cracks and /or threading dislocations than 60 ( e . g ., less than approximately 1800 ) , the lattice constant a
prior art approaches . As used herein , unless otherwise noted , for the AlN layer is slightly larger than the lattice constant
the term “ set” means one or more (i.e., at least one) and the a for an AIN layer without the presence of point defects ( e.g .,
phrase " any solution ” means any now known or later approximately 3 . 112 ). The difference in the lattice constant
developed solution . a results in tensile stresses being accumulated in the layer .
Aspects of the invention are directed to the growth of 65 For a high V /III ratio (e.g ., greater than approximately
semiconductor layers on a substrate . In an embodiment, the 1800 ), the lattice constant a for the AlN layer is slightly
semiconductor layers are formed of elements selected from smaller than the lattice constant a for an AIN layer without
 US 10 , 158 ,044 B2
the presence of point defects, which results in compressive While each semiconductor heterostructure 16A -16C is
stresses being accumulated in the layer . The V / III ratio also shown including three periods of epitaxial growth (e. g., each
influences the lattice constant c . In this case , small values of period including a compressive and a tensile layer ), it is
the V / III ratio ( e. g., below approximately 750 ) result in a understood that a semiconductor heterostructure can include
below approximately 4 . 982 ) in the layer , while larger values changes abruptly between a compressive layer and the
of the V / III ratio ( e .g ., above approximately 750 ) result in a adjacent tensile layer. Alternatively, the stress can gradually
lattice constant c , which causes tensile stress in the layer. change between adjacent layers ( e. g ., by growing layers
FIG . 3 shows illustrative plots of stress and strain as a having a graded tensile or compressive stress ) . Furthermore ,
function of the V / III ratio for an AIN layer according to an 10 the tensile and compressive stress can be substantially
embodiment. As illustrated , an AIN layer grown under a low constant between periods of the semiconductor heterostruc
V / III ratio ( e . g ., less than approximately 1800 ) is in tensile ture 16A - 16C or can gradually change from period to period .
stress , while an AIN layer grown with a high V / III ratio (e .g ., The growth of a semiconductor heterostructure 16A - 16C ,
above approximately 1800 ) is in compressive stress . As and the growth of the corresponding layers 18A - 18C , 20A
further illustrated , only small changes in the strain of the 15 20C forming the semiconductor heterostructure 16A - 16C ,
AlN layer are produced by modulating the V / III ratio . can use any set of deposition conditions. For example , the
In an embodiment, growth of a semiconductor hetero set of deposition conditions for a layer 18A - 18C , 20A - 20C
structure ( e . g ., a layer ), such as a group III - V based hetero - can include : a group III precursor flow rate between approxi
structure , includes growth of a series of layers ( e. g., films) mately 0 . 1 and approximately 200 micromoles per minute ;
with alternating tensile and compressive stresses. A layer 20 a nitrogen precursor flow rate between approximately 100
can be selectively configured to have tensile or compressive and 10000 standard cubic centimeters per minute (SCCM ) ;
stress by modulating a V / III ratio in each layer. For example , a pressure between approximately 1 and 760 Torr; a molar
the modulation can include varying the V /III ratio according ratio of group V precursors to group III precursors (V / III
to a set schedule to yield compressive and tensile semicon - ratio ) between approximately 10 and approximately 1000 ;
ductor layers. Additionally , one or more additional deposi- 25 and a growth temperature between approximately 500 and
tion conditions can be changed , such as a growth tempera - approximately 1800 degrees Celsius. Furthermore , a layer
ture, a gas flow , and/or the like . Furthermore , one or more 18A - 18C , 20A - 20C can be grown to a thickness that is
attributes of the layers , such as a relative thickness of a layer, greater than a critical thickness to avoid pseudomorphic
a distribution of stress within each layer, and /or the like , can growth . In an embodiment, each layer 18A - 18C , 20A - 20C
be adjusted during the growth of the layer. The modulation 30 has a thickness between approximately one nanometer and
of the set of deposition conditions can result in regions of five micrometers .
increased compressive stresses and regions of increased As described herein , during the growth of a semiconduc
tensile stress . In this manner , the resulting semiconductor tor heterostructure 16A - 16C , one or more of a set of the
structure can be configured to have a condition of approxi deposition conditions for epitaxially growing a layer 18A
mately zero ( or near zero ) overall residual stress . 35 18C , 20A - 20C can be changed to cause the resulting layer
FIGS. 4A - 4C show illustrative structures 10A - 10C 18A - 18C , 20A - 20C to exhibit either tensile or compressive
according to embodiments . Each structure 10A - 10C residual stress . For example , the growth of a compressive
includes a substrate 12 , which can be a foreign substrate , layer and the growth of a tensile layer can use molar ratios
of group V precursors to group III precursors that differ by
tures 10A , 10B include a buffer layer 14 ( e. g ., a nucleation 40 at least ten percent. In an embodiment , a composition of the
layer ) grown directly on the substrate 12 . The buffer layer 14 compressive layer differs from a composition of the tensile
can provide a transition to accommodate a large lattice layer by no more than approximately five percent. For
mismatch between the substrate 12 and the subsequent example , a fraction of aluminum in the tensile layer can
semiconductor heterostructure 16A - 160 . In an embodiment , differ from a fraction of aluminum in the compressive layer
the buffer layer 14 can comprise an Al Ga - N / Al,,GaN 45 by no more than approximately five percent. Similarly , the
superlattice , where 0sx , ys1. Each superlattice layer can be , compressive and tensile layers can have a lattice mismatch
for example , up to several nanometers thick . In an embodi of at least 0 .0001 Angstroms. Furthermore , a growth rate for
ment, the layers with differing aluminum content ( e . g ., the compressive and tensile layers can be changed . In an
denoted by x and y ) can have similar thicknesses . In an embodiment, the growth rates for the compressive and
illustrative embodiment, the buffer layer 14 has a thickness 50 tensile layers differ by at least ten percent. A growth tem
in a range from nearly zero nanometers to approximately perature for the compressive and tensile layers can be
2000 nanometers . In another embodiment, growth of the substantially the same or changed . In an embodiment, the
buffer layer 14 uses a growth temperature between approxi- growth temperatures for the compressive and tensile layers
mately 500 and approximately 1200 degrees Celsius and a differ by at least two percent.
growth rate between approximately 0 .01 micrometers and 55 FIGS. 4D -4G show illustrative structures 10D - 10G
approximately 10 micrometers per hour. However , as illus - according to additional embodiments . Similar to the struc
trated by the structure 10C , embodiments of the structure tures 10A - 10C shown in FIGS . 4A -4C , each structure 10D
can be formed without the buffer layer 14 , e .g ., based on the 10G can include a substrate 12 and a buffer layer 14 .
material of the substrate and /or the corresponding lattice However, it is understood that embodiments of the structures
mismatch . 60 10D - 10G can be fabricated without the buffer layer 14 as
Regardless, each of the structures 10A - 10C includes a described herein . Each structure 10D - 10G also includes a
semiconductor heterostructure 16A - 16C grown on the sub - plurality of compressive layers 18A - 18N alternating with a
strate 12 . Each semiconductor heterostructure 16A - 16C is plurality of tensile layers 20A - 20N , each of which can be
formed of a plurality of compressive layers 18A -18C alter - formed as described herein in conjunction with the struc
nating with a plurality of tensile layers 20A - 20C . In the 65 tures shown in FIGS . 4A - 4C . However, the structures 10D
structures 10A , 10C , a compressive layer 18A is first grown , 10G also include a set of transitional layers located between
while in the structure 10B , a tensile layer 20A is first grown. adjacent compressive and tensile layers to form a plurality of
 US 10 , 158 ,044 B2
periods 11A , 11B (e.g ., a period 11A includes a compressive n ess of the compressive layers 18A -18N and /or the tensile
layer 18A , a transitional layer 19A , and a tensile layer 20A ). layers 20A - 20N can decrease closer to the top portion of the
For example , FIG . 4D shows a transitional layer 19A - 19N structure 10D - 10F ( e.g ., away from the substrate 12 and the
located between a pair of layers (e .g ., each compressive buffer layer 14 ). In another embodiment, the amplitude of
layer 18A - 18N and tensile layer 20A -20N ) . In an embodi- 5 the variation of the V / III ratio can vary throughout the
ment, the transitional layer 19A - 19N can comprise a layer structure 10D - 10F for a larger lattice mismatch between the
with a V / III ratio which results in a lattice constant that tensile layers 20A - 20N and the compressive layers 18A
matches the 0 compressive or tensile strain as shown in FIG . 18N . In another embodiment, the composition can vary
3 . That is, the transitional layer 19A - 19N includes a region throughout the thickness of each layer. Additionally , in any
that has no tensile or compressive stresses . In an embodi- 10 embodiment described herein , either one or both of the
ment, the value of the V / III ratio can be approximately 1500 . plurality of compressive layers 18A - 18N and the plurality of
In an embodiment, the V / III ratio can vary continuously tensile layers 20A - 20N can be laterally discontinuous. In
through the first period 11A , which includes a compressive such embodiments , the layers can have discontinuous
layer 18A , a transitional layer 19A , and a tensile layer 20A , regions with a lateral characteristic dimension between
which is shown in plot 11C . That is , both the compressive 15 approximately 2 nm and approximately 2 um .
and tensile layers 18A , 20A can have a graded / changing Turning now to FIG . 4G , a structure 10G according to an
V / III ratio . In another embodiment, a plot 11D shows the embodiment is shown. The structure 10G can include a first
V / III ratio dependence on a second period 11B (e . g ., a set of composite layers 50A - 50N , each of which is located
compressive layer 18B , a transitional layer 19B , a tensile above a compressive layer 18A - 18N , and a second set of
layer 20B ) . In this embodiment, the V / III ratio can be 20 composite layers 52A -52N , each of which is located above
constant in both the tensile layer 20B and the compressive a tensile layer 20A - 20N . In this embodiment, the sets of
layer 18B and have a smooth rapid change in the transitional composite layers 50A -50N , 52A -52N can comprise the
layer 19B . It is understood that the V /III ratio can be a same composition as the compressive layers 18A - 18N and
continuous function having a generally smooth behavior and the tensile layers 20A - 20N .
broadly classified into a compressive layer 18A , 18B , 18N , 25 However, the composite layers 50A -50N , 52A -52N can
a transitional layer 19A , 19B , 19N , and a tensile layer 20A , also include a set of thin semiconductor interlayers 54 , 55 .
20B , 20N . In an embodiment, the set of interlayers 54 , 55 can have a
In the structure 10E shown in FIG . 4E , in addition to the composition that is different from a remaining portion of the
transitional layer 19A - 19N deposited after each compressive corresponding composite layer 50A - 50N , 52A -52N . For
layer 18A - 18N , another transitional layer 21A - N can be 30 example , the set of interlayers 54 , 55 can have a composition
deposited after each tensile layer 20A - 20N . In an embodi- that includes a higher Gamolar fraction or a higher Almolar
ment, the grading of stresses is achieved by varying the V /III fraction than a remaining portion of the corresponding
ratio continuously, as shown by a curve 25 . The higher composite layer 50A -50N , 52A -52N . In an embodiment, in
values of the V / III ratio correspond to the compressive the composite layer 50A , the interlayers 54 that are closer to
layers 18A - 18N , while the lower values of the V /III ratio 35 a first side 56 adjacent to a compressive layer 18A can
correspond to the tensile layers 20A - 20N , and the values include a composition that has a higher Ga molar fraction
between the higher values and the lower values of the V /III than a remaining portion of the composite layer 50A , while
ratio correspond to the transitional layers 19A - 19N , 21A - the interlayers 54 that are closer to a second side 58 adjacent
21N . In this embodiment, the V / III ratio is a continuous to a tensile layer 20A can include a composition that has a
function throughout each period 13A , 13B , 13C . 40 higher Al molar fraction than a remaining portion of the
Turning now to FIG . 4F , the structure 1 OF is similar to composite layer 50A . In an embodiment, the interlayers 55
the structure 10E shown in FIG . 4E , with two sets of in the composite layer 52A can have similar but reverse
transitional layers 19A - 19N , 21A -21N . However, the V /III structure as to the interlayers 54 in the composite layer 50A .
ratio in the structure 10F can be changed discretely , instead For example, the interlayers 55 closer to a first side 59
of continuously . For example , as shown by the curve 26 , the 45 adjacent to the tensile layer 20A can include a composition
V / III ratio in the compressive and tensile layers 18A - 18N , that has a higher Almolar fraction than a remaining portion
20A - 20N can be constant throughout the thickness of the of the composite layer 52A , while the interlayers 55 closer
layer and the V / III ratio can change linearly throughout the to a second side 57 adjacent to the compressive layer 18B
thickness of the transitional layers 19A - 19N , 21A -21N . In can include a composition that has a higher Ga molar
an embodiment, in addition to changing the V /III ratio , the 50 fraction than a remaining portion of the composite layer
composition of one or more of the layers 18A - 18N , 19A 52A .
19N , 20A - 20N , 21A - 21N can be changed . For example , a It is understood that the molar fractions and the thick
curve 27 shows an illustrative change in the Ga composition nesses of the set of interlayers 54 can be selected to provide
of the layers. a smooth transition between the compressive layers 18A
It is understood that the transitional layers 19A - 19N 55 18N and the tensile layers 20A - 20N . In another embodi
located after each compressive layer 18A - 18N can be dif ment, the set of interlayers 54 can include a V / III ratio that
ferent from the transitional layers 21A -21N located after is different from a V / III ratio of a remaining portion of the
each tensile layer 20A -20N . For example, as illustrated , the corresponding composite layer 50A -50N , 52A - 52N . For
grading direction of the V / III ratio , the composition , or both , example , the interlayers 54 that are located adjacent to the
as shown in the curves 26 , 27 can be different for the 60 first side 56 that is closer to the compressive layer 18A can
transitional layers . In any of the structures 10D - 10F shown, include a V / III ratio that is higher than a remaining portion
it is understood that the structure of any layer does not have of the composite layer 50A , while the interlayers 54 that are
to be periodic and the thickness of any layer can be varied located adjacent to the second side 58 that is closer to the
throughout the structure 10D - 10F . The structure and / or tensile layer 20A can include a V / III ratio that is lower than
thickness can be varied in order to manage stresses within 65 a remaining portion of the composite layer 50A .
the structure 10D - 10F and/or for the reduction of disloca - In any of the structures 10D - 10G shown in FIGS. 4D -4G ,
tions within the structure 10D - 10F . For example , the thick - the transitional layers 19A - 19N , 21A - 21N and the compos
 US 10 , 158 ,044 B2
10
ite layers 50A -50N , 52A -52N can also include doping and /or any layer located above the buffer layer , can be grown
densities that are significantly different from the doping in multiple steps , one or more of which can include pattern
density of the compressive layers 18A - 18N and the tensile ing. Such patterning can be achieved by etching and /or
layers 20A - 20N . In an embodiment, the differences can be masking the layer, masking and subsequent overgrowth , by
equal to or greater than 100 % different. This change in 5 producing voids during overgrowth process , and / or the like.
doping density between the layers can lead to changes in Regardless, the patterning can be configured to reduce an
stresses within the layers, which can further affect the overall stress accumulated in the corresponding layer struc
overall stresses within the structures 10D - 10G . For example , ture .
in FIG . 4E , the transitional layer 19A can comprise a graded For example , FIGS. 8A and 8B show illustrative patterns
doping composition or a delta doping composition with 10 of a surface of a compressive layer 18 with a tensile layer 20
doped interlayers in the proximity of the interface of the grown thereon according to embodiments . In FIG . 8A , the
transitional layer 19A and the tensile layer 20A . In another surface of the compressive layer 18 is patterned with a
example , the transitional layer 19A can comprise graded plurality of stripes 32A - 32C , while in FIG . 8B , the surface
doping composition or delta doping composition with doped of the compressive layer 18 is patterned with a plurality of
interlayers in the proximity of the interface of the transi- 15 windows 34A - 34F . However, it is understood that the stripe /
tional layer 19A and the compressive layer 18A . In another window patterns are only illustrative of various patterns that
example , the doped interlayers can be in a central portion of can be utilized . Furthermore, it is understood that similar
the transitional layer 19A . It is understood that the transi patterns can be formed on a surface of a substrate 12 , a
tional layers 19A - 19N , 21A - 21N and the composite layers buffer layer 14 , and /or a tensile layer 20 prior to the growth
50A -50N , 52A -52N can be modified using more than one 20 of a subsequent layer thereon . Regardless , each pattern can
approach discussed herein ( e.g ., modifying the V / III ratio , produce an interface where the layers 18 , 20 have a common
the composition , and/ or the doping density ). boundary in both a vertical direction of growth and in a
Dislocation density of a layer can be analyzed using lateral direction of the layer.
bright field opticalmicroscope images . To this extent, FIGS. When patterning is employed on the surfaces of multiple
5A and 5B show illustrative bright field optical microscope 25 layers , the relative positioning of the patterning elements
images 22A , 22B of layers according to an embodiment. In and /or the patterns can be varied for the surfaces of adjacent
FIG . 5A , the image 22A corresponds to a layer grown patterned layers . For example , FIGS. 9A and 9B show
without any strain modulation described herein . As illus - illustrative patterning arrangements according to embodi
trated , the layer includes various micro - cracks. In FIG . 5B , ments . In FIGS. 9A and 9B , an interface between a tensile
the image 22B corresponds to a layer grown using strain 30 layer 20A and a compressive layer 18A has a first pattern
modulation described herein . As illustrated , the layer shown 42A , and an interface between the compressive layer 18A
in the image 22B has a significant reduction in the number and a tensile layer 20B has a second pattern 42B . The
of cracks, and is substantially crack -free . In each image 22A , patterns 42A , 42B can be formed by plurality of patterning
22B , the black bars indicate a distance of one hundred elements, for example, a series ofmasked domains or voids
micrometers . 35 located at the respective interfaces . However, in the structure
Additionally , analysis of the dislocation density of a layer 40A , the patterning elements of the patterns 42A , 42B are
can include analysis of an X -ray diffraction (XRD ) rocking laterally offset from one another , thereby forming a vertical
curve, where the full width at half minimum (FWHM ) of checkerboard - like formation of the patterning elements. In
( 102 ) reflection is related to the dislocation density. To this contrast, in the structure 40B , the patterning elements of the
extent, FIG . 6 shows an illustrative plot of a ( 102) XRD 40 patterns 42A , 42B are positioned at substantially the same
rocking curve FWHM as a function of layer thickness lateral locations.
according to an embodiment. The plot corresponds to an It is understood that a device or a heterostructure used in
AlN layer grown using strain modulation as described forming a device including a structure described herein can
herein . As a illustrated , the AIN ( 102 ) XRD rocking curve be fabricated using any solution . For example , a device /
FWHM is reduced as the layer thickness increases, which 45 heterostructure can be manufactured by obtaining ( e .g .,
indicates a reduction in a density of the edge dislocations. forming, preparing, acquiring, and /or the like ) a substrate
FIG . 7 shows a possible mechanism for the reduction of 12 , forming (e . g ., growing) a buffer layer 14 thereon , and
dislocation density provided by a growth procedure growing a semiconductor heterostructure 16 as described
described herein . As illustrated , the structure 30 includes a herein . Furthermore , the fabrication can include patterning a
substrate 12, a buffer layer 14 , a layer 20A having a tensile 50 surface of the substrate 12 , the buffer layer 14 , and /or a
stress, a layer 18A having a compressive stress , and a layer semiconductor layer as described herein , the deposition and
20B having a tensile stress. A series of dislocations can removal of a temporary layer, such as mask layer, the
propagate from the substrate 12 into the upper layers . formation of one or more additional layers not shown , and / or
However, as the dislocations propagate , some or all of the the like . Additionally, one or more metal layers, contacts,
dislocations will tend to bend , such as shown in the region 55 and / or the like can be formed using any solution . The
32 , due to the tensile and compressive stresses . As a result, heterostructure / device also can be attached to a submount
a number of threading dislocations present in the upper via contact pads using any solution .
regions of the structure 30 , e . g ., in layer 20B , can be The patterning of a layer can be performed using any
significantly reduced from the number propagating from the solution . For example, the patterning can include defining a
substrate 12 . 60 set of regions on a top surface of the layer for etching using ,
In an embodiment, a surface of one or more layers can be for example, photolithography to apply a photoresist defin
patterned , which can be configured to provide an additional ing the set of regions , or the like. The set of openings having
relaxation mechanism for reducing cracks and / or threading a desired pattern can be formed , e. g ., by etching in the set of
dislocations in a structure . For example , a surface of the defined regions of the layer. Subsequently , the photoresist
substrate 12 and/or the buffer layer 14 can be patterned , e. g., 65 can be removed from the surface. Such a process can be
using etching, masking, a combination of etching and mask - repeated one or more times to form a complete pattern on the
ing, and /or the like . A layer, such as the buffer layer 14 layer. The patterning of a layer also can include applying
 US 10 , 158 ,044 B2
11 12
(e. g., depositing ) a mask (e .g., silicon dioxide, a carbon the program code can be perceived , reproduced , or other
based material , or the like ) over a second set of regions on wise communicated by a computing device .
the top surface of the layer. When the pattern also includes In another embodiment, the invention provides a method
a set of openings, the second set of regions can be entirely of providing a copy of program code , which implements
distinct from the locations of the set of openings . Further - 5 some or all of a process described herein when executed by
more , as described herein , the formation of a layer can a computer system . In this case , a computer system can
include multiple repetitions of the patterning process. In this process a copy of the program code to generate and transmit ,
for reception at a second , distinct location , a set of data
case, each repetition can vary from the previous repetition in signals
one or more aspects. For example , a repetition can include 10 changedthatin has one or more of its characteristics set and /or
both applying a mask and forming openings on a surface , program code in athemanner
such
set of
as to encode a copy of the
data signals . Similarly, an
only forming openings, only applying a mask , and /or the embodimentof the invention provides a method ofacquiring
like. Additionally, as described herein , the locations of the a copy of program code that implements some or all of a
masked and /or opening portions for a repetition can be process described herein , which includes a computer system
vertically offset from the locations ofI the
the adjacent
adjacent repetition
repetition .. 15 receiving the set of data signals described herein , and
In an embodiment, the invention provides a method of translating the set of data signals into a copy of the computer
designing and / or fabricating a circuit that includes one or program fixed in at least one computer-readable medium . In
more of the devices designed and fabricated as described either case , the set of data signals can be transmitted /
herein . To this extent, FIG . 10 shows an illustrative flow received using any type of communications link .
diagram for fabricating a circuit 126 according to an 20 In still another embodiment, the invention provides a
embodiment. Initially, a user can utilize a device design method of generating a device design system 110 for design
system 110 to generate a device design 112 for a semicon - ing and/ or a device fabrication system 114 for fabricating a
ductor device as described herein . The device design 112 can semiconductor device as described herein . In this case , a
comprise program code , which can be used by a device computer system can be obtained ( e .g ., created , maintained ,
fabrication system 114 to generate a set of physical devices 25 made available , etc . ) and one or more components for
116 according to the features defined by the device design performing a process described herein can be obtained ( e. g .,
112 . Similarly, the device design 112 can be provided to a created , purchased , used , modified , etc .) and deployed to the
circuit design system 120 ( e . g ., as an available component computer system . To this extent, the deployment can com
for use in circuits ), which a user can utilize to generate a prise one or more of: ( 1) installing program code on a
circuit design 122 ( e . g ., by connecting one or more inputs 30 computing device; ( 2 ) adding one or more computing and / or
and outputs to various devices included in a circuit). The 1/ 0 devices to the computer system ; (3 ) incorporating and /or
circuit design 122 can comprise program code that includes modifying the computer system to enable it to perform a
a device designed as described herein . In any event, the process described herein ; and /or the like.
circuit design 122 and /or one or more physical devices 116 The foregoing description of various aspects of the inven
can be provided to a circuit fabrication system 124 , which 35 tion has been presented for purposes of illustration and
can generate a physical circuit 126 according to the circuit description . It is not intended to be exhaustive or to limit the
design 122 . The physical circuit 126 can include one or more invention to the precise form disclosed , and obviously , many
devices 116 designed as described herein . modifications and variations are possible . Such modifica
In another embodiment, the invention provides a device tions and variations that may be apparent to an individual in
design system 110 for designing and / or a device fabrication 40 the art are included within the scope of the invention as
system 114 for fabricating a semiconductor device 116 as defined by the accompanying claims.
described herein . In this case , the system 110 , 114 can
comprise a general purpose computing device , which is What is claimed is :
programmed to implement a method of designing and /or 1 . A semiconductor heterostructure comprising:
fabricating the semiconductor device 116 as described 45 a plurality of semiconductor layers epitaxially grown over
herein . Similarly, an embodiment of the invention provides a substrate , the plurality of semiconductor layers
a circuit design system 120 for designing and /or a circuit including a set of periods, each period including :
fabrication system 124 for fabricating a circuit 126 that a first semiconductor layer, wherein the first semicon
includes at least one device 116 designed and / or fabricated ductor layer is grown using a first molar ratio of
as described herein . In this case , the system 120, 124 can 50 group V precursors to group III precursors (first V / III
comprise a general purpose computing device, which is ratio ) causing a first stress being one of: a tensile
programmed to implement a method of designing and /or stress or a compressive stress ; and
fabricating the circuit 126 including at least one semicon a second semiconductor layer located over the first
ductor device 116 as described herein . semiconductor layer, wherein the second semicon
In still another embodiment, the invention provides a 55 ductor layer is grown using a second molar ratio of
computer program fixed in at least one computer-readable group V precursors to group III precursors (second
medium , which when executed , enables a computer system V /III ratio ) causing a second stress being the other
to implement a method of designing and / or fabricating a of: the tensile stress or the compressive stress ,
semiconductor device as described herein . For example, the wherein at least one of the first stress or the second
computer program can enable the device design system 110 60 stress is graded .
to generate the device design 112 as described herein . To this 2 . The heterostructure of claim 1 , wherein each period
extent, the computer - readable medium includes program further includes a first transitional layer located between the
code, which implements some or all of a process described first semiconductor layer and the second semiconductor
herein when executed by the computer system . It is under layer , wherein the first transitional layer includes a region
stood that the term “ computer- readable medium " comprises 65 having substantially no tensile or compressive stress.
one or more of any type of tangible medium of expression, 3 . The heterostructure of claim 2 , further comprising a
now known or later developed , from which a stored copy of second transitional layer located between each period.
 US 10 , 158, 044 B2
13 14
4 . The heterostructure of claim 3 , wherein the second a second semiconductor layer directly on the first
V /III ratio varies continuously in the transitional layer. semiconductor layer, wherein the second semicon
5 . The heterostructure of claim 1, wherein the first and ductor layer has a second stress being the other of:
second V / III ratios vary continuously in the first semicon the tensile stress or the compressive stress , wherein
ductor layer and the second semiconductor layer. at least one of the first or second stress is graded .
6 . The heterostructure of claim 1, wherein the first and 14 . The structure of claim 13 , further comprising a buffer
second V /III ratios are constant in the first and second
semiconductor layers . layer located between the substrate and the plurality of
semiconductor
7 . The heterostructure of claim 1 , wherein the first V / III sem15 . The structure layers .
of claim 14 ,wherein the buffer layer has
ratio in the first transitional layer varies in a first direction 100 a thickness up to approximately
and the second V /III ratio in the second transitional layer two thousand nanometers .
varies in a second direction opposite of the first direction . 16 . The structure of claim 13 , each period further com
8. The heterostructure of claim 3 , wherein a semiconduc prising a first transitional layer located between the first
semiconductor layer and the second semiconductor layer ,
tor composition varies in the first and second transitional wherein the first transitional layer includes a region having
layers .
9 . The heterostructure of claim 1 , further comprising a 15 substantially no tensile or compressive stress .
17 . The structure of claim 16 , further comprising a second
composite layer located between the first semiconductor
layer and the second semiconductor layer, wherein the transitional layer located between each period , wherein a
V / III ratio varies continuously in the first and second tran
composite layer includes a plurality of interlayers , wherein
an interlayer in the plurality of interlayers located in a 20 sitional layers .
18 . The structure of claim 17 , wherein a V /III ratio varies
portion of the composite layer that is closer to the tensile continuously
stress includes a higher Almolar fraction and an interlayer in the first and second semiconductor layers .
in the plurality of interlayers located in a portion of the 19 . The structure of claim 17 , wherein the V / III ratio
composite layer that is closer to the compressive stress remains layers .
constant in the first and second semiconductor
includes a higher Ga molar fraction .
10 . The heterostructure of claim 1, wherein a thickness of 25 method
20. A method of fabricating a semiconductor structure, the
comprising :
each of the first semiconductor layer and the second semi growing a plurality of group III nitride semiconductor
conductor layer is greater than a critical thickness to avoid layers over a substrate using a set of epitaxial growth
pseudomorphic growth . periods, wherein each epitaxial growth period includes:
11 . The heterostructure of claim 1, wherein the first 30 epitaxially growing a first group III nitride semicon
semiconductor layer and the second semiconductor layer are
formed of group III nitride materials. ductor layer having a first stress being one of: a
12 . The heterostructure of claim 1 ,wherein a composition tensile stress or a compressive stress ; and
of the first semiconductor layer and a composition of the epitaxially growing a second group III nitride semicon
second semiconductor layer differ by no more than approxi- 35 ductor layer having a second stress being the other
mately five percent. of: the tensile stress or the compressive stress
13 . A semiconductor structure including : directly on the first semiconductor layer, wherein the
a substrate ; and epitaxially growing the first semiconductor layer and
a plurality of semiconductor layers on the substrate , the the epitaxially growing the second semiconductor
plurality of semiconductor layers including a set of 40 layer use molar ratios of group V precursors to group
periods, each period including: III precursors that differ by at least ten percent, and
a first semiconductor layer , wherein the first semicon wherein at least one of the first or second stresses is
ductor layer has a first stress being one of: a tensile graded .
stress or a compressive stress; and