Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
22 views

VLSI Design Module 4- Sequential circuit design notes

Uploaded by

rashmi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
22 views

VLSI Design Module 4- Sequential circuit design notes

Uploaded by

rashmi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

Syllabus

Module-4 10 Hours/L3
Combinational Circuit Design: Circuit Families- Static CMOS, Ratioed Circuits, Cascode
Voltage Switch Logic, Dynamic Circuits, Pass-Transistor Circuits.
Sequential Circuit Design: Circuit Design of Latches and Flip-flops, Conventional CMOS
Latches, Conventional CMOS Flip-flops, Pulsed Latches, Resettable Latches and Flip-flops,
Enabled Latches and Flip-flops. (Text-1)

Sequential Circuit Design


Sequential circuits are circuits in which the output depends on previous as well as current
inputs; such circuits are said to have state. Finite state machines and pipelines are two
important examples of sequential circuits.

Sequential circuits are static and dynamic circuits. Sequential circuits consists sequencing
circuits/ elements. Static circuits refer to gates that have no clock input, such as
complementary CMOS, pseudo-nMOS, or pass transistor logic. Dynamic circuits refer to
gates that have a clock input, especially domino logic.
A sequencing element with static storage employs some sort of feedback to retain its output
value indefinitely. A sequential element with dynamic storage maintains its value as charge
on a capacitor that will leak away if not refreshed for a long period of time.

Latches and flip-flops


Latches and flip-flops are the two most commonly used sequencing elements.
Both latches and flip-flops have three terminals: data input (D), clock (clk), and data output
(Q).
In a latch when the clock is high, data from D flows to Q. In this state the latch is said to be
transparent.
In a latch when the clock is low, data from D does not flows to Q, but holds the present
value of Q as output. In this state the latch is said to be opaque.
The flip-flop is an edge-triggered device that copies D to Q on the rising edge of the clock
and ignores D at all other times. These are illustrated in figure below.
Circuit Design of Latches and Flip-Flops

Conventional CMOS latches are built using pass transistors or tristate buffers to pass the data
while the latch is transparent and feedback to hold the data while the latch is opaque.

Conventional CMOS Latches

The Conventional CMOS latch is as shown in the figure below:

The way the Conventional CMOS latch is built is as explained below:

Figure (a) below shows a simple latch built from a single transistor..

Figure (a)
It has four limitations which are:
1. The output does not swing from rail-to-rail (i.e., from GND to VDD); it never rises above
VDD – Vt.
2. The output is also dynamic; in other words, the output floats when the latch is opaque. If
it floats long enough, it can be disturbed by leakage.
3. D drives the diffusion input of a pass transistor directly, leading to noise issues.
4. The state node is exposed, so noise on the output can corrupt the state.

Replace the single nMOS pass transistor in Figure (a) with a CMOS transmission gate as
shown in Figure(b) below. This offers rail-to-rail output swings. It requires a complementary
clock φ` (φ bar) ,which is provided as an additional input.

Figure (b)
Adds an output inverter to the circuit in Figure (b) so that the state node X is isolated from
noise on the output. This is shown in Figure(c). This creates an inverting latch.

Figure (c)

To provide buffered input add an inverter as buffer to the input as shown in Figure (d) below.

Figure (d)

The latches shown in Figure(c) and (d) are both fast dynamic latches. Dynamic nodes retain
their values for only a short time. Therefore, practical latches need to be staticized, that is
made to retain values. This is done by adding feedback as shown in Figure (e). When the
clock is 1, the input transmission gate is ON, the feedback tristate is OFF, and the latch is
transparent. When the clock is 0, the input transmission gate turns OFF, the feedback tristate
turns ON, retaining the value of X at the correct level.

Figure (e)
A large noise spike on the output can propagate backward through the feedback gates and
corrupt the state node X, hence the output is taken from X through a separate inverter as
shown in Figure(f). This is the Conventional CMOS latch which is static, all nodes swing
rail-to-rail, the state noise is isolated from output noise, and the input drives transistor gates
rather than diffusion.
Figure(f)

Improvement on Conventional CMOS latch - Jamb latch


Figure below shows the jamb latch, a variation of Figure (f) that reduces the clock load and
saves two transistors by using a weak feedback inverter in place of the tristate. This requires
careful circuit design to ensure that the tristate is strong enough to overpower the feedback
inverter in all process corners.

CMOS latch with Write and Read facility


Figure below shows another jamb latch commonly used in register files and Field
Programmable Gate Array (FPGA) cells. Many such latches read out onto a single Dout wire
and only one latch is enabled at any given time with its RD signal.

C2MOS latch is shown at Figure 10.18 below.


Conventional CMOS Flip-Flops
Conventional CMOS Flip-Flops can be built by using two latches as shown in the figure and
graph below.
The clock clk is inverted to obtain the inverted clock.

Data D is provided to 1st latch which is clocked by the inverted clock. When clock, clk, is
‘0’, first latch is transparent and the second latch is opaque, so value of D passes to Q of the first
latch.
When clock, clk, is ‘1’, first latch is opaque and the second latch is transparent, so value of D
passes to Q of the second latch.
By this only during the rising edge of the clk Q of the second latch follows D, which the
requirement of Flip-Flop.

Figure below shows a Conventional CMOS flip-flop built using two latches

Flip-Flops using C2MOS latches is as in figure below


Pulsed Latches
A pulsed latch can be built from a conventional CMOS transparent latch driven by a brief
clock pulse. Figure below shows a simple pulse generator. The pulsed latch is faster than a
regular flip-flop because it involves a single latch rather than two, thus cutting down delay
time of one latch. It also consumes less energy.

The below wave form and the table explains the circuit above

Time φ nMOS nMOS nMOS pMOS pMOS Φp


- down – en – up – left – right
Initial 0 ON 1 OFF ON OFF 0
After delay t1 from starting 1 ON 1 ON OFF ON 1
of clk φ rising edge
After delay t2 from starting 1 OFF 1 ON OFF ON 0
of clk φ rising edge
The pulse width of φp is t2-t1, which is way much less than the pulse width of the clock φ.
This is caused due to the delay of the “slow” inverter.
The output of the pulse generator φp in Figure(a) below is given to the clk or φ input of a
single conventional latch in Figure (b) below to get a Pulsed Latch.
Figure(a)

Figure(b)
Resettable Latches and Flip-Flops

Most practical sequencing elements require a reset signal to enter a known initial state on
startup and ensure deterministic behavior. Reset signal high or active makes the Q output of
the latch or the Flip-flop ‘0’.
The symbol for Latches and Flip-flops with Reset are as below:

There are two types of reset: synchronous and asynchronous.

Synchronous latch and Synchronous Flip-flop


Figure(a) below shows Synchronous latch and Figure(b) shows Synchronous Flip-flop
Synchronous reset simply requires ANDing the input D with reset. This ensures reset makes
Q as ‘0’ only during clk φ level 1 or rising edge.

Figure(a) Figure(b)
Asynchronous latch and Asynchronous Flip-flop
Figure(a) below shows Asynchronous latch and Figure(b) shows Asynchronous Flip-flop
Asynchronous reset requires gating both the data and the feedback to force the reset
independent of the clock φ.
The tristate NAND gate can be constructed from a NAND gate in series with a clocked
transmission gate.

Figure(a) Figure(b)

Settable latches and flip-flops


Settable latches and flip-flops force the output high instead of low. They are similar to
resettable elements of Asynchronous Reset Latch and Flip-flop in the above Figures but
replace NAND with NOR and reset with set. Figure below shows a flip-flop combining both
asynchronous set and reset.
Enabled Latches and Flip-Flops
Sequencing elements also often accept an enable input. When enable en is low, the element
retains its state independently of the clock. The enable can be performed with an input
multiplexer or clock gating, as shown in Figure below. The input multiplexer feeds back the
old state when the element is disabled. The multiplexer adds area and delay.
Clock gating does not affect delay from the data input and the AND gate can be shared
among multiple clocked elements. Moreover, it significantly reduces power consumption
because, the clock on the disabled element does not toggle. However, the AND gate delays
the clock, potentially introducing clock skew.

You might also like