Addc Lab Manual (Ec322i2e)

PP
ANALYSIS AND DESIGN OF DIGITAL

CIRCUITS (EC322I2E)
(EC32212E)
LABORATORY MANUAL
III Semester B.E.
(Academic Year: 2023-24)
Insert any equipment/lab related pictures
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
SAHYADRI
College of Engineering & Management
Adyar, Mangaluru - 575009
STUDENT DETAILS
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STAFF DETAILS
NAME OF THE FACULTY
NAME OF THE INSTRUCTOR
EVALUATION
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EVALUATION*
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TOTAL
*OBE Sheet Evaluation
Signature of the Faculty

ENGINEERING
SAHYADRI
Institutional Vision & Mission
VISION
To be a premier institution in Technology and Management by fostering excellence in
education, innovation, incubation and values to inspire and empower the young minds.
MISSION
M1: Creating an academic ambience to impart holistic education focusing on individual
growth, integrity, ethical values and social responsibility.
M2: Develop skill-based learning through industry-institution interaction to enhance

competency and promote entrepreneurship.
M3: Fostering innovation and creativity through competitive environment with state of-
the-art infrastructure.

ENGINEERING
SAHYADRI
Department Vision & Mission
VISION
To establish the department as a centre of excellence in creating globally competitive,
socially responsible engineers to excel in the field of Electronics and Communication by
transforming future challenges to sustainable opportunities.
MISSION
M1: Inculcating a distinctive teaching learning process to provide extensive knowledge of
principles and solutions to challenges in the relevant domain.
M2: Nurturing the growth of every individual through inventive, dynamic and conductive
learning environment using modern education techniques and industry-oriented pedagogy.
M3: Imparting leadership qualities with ethical values among students to cater societal and
environmental needs.

ENGINEERING
SAHYADRI
COURSE OUTCOMES
Bloom’s
COs Description
Level
Apply the knowledge of digital electronics to construct the combinational
circuits using SOP and POS expressions and simplify the Boolean
EC322I2E CL3
functions using K- map, Quine – McCluskey minimization Technique,
and MEV techniques.
Construct combinational logic circuits like multiplexers, encoders,
EC322I2E CL3
decoders, adders, subtractors, and comparators.
Demonstrate building blocks of sequential logic circuits.
EC322I2E CL3
EC322I2E Design shift registers & Synchronous counters using flip-flops. CL3
Develop Mealy/Moore FSM models and state diagrams for the given
EC322I2E CL3
sequential circuits.
CO-PO-PSO Mapping
POs
COs 1 2 3 4 5 6 7 8 9 10 11 12 PSO1 PSO2 PSO3
EC322I2E 3 3 2 2 2 2 2 2 2
EC322I2E 3 2 2 2 2 2 2 2 2
EC322I2E 3 2 2 2 2 2 2 2 2
EC322I2E 3 2 2 2 2 2 2 2 2
EC322I2E 3 2 2 2 2 2 2 2 2
Assessment Components (ACs)

Assessment Component (AC) Assessment Component Description
AC1: Written Work
AC2: Fundamental Knowledge to
conduct experiment
AC3: Viva
AC4: Interaction during conduction of
Experiment
AC5: Punctuality

ENGINEERING
SAHYADRI
List of Experiments
Expt. No. Objective of the Experiment Page No
Simplification, realization of Boolean expressions using logic Gates/

1 1-9
Universal gates.
Analyze the difference in design and functionality between a Half

2 10-18
Subtractor/ Adder and Full Subtractor / adder
Implementation of
3 (i) Parallel Adder/Subtractor using IC 7483. 19-25
(ii)BCD to Excess-3 code conversion and vice-versa.
4 Demonstrate the conversion of Binary to Gray code and vice versa 26-32
5 Design of Multiplexer using IC 74153 33-38
Utilizing the IC7485, demonstrate the circuit connections and

6 configurations required for the implementation of a one and two-bit 39-43
comparator
Verify the truth table of flip-flops

7 i.JK Master slave 44-47
ii.T type and D type
Demonstrate the circuit connections and configuration required to

8 48-50
realize a 3-bit counter using the IC7476
Realize the following shift registers using IC7474

9 51-57
(i) SISO (ii) SIPO (iii) PISO (iv) PIPO
Realize
10 I. Ring Counter using IC7476 58-62
ii. Jhonson counter using IC7476

ENGINEERING
SAHYADRI
Program Outcomes (POs) and Program Specific Outcomes (PSOs)
PO1. Engineering Knowledge: Apply knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
PO2. Problem Analysis: Identify, formulate, research literature and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences and engineering sciences.
PO3. Design/ Development of Solutions: Design solutions for complex engineering problems and
design system components or processes that meet specified needs with appropriate
consideration for public health and safety, cultural, societal and environmental considerations.
PO4. Conduct Investigations of complex problems using research-based knowledge and research
methods including design of experiments, analysis and interpretation of data and synthesis of
information to provide valid conclusions.
PO5. Modern Tool Usage: Create, select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO6. The Engineer and Society: Apply reasoning informed by contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to professional engineering practice.
PO7. Environment and Sustainability: Understand the impact of professional engineering
solutions in societal and environmental contexts and demonstrate knowledge of and need for
sustainable development.
PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice.
PO9. Individual and Team Work: Function effectively as an individual, and as a member or leader
in diverse teams and in multi-disciplinary settings.
PO10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as being able to comprehend and write
effective reports and design documentation, make effective presentations and give and receive
clear instructions.
PO11. Project Management and Finance: Demonstrate knowledge and understanding of
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
PO12. Life-long Learning: Recognize the need for and have the preparation and ability to Engage
in independent and lifelong learning in the broadest contest of technological change.
PSO1: Exhibit competency in IoT and Embedded systems

PSO2: Comprehend the technological advancement in Signal Processing and Communication.
PSO3: Apply a professional approach to provide a sustainable solution to VLSI and the semiconductor
sector.

ENGINEERING
SAHYADRI
EC322I2E: ANALYSIS AND DESIGN OF DIGITAL CIRCUITS
EXPERIMENT No.01: Simplification, realization of Boolean

expressions using logic gates & Universal gates.
1.1Objectives 1.6 Observations

1.2 Apparatus Required 1.7 Results
1.3 Pre-Requisite 1.8 Pre-Experimentation Questions
1.4 Introduction 1.9 Post-Experimentation Questions
1.5 Procedure
1.1 Objectives:
Simplification, realization of Boolean expressions using logic gates & universal gates.
1.2 Apparatus Required:
Component Specification Qty

AND Gate IC 7408 1
OR Gate IC 7432 1
NOT Gate IC 7404 1
NAND Gate IC 7400 1
NOR Gate IC 7402 1
XOR Gate IC 7486 1
Patch Cord - 1 set
Digital IC Trainer Kit - 1
1.3 Pre-Requisite: basic gate
1.4 Introduction:
Logic gates are electronic circuits that operate on one or more input signals to produce an
output signal. The gates are blocks of hardware that produces the equivalent of logic 1 or
logic 0 output signals if input logic requirements are satisfied. Gate INPUTS are driven by
voltages having two nominal values, e.g. 0V and 5V representing logic 0 and logic 1
respectively. The OUTPUTS of a gate provide two nominal values of voltage only, e.g. 0V
and 5V representing logic 0 and logic 1 respectively. There is always a time delay between
an input being applied and the output responding. The different types of logic gates are as
follows:
Department of Electronics and Communication Engineering, SCEM, Mangaluru 1

NOT GATE: It has one input and one output. The output is the complement of the input.
OR GATE: The gate has two inputs and one output. The output is logic ‘1’ when either of the
inputs or both the inputs are at logic’1’.
AND GATE: The gate has two inputs and one output. The output is logic ‘1’ only when both
the inputs are high.
NAND GATE: It is an AND gate followed by a NOT gate. It is the complement of AND gate.
The output is logic ‘0’ when both the inputs are at logic ‘1’; else the output is always in the
high state.
NOR GATE: It is an OR gate followed by a NOT gate. It is the complement of OR gate.
The outputis logic ‘1’ when both the inputs are at logic ‘0’; else the output is always in the low state.
EXOR GATE: It is logic gate whose output is in the high state when both the inputs are
not same. When the both the inputs are high and when both are low, the output is low.
EXNOR GATE: It is logic gate whose output is in the high state when the both the inputs
are high and when both are low. The output is low when both the inputs are not same
1.5 Procedure:
1. Check all the components & patch cords, whether they are in good condition.
2.Insert the appropriate IC into the IC base.
3.Do the connection as shown in the Logic Diagram.
4.Give the supply to the trainer kit.
5.Verify the Truth Table & Observe the output for corresponding combination

1.6 Observations:
Implementation of Logic Gates
1. NOT Gate: - [IC7404] Truth Table

Symbol
I/P (A) O/P (𝑨)
0 1
Ā
1 0
2. OR Gate: - [IC7432]
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

3. AND GATE: - [IC7408]

Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
4. NAND GATE: - [IC 7400] Truth Table
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Department of Electronics and Communication Engineering, SCEM, 4

5. NOR GATE: [IC 7402]

Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
6. XOR GATE: - [IC 7486]

Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
7. EX-NOR GATE: - [IC4077]
Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Department of Electronics and Communication Engineering, SCEM, 5

Implementation of Basic Gates Using Universal Gates

1. NAND GATE AS
Truth Table
(a) AND GATE A B Y

0 0 0
0 1 0
1 0 0
1 1 1
Truth Table
(b) OR GATE
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
(c) NOT GATE

Truth Table
I/P (A) O/P (𝑨)
0 1
1 0
(d) NOR GATE

Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Department of Electronics and Communication Engineering, SCEM, Mangalore 6

(e) EX-OR GATE

Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
(f) EX-NOR GATE

Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
1.NOR Gate As
(a) AND GATE
Truth Table
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

(b) OR GATE
Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
(c) NOT GATE

Truth Table
I/P (A) O/P (𝑨)
0 1
1 0
(d) NAND GATE

Truth Table
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
(e) EX-OR GATE
Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

(f) EX-NOR GATE

Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
1.6 Results:
• Truth Table is verified.
1.7 Pre – Experimentation Questions:
• What is a logic gate?
• What is universal gate?
• What are basic gates?
• Why NAND & NOR gates are called universal gates?
• State De Morgan’s Theorem.
1.8 Post – Experimentation Questions:
• What is the primary motivation of using Boolean algebra to simplify logic expression?
• Which of the logic operation is represented by the sign ‘’ in Boolean algebra?
• Which of the 2-input logic gate can be used to implement an inverter circuit?
• Which are the logic gates whose all output entries are logic 1 except for one entry there is
logic 0?
• TTL operates from a to volts.

EXPERIMENT No.02: Analyze the difference in design and

functionality between a Half Subtractor/Adder and Full
Subtractor / adder

2.5 Procedure
2.1 Objectives:
i) To realize Half adder, Full adder using basic gates and NAND gates.
ii) To realize Half subtractor& Full subtractor using basic gates and NAND gates.

AND Gate IC 7408 2
OR Gate IC 7432 2
NOT Gate IC 7404 1
XOR Gate IC 7486 1
2 I/P NAND Gate IC 7400 2
NOR Gate IC 7402 2
Patch Cord - 1 set
2.3 Pre-Requisite: Operation of basic gates and universal gates, Binary addition and subtraction,
simplification of Boolean expressions, Boolean laws and theorems.
2.4 Introduction:
An adder is a digital circuit that performs addition of numbers. The half adder adds two binary
digits and produces two outputs as sum and carry; XOR is applied to both inputs to produce
sum and AND gate is applied to both inputs to produce carry.

The full adder adds 3 one-bit numbers, where two can be referred to as operands and one can
be referred to as bit carried in. And produces 2-bit output, and these can be referred to as
output carry and sum.
The simplest binary subtractor is called half subtractor. It has two input bits and two output bits.
One output bit is the Difference and the other is borrowed. They are represented by ‘D’ and ‘B’
respectively in logic symbol.
When two input bits and a borrow have to be subtracted the number of input bits equal to three
and the input combinations increases to eight, for this a full subtractor is used.
2.5 Procedure:
2. Insert the appropriate IC into the IC base.
3. Do the connection as shown in the Logic Diagram.
4. Give the supply to the trainer kit.
5. Verify the Truth Table & Observe the output for corresponding combination.
TRUTH TABLE FOR HALF ADDER:
Inputs Output
A B carry sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
K-map Simplification

HALF ADDER USING AOI GATES

_ _
SUM=AB +AB
CARRY=AB
TRUTH TABLE FOR FULL ADDER:

A B C Cary Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

FULL ADDER USING AOI GATES:

(i) Half subtractor& Full subtractor using
a) Basic gates b) NAND gates
I. HALF SUBTRACTOR
Block Diagram Truth Table
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
K-Map Simplification
HALF SUBTRACTOR USING EX-OR AND BASIC GATES:
̅̅̅̅ +𝐵𝐴
DIFFERENCE D =𝐴𝐵 ̅̅̅̅
= A+B
BORROW = 𝐴B

HALF SUBTRACTOR USING AOI GATES:
TRUTH TABLE FOR FULL SUBTRACTOR:
A B C Borrow Difference
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

FULL SUBTRACTOR USING AOI GATES:

FULL SUBTRACTOR USING EX-OR AND BASIC GATES:
2.6 Results:
• Truth Table of Half adder, Full adder, half subtractor& Full subtractor is realized using
basic gates and NAND gates.
2.7 Pre -Experimentation Questions:

• What is a half adder and half subtractor?
• What are the limitations in half adder/subtractor?
• What is full adder/subtractor?
• What do you mean by prime implicant, prime implicant and essential prime implicant
mean?
• Among K-map, VEM technique & Quine-McCluskey, which is easier to use?


• Draw the block diagram of full adder as a combination of two half adder.
• What is the Boolean expression for sum and carry of a full adder from the truth table?
• What is the difference between adder and subtractor?
• What is the difference between Combinational circuit and Sequential circuit?
• What is the other name given to K-map?

EXPERIMENT No.03: Implementation of

(i)Parallel Adder/Subtractor using IC 7483.
(ii) BCD to Excess – 3 code conversion and vice versa
3.1 Objectives 3.6 Observations

3.5 Procedure
3.1 Objectives:
i) Realization of Parallel adder/subtractor using 7483chip
ii) BCD to EXCESS-3 code conversion and vice versa
4-Bit Full Adder IC 7483 1
XOR Gate IC 7486 2
Patch Cord - 1 set
3.3 Pre-Requisite: Number Systems, binary addition and subtraction, subtraction using 1’s & 2’s
complement, Number conversion methods.
3.4 Introduction:
Many high-speed adders available in integrated circuit form utilize the look ahead carry or a
similar technique for reducing overall propagation delays. A parallel adder consists of n
number of full adders and look ahead carry circuitry needed for high speed operation. A
parallel subtractor is one where subtraction done by full adder and ahead carry circuitry. For
subtraction Cin is made equal to 1 and A-B format is used.
The Excess-3code for a decimal digit is the binary combination corresponding to the decimal
digit plus 3. For example, the excess-3 code for decimal digit 5 is the binary combination for
5+3=8, which is 1000.

3.5 Procedure:
1. Make the connections as shown.
2. For addition, make Cin=0 and apply the 4 bits as i/p for A and apply another set of 4bits
to B. Observe the o/p at S3, S2 S1 S0 and carry generated at Cout.
Repeat the above steps for different inputs and tabulate the result.
3. For subtraction Cin is made equal to 1 and A-B format is used.
A-First no, B- second no.
By Coring the i/p bits of ‘B’ with 1 complement of ‘B’ is obtained.
Further Cin, which is 1 is added to the LSB of the Cored bits. This generates 2’s
complement of B.
4. Verify the difference and polarity of differences at S0, S1, S2, S3. and Cout.
If Cout is 0, diff is –ve and diff is 2’s complement form.
If Cout is 1, diff is +ve.
5. Repeat the above steps for different inputs. And tabulate the result.
3.6 Observations:
i) 4-bitParallelAdder/Subtractor using IC 7483

4 BIT BINARY ADDER:
4 BITS BINARY ADDER/SUBTRACTOR:
EXAMPLE:
A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0
1 0 0 0 0 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
1 1 1 1 0 0 0 1 1 0 0 0 0

Cin A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0
Ex. 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0
Ex. 2 0 0 1 1 1 0 0 0 1 0 1 0 0 0
Ex. 3 1 1 0 0 1 1 0 0 0 1 0 0 0 1
Ex. 4 1 0 0 0 1 0 0 1 1 0 1 1 1 0
If carry input Cin = 0,

a) 1100 Cin = 0 b) 1001 Cin = 0
0011 1101
Cout = 0 1111 Cout = 1 0110
If carry input Cin = 1,

a) 1100 Cin = 1 b) 1001 Cin = 1
0011 1101
Cout = 0 1100 Cout = 1 0111
(a) SUBTRACTION
1) To subtract a smaller number from a larger number:
1001 Larger
0011 Smaller Take 2’s Complement =1101 & add
i.e. 1 0 0 1
1101
0 1 1 0 Cout = 1
If the end around carry is 1, result is +ve & discard the carry.
2) To subtract a larger number from a smaller number:
0011 Small
1001 Larger 2’s Complement = 0 1 1 1 & add
i.e., 0 0 1 1
0111
1 0 1 0 Cout = 0
If the end carry is 0 the result is –ve & is in 2’s complement form. To obtain the result in true
form take the 2’s Complement of it (i.e.) 1010’s 2’s complement is 0 1 1 1.

ii) BCD to Excess-3 code conversion and vice-versa.

BCD to EXCESS -3:
Truth table
BCD Code Excess – 3 code
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

EXCESS -3 to BCD:
Logic diagram:
Truth table
Excess-3 BCD
X4 X3 X2 X1 B4 B3 B2 B1
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 0 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

3.7 Results:
• Operation of Parallel adder and Parallel Subtractor were studied and checked using IC
7483.
• Operation of BCD – to – Excess3 and vice versa was studied and checked using IC
7483.

• What is the difference between serial adder and parallel adder?
• How many full adders are required to construct m bit parallel adder?
• What are the disadvantages of parallel adder?
• What is a look ahead carry adder?
• What is a serial adder?

• Significance of excess-3 code.
• Is Excess – 3 is weighted code or not?
• What is the difference between BCD and Excess-3 code?
• How many bits can be added using 7483 IC?
• If 2 10-bit numbers have to be added using Parallel adder how many full adders are
required?

EXPERIMENT No.04:
Demonstrate the conversion of Binary to Gray code and vice versa

4.3 Introduction 4.7 Pre-Experimentation Questions
4.4 Procedure 4.8 Post-Experimentation Questions
4.1 AIM: To design and set up the following circuits:

1.A 4-bit binary to gray code converter using only EX-OR gates.
2.A 4-bit binary to gray code converter using only NAND gates.
3.A 4-bit gray to binary code converter using only EX-OR gates.
4.A 4-bit gray to binary code converter using only NAND gates.
4.2 IC PACKAGES REQUIRED:
Sl. No. Name Specification

1. 7486 Quad 2 input EX-OR gate
2. 7400 Quad 2 input EX-OR gate
4.3 THEORY:
The gray code belongs to a class called change code (unit distance code), in which any 1 bit
in the group changes from 1 step to the next. The gray code is an unweighted code meaning thatthe
bit position in the code group do not have specific weight assigned to them. The code is
also known as reflected code characterized by the fact that it is imaged about the center entries
with 1-bit change.
Gray code has application in input-output devices and some types of analog to digitalcontroller.
The gray code is often used in situations where other codes, such as binary might produce
erroneous or ambiguous results during those transitions in which more than 1 bit of code is
changing.
The binary code is weighted code, which means that there are specific weights assigned to each
bit position. The weight of each successive higher position (to the left) in a binary number is
an increasing power of two. The binary representation of a decimal number consists of only
0’s and 1’s.

Binary to gray conversion:
1. The most significant bit (left most) in a gray code is same as the corresponding bit in the
binary number.
2. Going from left to right, EX-OR each adjacent bit of binary to get the next gray code bit.
Example:
Gray to binary conversion:

The most significant bit (left most) in the binary code is same as the corresponding bit in the
gray code.
EX-OR each binary bit generated to the gray bit in the next adjacent position.
Example:
4.4 PROCEDURE:
1. Draw the truth table for binary to gray code converter and gray to binary code converter.
2. Simplify the output expression using K-Map.
3. Draw the circuit diagram.
4. Check all the IC packages using digital IC trainer.
5. Make connections as shown in the circuit diagram.
6. For different binary data inputs, verify the corresponding gray code outputs according to
the truth tables.
7. And also, for different gray code inputs verify the binary data outputs according to truth
table.

4.5 Observations
BINARY TO GRAY CODE CONVERSION
BINARY INPUT GRAY OUTPUT

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-MAP SIMPLIFICATION:

BINARY TO GRAY CONVERSION USING EX-OR GATE:
BINARY TO GRAY CONVERSION USING NAND GATE

GRAY TO BINARY CONVERSION:
Truth Table:
GRAY INPUT BINARY OUTPUT

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

GRAY TO BINARY USING EX-OR GATE:
GRAY TO BINARY USING NAND GATE

4.6 Results:
• Truth table for the adder and subtractor is verified using IC 74139
• BCD – to Gray code and vice versa circuit is designed and output is verified for different
combination of input.
• What is gray code?

• What are BCD numbers?
• What is a decoder?
• What is demultiplexer?
• What is a dual pinout IC?
• Is Gray codes are generated from rotational position transducers?

• Is Gray code a weighted code?
• What is the use of Gray code?
• Which is called a self-complementing code?
• What is an ASCII code?

EXPERIMENT No.05: Design of Multiplexer using IC 74153

5.1 AIM: To design and set up the following circuits using the IC 74153
• Full adder 2. half adder 3. Full subtractor 4. Half subtractor

IC74153, 3 input AND gate, and OR gate, and NOT gate
5.3 THEORY:
Multiplexer is a digital switch. It allows digital information from several sources to be
routed onto a single output line. The 74153 is a dual 4 to 1 multiplexer. It contains two
identical and independent 4 to 1 multiplexer. Each multiplexer has separate enable inputs.
A demultiplexer is a circuit that receives information on single line and transmits this
information on one 2^n possible output lines. The selection of specific output lines is
controlled by the values of n selection lines.
5.4 PROCEDURE:
Design and implementation of a full adder and full subtractor using multiplexer.
• Use data sheets of multiplexer IC 74153 to determine input, output and control pins.
• Draw circuit diagrams of full adder and full subtractor using IC 74153.
• Build and test the circuits.

5.5 Observations
INPUT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Y = S1S0D0 + S0S1D1 + S1S0D2 + S1S0D
LOGIC DIAGRAM

PIN DIAGRAM
Truth Table of IC 74153
INPUTS OUTPUTS
1G 2𝑮 B A 1Y 2Y
0 0 0 0 1C0 2C0
0 0 0 1 1C1 2C1
0 0 1 0 1C2 2C2
0 0 1 1 1C3 2C3
0 1 0 0 1C0 0
0 1 0 1 1C1 0
0 1 1 0 1C2 0
0 1 1 1 1C3 0
1 0 0 0 0 2C0
1 0 0 1 0 2C1
1 0 1 0 0 2C2
1 0 1 1 0 2C3
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 0 0

HALF ADDER:
INPUT OUTPUT
B A SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
HALF SUBTRACTOR:
INPUT OUTPUT
B A D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
FULL ADDER
TRUTH TABLE
INPUTS OUTPUT INPUT OUTPUT
B A SUM CARRY
A B Ci SUM CARRY
0 0 Ci 0
0 0 0 0 0
0 0 1 1 0 0 1 𝐶𝑖 Ci
0 1 0 1 0 1 0 𝐶𝑖 Ci
0 1 1 0 1 1 1 𝐶𝑖 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

FULL SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT INPUTS OUTPUT

B A D B A B Ci D B
0 0 0 0 0
0 0 Ci Ci
0 0 1 1 1
0 1 𝐶𝑖 1
0 1 0 1 1
1 0 𝐶𝑖 0 0 1 1 0 1
1 1 𝐶𝑖 Ci 1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

5.6 Result: Truth table for the adder and subtractor is verified using IC 74153
5.7 Pre-Experimentation Questions

• What is the primary function of a multiplexer (MUX)?
• How many data inputs and control inputs does the IC 74153 have?
• What are the possible applications of a multiplexer in digital systems?
5.8 Post-Experimentation Questions

• What are the practical applications of the multiplexer you designed?
• Explain the purpose of each component in your circuit and its role in the
multiplexeroperation.
• What was the role of the select lines (S0 and S1) in your multiplexer design?

EXPERIMENT No.06: Utilizing the IC7485, demonstrate the circuit

connections and configurations required for the implementation of a
one and two-bit comparator

6.1 AIM:
1. To construct and verify the truth table of one-bit comparator.
2. To construct and verify the truth table of two-bit comparator.

Sl. No. Name Specification
1. IC 7404 Hex inverter
2. IC 7408 Quad 2 i/p AND gate
3. IC 7411 3 input AND gate
4. IC 7432 Quad 2 i/p OR gate
5. IC 7486 Quad 2 i/p EX-OR gate
6. IC 7485 4-bit magnitude comparator
6.3 THEORY:
Comparator is a circuit capable of combining two binary words indicating whether they are
equal and also indicates an arithmetic relationship (< >) between the binary words under
comparison.
Comparator is a combinational circuit that compares the binary quantities and generates the
output to indicate which one has greater magnitude.
Magnitude comparators are often used as a part of address decoding circuitry used in a
computer to select a specific input/output device or area of a memory for storage. Magnitude
comparators are also useful in control applications where a binary number representing the
physical variable is being controlled.
6.4 PROCEDURE:
1. Draw the truth table for BCD to Excess-3 code converter.
2. Simplify the output expressions using Karnaugh map.
3. Draw the circuit diagram.

4. Check all the IC packages using digital trainer kit.

5. Make the connections as shown in the circuit diagram.
Give input bit combinations to the circuit via switches.
6. Compare the input bit combinations and observe the output at A>B, A=B and A<B.
7. Rig up the circuit 4 bit/ 5 bit/ 8-bit comparator using 7485 chips.
8. Observe the output for different combinations of the output.
9. Clearly note down the importance of IC 7485.
6.5 Observations
(i) One-bit Comparator
Truth Table
X(E)Y(D) Z(C)
A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Logic Diagram using basic gates

(ii) 2 BIT COMPARATOR:

TRUTH TABLE:
INPUTS OUTPUTS
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K-MAP:

Logic Diagram using basic gates
6.6 Results:
• Designed and setup single bit comparator using basic gates and NAND gate and verified
the truth table.

• Which logic is used in a single bit comparator?
• What is comparator?
• Explain the working of Ex-or gate.
• What are the different types of digital comparators?
• Design a two-bit comparator using one-bit comparator.


• Write the truth table for 2-bit comparator.
• What are the applications of comparators?
• Which logic is used as a one-bit comparator?
• Can we use subtractor and divider as comparator?
• Design a 2-bit comparator circuit.

EXPERIMENT No.07: Verify the truth table of flip-flops

(i) JK Master slave
(ii)T type and D type
7.1 Objective 7.6 Observations

7.5 Procedure
7.1 Objectives:
Realize Master-Slave JK, D & T Flip-Flop using NAND Gates.

Patch Cord - 1 set
7.3 Pre-Requisite: Basic operations of flip flops like SR, JK, D & T along with its truth table.
7.4 Introduction:
JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use. The
variable J and K are called control I/Ps because they determine what the flip- flop does when
a positive edge arrives.
MASTER SLAVE J K FLIP FLOP: The race around condition of JK FF is rectified in
master save JK FF. Racing is toggling of output more than ones during the positive clock
edge. MSJK FF is created by cascading two JK FF. The clock is fed to the first stage
(Master) and is inverted and fed to the second stage (slave). This ensures that the master is
always followed by the slave and eliminates the chance of racing.
D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output until
clock pulses occur. When the clock is low, change in D value will not affect the value
Q. On the other hand, when the clock is high, Q is forced to equal the value of D. When
The clock again goes low, Q retains or stores the last value of D. A D flip flop is a stable

circuit.
whose D input is transferred to the output after a clock pulse is received.
T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an output
which is half the frequency of the signal to the T input. It is useful for constructing binarycounters,
frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by
tying both of its inputs high.
7.5 Procedure:
2.Insert the appropriate IC into the IC base.
3.Do the connection as shown in the Logic Diagram.
4.Give the supply to the trainer kit.
5.Verify the Truth Table & Observe the output for corresponding combination.
7.6 Observations:
Master-Slave JK
Truth Table
Clock J K Q+ Q+ Comment
1 0 0 Q Q No
Change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Race Around

T Flip Flop:
PRE
~1PR
1J 1Q T
1CLK
1K ~1Q
~1CLR
Truth Table
T 𝑸𝒏+𝟏 Comments
0 𝑄𝑛 No change
1 ̅̅̅̅
𝑄𝑛 Toggle
D Flip Flop:
Truth Table
D Q
0 0
1 1

7.7 Results:
• The Master slave JK flip flop, D, T flip flops were set up using NAND gates and
verified.
• What is a combinational circuit?
• What is a sequential circuit?
• What is the difference between flip-flop and latch?
• What are flip-flops?
• What are latches?
• What does a basic bi-stable element mean?
• What is the forbidden state in SR latch?
• How contact de-bouncing can be eliminated using SR latch?
• What is the difference between a latch and a flip flop?
• What is meant by race around condition? How is it eliminated?
• How to convert a JK flip flop to a D flip flop?
• How to convert a JK flip flop to a T flip flop?
• How to convert a T flip flop to a D flip flop?
• How to convert a D flip flop to a T flip flop?
• Why is a D flip flop called as a transparent flip flop?
• Can a multiplexer be used to realize a JK flip flop?
• What is MEALY sequential circuit?
• What is MOORE sequential circuit?

EXPERIMENT No.08: Demonstrate the circuit connections and

configuration required to realize a 3-bit counter using the IC7476

8.1 AIM: To design the following 3-bit synchronous counters using IC7476.
8.2 COMPONENTS REQUIRED:
1. IC 7476, IC7408, IC 7404, and IC 7432
8.3 THEORY:
A counter is a cascade of flip flops configured to output a specific s sequence on the

application of the clock. Each output of the sequence is dependent on the contents ofthe
flip flop and is called the state of the counter. The modulus of the counter is the total
number of states of the counter which counts from 0000 to 1001 and reset is called a
MOD 10 counter. In Asynchronous counters the clock pulses are applied to the flip flops
from the output of the previous flip flop.
8.4 PROCEDURE:
• 3 bit up/down counter:

• Set up the circuit as shown in the circuit diagram.
• Observe the up counting when mode control is, M=1.
• Observe the down counting when mode control is, M=0.

8.5 Observations
a) 3 BIT UP/DOWN COUNTER:
CIRCUIT:
STATE DIAGRAM: -
When M=0
When M=1

Truth Table
M Q2 Q1 Q0 M Q2 Q1 Q0
1 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1
1 0 1 0 0 0 1 0
1 0 1 1 0 0 1 1
1 1 0 0 0 1 0 0
1 1 0 1 0 1 0 1
1 1 1 0 0 1 1 0
1 1 1 1 0 1 1 1
8.6 Results:
The counter will increment on each rising edge of the clock signal, producing a binary
count from 000 to 111 and then wrapping back to 000.
8.7 Pre-Experimentation Questions
• What is the primary function of the IC7476?
• Why is a clock signal essential in sequential circuits like counters?
• Why is it important to connect the VCC and GND pins correctly?
8.8 Post-Experimentation Questions
• How could the circuit be expanded or modified for different applications?

• How did you ensure stable logic levels throughout the experiment?

EXPERIMENT No.09: Realize the following shift registers using IC7474

(i) SISO (ii) SIPO (iii) PISO (iv) PIPO

9.5 Procedure
9.1 Objectives:
• To realize the following shift registers using IC 7474

(a) Serial in Serial Out (SISO)
(b) Serial in Parallel Out (SIPO)
(c) Parallel in Parallel Out (PIPO)
(d) Parallel in Serial Out (PISO)

Dual D Flip Flop IC IC 7474 1
Patch Cord - 1 set
9.3 Pre-Requisite: Operation of different shift registers, operation of different counters.
9.4 Introduction:
Registers are simply a group of flip flops that can be used to store a binary number. A shift
register is nothing but a register which can accept binary number and shift it. The data can be
entered in the shift register either in serial or in parallel. The output can be taken either in serial
or in parallel. Since there are two ways to shift data in to a register and two ways to shiftdata
out of the register four types of registers can be constructed. A register capable of shiftingits
binary information either to the left or to the right is called a shift register. The

logical configuration of a shift register consists of a chain of flip flops connected in cascade with the
output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common
clock pulse which causes the shift from one stage to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse
shifts the contents of the register one-bit position to the right. The serial input determines, what goes
into the right most flip flop during the shift. The serial output is taken from the output of the left most
flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we
turn the page upside down, we find that the register shifts its contents to the right. Thus, a
unidirectional shift register can function either as a shift right or a shift left register.
The binary information (data) in a register can be moved within or into or out of the register upon
application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic
and logic operations used in microprocessors. This gives rise to group of registers called shift
registers. They are very important in applications involving the storage and transfer of data in a
digital system.
TYPES OF SHIFT REGISTERS:
Serial in Serial out (SISO):

In this type of register, the output of one flip-flop is connected to the input of the next flip flop. Output
of the register is obtained from the last flip-flop. Depending on the direction of the input given shifting
takes place in this. Bit by bit loading is done with every clock pulse and shifting takesplace with every
clock pulse.
Serial in Parallel out [SIPO]:
This is similar to SISO except that the output is taken from each flip-flop. Thereby the shifted value
is shown at once.
Parallel in Parallel out [PIPO]:
Upon giving clock pulse, data is loaded in parallel in all flip-flops. Output is taken from each of the
flip-flop.
Parallel in Serial out [PISO]:
Here we use a control input Load/ (Shift) such that if Load/ (Shift) = 1, data is loaded in all flip-flops
in parallel and when the Load/ (Shift) = 0, data is shifted with every clock pulse. Output is obtained
from the last flip-flop.

9.5 Procedure:
2. Insert the appropriate IC into the IC base.
3. Do the connection as shown in the Logic Diagram.
4. Give the supply to the trainer kit.
5. Verify the Truth Table & Observe the output for corresponding combination.
9.6 Observations:
PIN DIAGRAM OF IC 7474:
FUNCTION TABLE FOR IC 7474:
Inputs Outputs
Preset Clear Clock D Q Q‟
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 1 0 0 1
1 1 1 1 1 0
1 1 0 X No change No change

LOGIC DIAGRAM:
a. Serial in Serial Out:
Observation Table
Input Clock Outputs

(SI) Pulse Q0 Q1 Q2 Q3
0 0 - - -
1 1 0 - -
1 1 1 0 -
0 0 1 1 0
1 1 0 1 1
0 0 1 0 1
b. Serial in Parallel Out

Observation Table
Input Clock Outputs

(SI) Pulse Q0 Q1 Q2 Q3
0 0 - - -
1 1 0 - -
1 1 1 0 -
0 0 1 1 0
1 1 0 1 1
0 0 1 0 1
c.Parallel In Parallel Out:
Observation Table:
Clock Inputs Outputs

pulse D0 D1 D2 D3 Q0 Q1 Q2 Q3
0 1 0 1 0 1 0 1
1 1 1 0 1 1 1 0
1 0 1 0 1 0 1 0
0 1 1 0 0 1 1 0

d.Parallel in Serial Out:
TRUTH TABLE:
CLK Load/Shift QA QB QC QD
1 0 1 0 1 0
2 1 X 1 0 1
3 1 X X 1 0
4 1 X X X 1
5 1 X X X X
9.7 Results:
• All shift registers have designed and verified using the specified IC.
• What is shift register?
• What are counters?
• Why is an asynchronous counter called as a ripple counter?
• Define modulus of a counter.
• What type of counter is 7490?


• Explain the operation of different shift registers.
• Explain the operation of counters.
• What are the applications of shift registers?
• What are the applications of counters?
• What is the difference between a counter and a register?
• What is the difference between a synchronous counter and asynchronous counter?
• What type of flip flop is used to design a asynchronous counter?

EXPERIMENT No.10: Realize

i. Ring Counter using IC7476
ii. Jhonson counter using IC7476

10.1 AIM:
To design and set up four-bit Johnson and ring counter using JK FF
10.2 COMPONENTS REQUIRED:

Digital IC trainer kit, IC 7476
10.3 THEORY:
Ring counter:
A ring counter is a type of digital counter circuit that forms a closed-loop or ring structure. In
a ring counter, the output of one flip-flop is connected to the input of the next flip-flop,
forming a circular arrangement. The counter progresses through its states by shifting a '1' bit,
or high signal, around the ring. It's also known as a shift register counter.
Johnson counter:
A Johnson counter, also known as a "twisted ring counter" or "walking ring counter," is a type of
digital counter circuit that provides a 2^n state sequence, where 'n' is the number of flip-flops in
the circuit. The Johnson counter is a modification of the traditional ring counter, and it uses
complemented outputs to achieve the expanded state sequence.
10.4 PROCEDURE:
a) Ring counter:
• Connect the circuit as shown in the circuit diagram

• To circulate logical ‘1’, set
Mode control=1
Apply data 0001 at the parallel inputs and a clock pulse at CLK-2.

Make the mode control=0 and apply the clock pulse to CLK-1.
• Observe the outputs on the CRO and verify the truth table.
b) Johnson counter:
• Make the connections as shown in the circuit diagram.

• Start with all zeroes in the truth table.
• Observe the count sequence.
10.5 Observations
Ring counter:
Truth Table
Clock QA QB QC QD
pulse
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 1

Johnson counter:
Truth Table
Clock QA QB QC QD
pulse
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 0

Wave Form
10.6 Results:
• Operation of ring and Johnson counter is realized and verified using the specified IC.
• What are counters?
• Why is an asynchronous counter called as a ripple counter?
• Define modulus of a counter.
• What type of counter is 7490?
• Is the output of a counter always a square wave?


• Explain the operation of counters.
• What are the applications of shift registers?
• What are the applications of counters?
• What is the difference between a counter and a register?
• What is the difference between a synchronous counter and asynchronous counter?
• What type of flip flop is used to design an asynchronous counter?

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ANALYSIS AND DESIGN OF DIGITAL

Insert any equipment/lab related pictures

DEPARTMENT OF ELECTRONICS & COMMUNICATION

NAME OF THE FACULTY

NAME OF THE INSTRUCTOR

MAXIMUM MARKS MARKS OBTAINED

DEPARTMENT OF ELECTRONICS & COMMUNICATION

M2: Develop skill-based learning through industry-institution interaction to enhance

DEPARTMENT OF ELECTRONICS & COMMUNICATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION

Assessment Components (ACs)

DEPARTMENT OF ELECTRONICS & COMMUNICATION

Simplification, realization of Boolean expressions using logic Gates/

Analyze the difference in design and functionality between a Half

5 Design of Multiplexer using IC 74153 33-38

Utilizing the IC7485, demonstrate the circuit connections and

Verify the truth table of flip-flops

Demonstrate the circuit connections and configuration required to

Realize the following shift registers using IC7474

DEPARTMENT OF ELECTRONICS & COMMUNICATION

PSO1: Exhibit competency in IoT and Embedded systems

DEPARTMENT OF ELECTRONICS & COMMUNICATION

EXPERIMENT No.01: Simplification, realization of Boolean

1.1Objectives 1.6 Observations

1.2 Apparatus Required:

Component Specification Qty

1.3 Pre-Requisite: basic gate

Department of Electronics and Communication Engineering, SCEM, Mangaluru 1

2.Insert the appropriate IC into the IC base.

3.Do the connection as shown in the Logic Diagram.

4.Give the supply to the trainer kit.

Department of Electronics and Communication Engineering, SCEM, Mangaluru 2

Implementation of Logic Gates

1. NOT Gate: - [IC7404] Truth Table

I/P (A) O/P (𝑨)

Department of Electronics and Communication Engineering, SCEM, Mangaluru 3

3. AND GATE: - [IC7408]

4. NAND GATE: - [IC 7400] Truth Table

Department of Electronics and Communication Engineering, SCEM, 4

5. NOR GATE: [IC 7402]

6. XOR GATE: - [IC 7486]

7. EX-NOR GATE: - [IC4077]

Department of Electronics and Communication Engineering, SCEM, 5

Implementation of Basic Gates Using Universal Gates

(a) AND GATE A B Y

(c) NOT GATE

I/P (A) O/P (𝑨)

(d) NOR GATE

Department of Electronics and Communication Engineering, SCEM, Mangalore 6

(e) EX-OR GATE

(f) EX-NOR GATE

Department of Electronics and Communication Engineering, SCEM, Mangalore 7

(c) NOT GATE

I/P (A) O/P (𝑨)

(d) NAND GATE

(e) EX-OR GATE

Department of Electronics and Communication Engineering, SCEM, Mangalore 8

(f) EX-NOR GATE

• Truth Table is verified.