74LS258
74LS258
74LS258
The MC74F258A is a quad 2-input multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common Data Select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems. Multiplexer Expansion by Tying Outputs Together Inverting 3-State Outputs AC Enhanced Version of the F258 CONNECTION DIAGRAM (TOP VIEW)
VCC 16 OE 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9
16
MC74F258A
1 S
2 I0a
3 I1a
4 Za
5 I0b
6 I1b
7 Zb
8 GND
16 1
LOGIC DIAGRAM
OE I0a I1a I0b I1b I0C I1C I0D I1C S
16 1
ORDERING INFORMATION
MC54FXXXAJ Ceramic MC74FXXXAN Plastic MC74FXXXAD SOIC
LOGIC SYMBOL
1
MC74F258A
FUNCTION TABLE
Output Enable OE H L L L L
H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High Impedance
Select Input S X H H L L I0 X X X L H
Data Inputs I1 X L H X X
Output Z Z H L H L
Min 2.0
Typ
Max
Unit V
Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = 18 mA IOH = 3.0 mA VCC = MIN VCC = 4.75 V VCC = MIN VCC = MIN VCC = MAX VCC = MAX VCC = MAX
V V V
VCC = MAX
MC74F258A
AC CHARACTERISTICS
74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay In to Zn Propagation Delay S to Zn Output Enable Time Parameter Min 2.5 1.0 3.0 2.5 2.0 2.5 2.0 1.5 Max 5.3 4.0 7.5 7.0 6.0 7.0 6.0 6.0 74F TA = 0C to 70C VCC = 5.0 V 10% CL = 50 pF Min 2.0 1.0 3.0 2.5 2.0 2.5 2.0 1.5 Max 6.0 5.0 8.5 8.0 7.0 8.0 7.0 7.0 ns ns ns Unit ns
FUNCTIONAL DESCRIPTION
The F258A is a quad 2-input multiplexer with 3-state outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in inverted form. The F258A is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Za = OE (I1a S + I0a S) Zb = OE (I1b S + I0b S) Zc = OE (I1c S + I0c S) Zd = OE (I1d S + I0d S) When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap.