7 Practical Operational Amplifier (White Box)

Operational Amplifier
(What’s Inside?)
UNIVERSITY OF SCIENCE AND TECHNOLOGY OF SOUTHERN PHILIPPINES - CDO ECE223 Engr. Villaruz
LM741 Op Amp Internal Circuit
Bias Circuit and Input Stage
Gain Stage
Output Stage
Prone to burnout if vo is grounded.
Output Stage with Short-Circuit Protection
R6 limits emitter current of Q14. If

VR6 is high, Q15 turns on, shunting
base current of Q14 which limites
collector current.
R7 limits emitter current of Q20. If

VR7 is high, Q21 turns on, shunting
excessive current through Q21 and
Q24 away from Q20.
Input Common-Mode Range (ICMR)
Input Common-Mode Range (ICMR) - range of input CM level for normal operation (BJT - active)
Transistors in the input differential pair must be correctly biased (active region for BJT).
vCM_max is limited by Q5 and Q7
note: for active mode PNP,

VEB ≥ 0.7 for silicon
VCB < 0 (BC is reverse biased)
then,
vCM_max = V+ - 2VEB(on)
Input Common-Mode Range (ICMR) - range of input CM level for normal operation (BJT - active)
Transistors in the input differential pair must be correctly biased (active region for BJT).
vCM_min is limited by Q3
note: for active mode NPN,

VBE ≥ 0.7 for silicon
VBC < 0 (BC is reverse biased)
then,
vCM_min = V- + 2VBE(on)
Example: An Op-Amp below is biased with +15 and -15 V supply. What is the ICMR?
Output Voltage Limitation
Range of output voltage swing for normal operation (output BJT’s are in active mode)
vo_max is limited by Q8 and Q11


then,
vo_max = V+ - (VEB8(on) + VBE11(on))
Output Voltage Limitation
Range of output voltage swing for normal operation (output BJT’s are in active mode)
vo_min is limited by Q10 and Q12


then,
vo_min = V- + (VBE4(on) + VEB12(on))
Non-Ideality Considerations
Finite input impedance, nonzero output impedance, and finite open-loop gain.
R2
R1
v1 _
vi ro
rd vo 1
+ R1
v2 + _ AOL(v2 – v1) ACL 
 1 1  1 1 1 
     
 R 2 Ro  R1 rd R2   1
1 AOL R2

R2 Ro
Example: An inverting amplifier employs an op-amp with an open-loop gain of, A OL = 200,000.
Input impedance is 2MΩ and output impedance is 75Ω. The ideal closed-loop gain of the amplifier
has to be -40.
a. What is the actual closed-loop gain?
b. The op-amp is replaced with the one with AOL = 50,000. What is now the actual closed-loop
gain?
Homework: A pressure transducer produces a maximum dc voltage signal of 2 mV and has an
output resistance of RS = 2 kΩ. The maximum DC current from the transducer is to be limited to
0.2μA. An inverting amplifier is to be used in conjunction with the transducer in order to produce
an output voltage of -0.1 V for a 2-mV transducer signal. The error in the output voltage cannot be
greater than 0.1%. Input impedance is 2MΩ and output impedance is 75Ω. How much is the
minimum open-loop gain of the amplifier to meet this requirement?
Homework: Calculate the voltage gain for the amplifier below with non-ideal gain and impedances.
What will be the closed-loop input resistance, Rif, considering non-idealities?
Homework: Calculate the input resistance, Rif of the non-inverting amplifier below.
Effect of Non-Zero Output Resistance
Ideally, output resistance of op-amp is zero. Meaning, the output voltage is independent of the load
and there is no loading effect.
Effect of Non-Zero Output Resistance
Example: An op-amp with an open-loop gain of AOL = 105 is used in a non-inverting amplifier
configuration with a closed-loop gain of ACL = 100. Determine the closed-loop output resistance Rof
for Ro = 100 Ω and Ro = 10 kΩ.
Offset Voltage
Output DC offset voltage: the measured open-loop output voltage when both the input voltages is
zero.
Input DC offset voltage: input differential voltage that must be applied to the open-loop op amp in
order to produce a zero output voltage.
LM741 Electrical Characteristics
Offset Voltage
Cause of Offset Voltage:
Transistor Mismatch:
vo can only be zero iff vBE1 = vBE2 and
RCiC1 =RCiC2. This is not always the case in
reality.
Causes of Mismatch:
1. Resistor Mismatch
2. Transistor Mismatch
Offset Voltage
 vVBE 1 
iC1 
 I S1 e T
 1
 
 
 vVBE 2 
iC 2 
 IS2 e T
 1
 
 
v1 Vo1
We define vos = v1 - v2 as the necessary voltage to produce +
+
Vos _ DA vo = 0
a zero voltage. _
v2 Vo2
vos  v1  v2
vos  vBE 1  vBE 2
Offset Voltage
For zero output voltage
with matched resistors,
iC1 =iC2
 vVBE 1   vVBE 2 
I S1  e T
 1  I S 2  e T
 1
   
   
v BE 1 v BE 1
VT VT v BE 1  v BE 2
IS2 e 1 e VT
 vBE 2  vBE 2  e
I S1
e VT  1 e VT
Vo s
IS2 I  If transistors are matched,
 e VT Vos  VT ln  S 2  reverse saturation currents
I S1
 I S1  are equal. Vos = 0.
Offset Voltage
Example: Calculate the offset voltage in a differential amplifier shown below if I S1 = 100 fA and
IS2 = 10.5 fA?
Offset Voltage
Example: For a differential amplifier shown, the offset voltage is 2 mV. What is the percent
difference of IS1 and IS2 if IS1 = 2 fA?
Offset Voltage Compensation
Method 1: External offset Compensation network
Offset voltage, VOS is taken from the

voltage divider network of
potentiometer R3. This is further voltage
divided using R5 and R4. if VOS is in the
millivolt range, R5 << R4.
Sample Problem: Consider the compensation network below. If the rails are 10V and -10V, R 3 =
R4= 100kΩ, how much is R5 in order to compensate for an offset voltage of 5 mV? Assume
potentiometer rating is 100kΩ.
Method 2: Dedicated Offset-Null Terminals
A pair of offset-null terminals are

included in many op-amp IC’s.
Wiper arm of RX can be adjusted to

compensate for the offset voltage
introduced by the assymetry of
resistances.
Compensation Method:
With feedback of any type, set input
differential voltage to zero. Wiper arm
of RX is adjusted until the output voltage
is zero.
A pair of offset-null terminals are

included in many op-amp IC’s. R1  R1 || xRx R2  R2 || (1  x) Rx
Wiper arm of RX can be adjusted to

compensate for the offset voltage vBE 3  iC1 R1  vBE 4  iC 2 R2
introduced by the assymetry of
resistances.
Compensation Method:
With feedback of any type, set input
differential voltage to zero. Wiper arm
of RX is adjusted until the output voltage
is zero.
5 k
VCC
5 k
_
vo
5
+ 1
VEE

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Operational Amplifier

Prone to burnout if vo is grounded.

R6 limits emitter current of Q14. If

R7 limits emitter current of Q20. If

vCM_max is limited by Q5 and Q7

note: for active mode PNP,

note: for active mode NPN,

vo_max is limited by Q8 and Q11

note: for active mode PNP,

note: for active mode NPN,

vo_min is limited by Q10 and Q12

note: for active mode PNP,

note: for active mode NPN,

Offset voltage, VOS is taken from the

A pair of offset-null terminals are

Wiper arm of RX can be adjusted to

A pair of offset-null terminals are

Wiper arm of RX can be adjusted to

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