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2020 – today
- 2022
[j64]Leonid Yavits
, Roman Kaplan, Ran Ginosar:
GIRAF: General Purpose In-Storage Resistive Associative Framework. IEEE Trans. Parallel Distributed Syst. 33(2): 276-287 (2022)- 2021
- [j63]Leonid Azriel, Julian Speith, Nils Albartus, Ran Ginosar, Avi Mendelson, Christof Paar:
A survey of algorithmic methods in IC reverse engineering. J. Cryptogr. Eng. 11(3): 299-315 (2021) - [i17]Leonid Azriel, Julian Speith, Nils Albartus, Ran Ginosar, Avi Mendelson, Christof Paar:
A survey of algorithmic methods in IC reverse engineering. IACR Cryptol. ePrint Arch. 2021: 1278 (2021) - 2020
- [c74]Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu:
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. ICCD 2020: 187-196 - [c73]Roman Kaplan, Leonid Yavits, Ran Ginosar:
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. SYSTOR 2020: 36-48 - [i16]Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu:
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. CoRR abs/2010.02825 (2020)
2010 – 2019
- 2019
- [j62]Roman Kaplan, Leonid Yavits, Ran Ginosar:
RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. IEEE Micro 39(4): 44-54 (2019) - [j61]Misbah Ramadan, Nicolás Wainstein, Ran Ginosar, Shahar Kvatinsky:
Adaptive programming in multi-level cell ReRAM. Microelectron. J. 90: 169-180 (2019) - [c72]Roman Kaplan, Leonid Yavits, Ran Ginosar:
POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. PACT 2019: 459-460 - [c71]Leonid Yavits, Roman Kaplan, Ran Ginosar:
POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. PACT 2019: 477-478 - [c70]Leonid Azriel, Ran Ginosar, Avi Mendelson:
SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. ASHES@CCS 2019: 65-74 - [i15]Leonid Yavits, Roman Kaplan, Ran Ginosar:
AIDA: Associative DNN Inference Accelerator. CoRR abs/1901.04976 (2019) - [i14]Roman Kaplan, Leonid Yavits, Ran Ginosar:
BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. CoRR abs/1901.05959 (2019) - 2018
- [j60]Leonid Yavits, Ran Ginosar:
Accelerator for Sparse Machine Learning. IEEE Comput. Archit. Lett. 17(1): 21-24 (2018) - [j59]Leonid Yavits, Roman Kaplan, Ran Ginosar:
Enabling Full Associativity with Memristive Address Decoder. IEEE Micro 38(5): 32-40 (2018) - [i13]Leonid Yavits, Roman Kaplan, Ran Ginosar:
PRINS: Resistive CAM Processing in Storage. CoRR abs/1805.09612 (2018) - [i12]Roman Kaplan, Leonid Yavits, Ran Ginosar:
RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. CoRR abs/1809.01127 (2018) - 2017
- [j58]Leonid Yavits, Uri C. Weiser, Ran Ginosar:
Resistive Address Decoder. IEEE Comput. Archit. Lett. 16(2): 141-144 (2017) - [j57]Y. Zhang, Rostislav (Reuven) Dobkin, Aharon Unikovski, Danniel Nahmanny, Goel Samuel, Michael Moyal, Ran Ginosar:
A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. Integr. 59: 190-197 (2017) - [j56]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro 37(4): 20-28 (2017) - [j55]Roman Kaplan, Leonid Yavits, Ran Ginosar:
From Processing-in-Memory to Processing-in-Storage. Supercomput. Front. Innov. 4(3): 99-116 (2017) - [j54]Leonid Azriel, Ran Ginosar, Shay Gueron, Avi Mendelson:
Using Scan Side Channel to Detect IP Theft. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3268-3280 (2017) - [c69]Leonid Azriel, Ran Ginosar, Avi Mendelson:
Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering. ACM Great Lakes Symposium on VLSI 2017: 233-238 - [i11]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR abs/1701.04723 (2017) - [i10]Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar:
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR abs/1705.06923 (2017) - [i9]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Temperature on Amdahl Law in 3D Multicore Era. CoRR abs/1705.07280 (2017) - [i8]Leonid Yavits, Amir Morad, Ran Ginosar:
Cache Hierarchy Optimization. CoRR abs/1705.07281 (2017) - [i7]Leonid Yavits, Amir Morad, Ran Ginosar:
Sparse Matrix Multiplication On An Associative Processor. CoRR abs/1705.07282 (2017) - [i6]Leonid Yavits, Ran Ginosar:
Sparse Matrix Multiplication on CAM Based Accelerator. CoRR abs/1705.09937 (2017) - 2016
- [j53]Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann, Yoni Aizik:
H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer 49(10): 47-55 (2016) - [j52]Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar:
Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. 12(4): 57:1-57:22 (2016) - [j51]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Temperature on Amdahl Law in 3D Multicore Era. IEEE Trans. Computers 65(6): 2010-2013 (2016) - [c68]Leonid Azriel, Ran Ginosar, Shay Gueron, Avi Mendelson:
Using Scan Side Channel for Detecting IP Theft. HASP@ISCA 2016: 1:1-1:8 - [c67]Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar:
Deduplication in resistive content addressable memory based solid state drive. PATMOS 2016: 100-106 - [i5]Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser:
Convex Optimization of Real Time SoC. CoRR abs/1601.07815 (2016) - [i4]Leonid Yavits, Amir Morad, Ran Ginosar:
Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. CoRR abs/1602.01329 (2016) - 2015
- [j50]Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar:
Resistive Associative Processor. IEEE Comput. Archit. Lett. 14(2): 148-151 (2015) - [j49]Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser:
Power and thermal constraints of modern system-on-a-chip computer. Microelectron. J. 46(12): 1225-1229 (2015) - [j48]Leonid Yavits, Amir Morad, Ran Ginosar:
Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Computers 64(2): 368-381 (2015) - [j47]Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno:
SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2238-2247 (2015) - [j46]Leonid Yavits, Amir Morad, Ran Ginosar:
Sparse Matrix Multiplication On An Associative Processor. IEEE Trans. Parallel Distributed Syst. 26(11): 3175-3183 (2015) - [j45]Salomon Beer, Ran Ginosar:
Eleven Ways to Boost Your Synchronizer. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1040-1049 (2015) - [j44]Salomon Beer, Ran Ginosar:
A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2461-2472 (2015) - [j43]Salomon Beer, Jerome Cox, Ran Ginosar, Tom Chaney, David M. Zar:
Variability in Multistage Synchronizers. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2957-2969 (2015) - [c66]Ron Diamant, Ran Ginosar, Christos P. Sotiriou:
Asynchronous sub-threshold ultra-low power processor. PATMOS 2015: 89-96 - 2014
- [j42]Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson:
Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. IEEE Comput. Archit. Lett. 13(1): 25-28 (2014) - [j41]Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. 13(1): 37-40 (2014) - [j40]Leonid Yavits, Amir Morad, Ran Ginosar:
Cache Hierarchy Optimization. IEEE Comput. Archit. Lett. 13(2): 69-72 (2014) - [j39]Dmitry Verbitsky, Rostislav (Reuven) Dobkin, Ran Ginosar, Salomon Beer:
StarSync: An extendable standard-cell mesochronous synchronizer. Integr. 47(2): 250-260 (2014) - [j38]Leonid Yavits, Amir Morad, Ran Ginosar:
The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Comput. 40(1): 1-16 (2014) - [j37]Jawad Haj-Yihia, Yosi Ben-Asher, Efraim Rotem, Ahmad Yasin, Ran Ginosar:
Compiler-Directed Power Management for Superscalars. ACM Trans. Archit. Code Optim. 11(4): 48:1-48:21 (2014) - [j36]Amir Morad, Leonid Yavits, Ran Ginosar:
GP-SIMD Processing-in-Memory. ACM Trans. Archit. Code Optim. 11(4): 53:1-53:26 (2014) - [j35]Ran Ginosar, Karam S. Chatha:
Guest Editors' Introduction - Special Issue on Network-on-Chip. IEEE Trans. Computers 63(3): 527-528 (2014) - [c65]Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, Luciano Lavagno:
Metastability in Better-Than-Worst-Case Designs. ASYNC 2014: 101-102 - [c64]Itai Avron, Ran Ginosar:
Hardware Scheduler Performance on the Plural Many-Core Architecture. MES@ISCA 2014: 48-51 - [c63]Amir Morad, Leonid Yavits, Ran Ginosar:
Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. PATMOS 2014: 1-8 - [c62]Amir Morad, Leonid Yavits, Ran Ginosar:
Convex optimization of resource allocation in asymmetric and heterogeneous SoC. PATMOS 2014: 1-8 - [c61]Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar:
Energy management of highly dynamic server workloads in an heterogeneous data center. PATMOS 2014: 1-5 - 2013
- [j34]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. 46(4): 382-391 (2013) - [c60]Leonid Yavits, Amir Morad, Ran Ginosar:
3D cache hierarchy optimization. 3DIC 2013: 1-5 - [c59]Salomon Beer, Ran Ginosar, Rostislav (Reuven) Dobkin, Yoav Weizman:
MTBF Estimation in Coherent Clock Domains. ASYNC 2013: 166-173 - [c58]Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar:
Metastability challenges for 65nm and beyond: simulation and measurements. DATE 2013: 1297-1302 - [c57]Eyal-Itzhak Nave, Ran Ginosar:
PBD: packet buffer DVFs. ACM Great Lakes Symposium on VLSI 2013: 319-320 - [i3]Leonid Yavits, Amir Morad, Ran Ginosar:
The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. CoRR abs/1306.3302 (2013) - [i2]Leonid Yavits, Amir Morad, Ran Ginosar:
Thermal analysis of 3D associative processor. CoRR abs/1307.3853 (2013) - [i1]Leonid Yavits, Amir Morad, Ran Ginosar:
3D Cache Hierarchy Optimization. CoRR abs/1311.1667 (2013) - 2012
- [c56]Itai Avron, Ran Ginosar:
Performance of a Hardware Scheduler for Many-core Architecture. HPCC-ICESS 2012: 151-160 - [c55]Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Energy metrics for power efficient crosslink and mesh topologies. ISCAS 2012: 1656-1659 - [c54]Salomon Beer, Ran Ginosar:
An Extended Metastability Simulation Method for Synchronizer Characterization. PATMOS 2012: 42-51 - [c53]Eyal-Itzhak Nave, Ran Ginosar:
TCP Window Based DVFS for Low Power Network Controller SoC. PATMOS 2012: 83-92 - 2011
- [j33]Ran Ginosar:
Metastability and Synchronizers: A Tutorial. IEEE Des. Test Comput. 28(5): 23-35 (2011) - [j32]Dmitri Vainbrand, Ran Ginosar:
Scalable network-on-chip architecture for configurable neural networks. Microprocess. Microsystems 35(2): 152-166 (2011) - [c52]Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny:
An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS 2011: 2593-2596 - [e1]Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha:
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011. ACM/IEEE Computer Society 2011, ISBN 978-1-4503-0720-8 [contents] - 2010
- [j31]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 689-696 (2010) - [j30]Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar:
Asynchronous Current Mode Serial Communication. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1107-1117 (2010) - [j29]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1262 (2010) - [c51]Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny:
The Devolution of Synchronizers. ASYNC 2010: 94-103 - [c50]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20 - [c49]Dmitri Vainbrand, Ran Ginosar:
Network-on-Chip Architectures for Neural Networks. NOCS 2010: 135-144 - [c48]Amit Berman, Ran Ginosar, Idit Keidar:
Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. VLSI-SoC 2010: 37-42
2000 – 2009
- 2009
- [j28]Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
QNoC asynchronous router. Integr. 42(2): 103-115 (2009) - [j27]Rostislav (Reuven) Dobkin, Ran Ginosar:
Two-phase synchronization with sub-cycle latency. Integr. 42(3): 367-375 (2009) - [c47]Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290 - [c46]Asaf Baron, Ran Ginosar, Isaac Keslassy:
The Capacity Allocation Paradox. INFOCOM 2009: 1359-1367 - [c45]Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser:
Multiple clock and voltage domains for chip multi processors. MICRO 2009: 459-468 - 2008
- [j26]A. Elyada, Ran Ginosar, Uri C. Weiser:
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1243-1248 (2008) - [c44]Rostislav (Reuven) Dobkin, Ran Ginosar:
Fast Universal Synchronizers. PATMOS 2008: 199-208 - [c43]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Timing optimization in logic with interconnect. SLIP 2008: 19-26 - [c42]Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar:
Parallel vs. serial on-chip communication. SLIP 2008: 43-50 - 2007
- [j25]Yevgeny Perelman, Ran Ginosar:
An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection. IEEE Trans. Biomed. Eng. 54(1): 130-137 (2007) - [j24]Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes:
Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. IEEE Trans. Neural Networks 18(2): 542-550 (2007) - [j23]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: 90941:1-90941:15 (2007) - [c41]Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny:
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14 - [c40]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947 - [c39]Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126 - [c38]Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148 - [c37]Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon:
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. NOCS 2007: 218 - 2006
- [j22]Uri Frank, Tsachy Kapschitz, Ran Ginosar:
A predictive synchronizer for periodic clock domains. Formal Methods Syst. Des. 28(2): 171-186 (2006) - [j21]Yevgeny Perelman, Ran Ginosar:
A low-power inverted ladder D/a converter. IEEE Trans. Circuits Syst. II Express Briefs 53-II(6): 497-501 (2006) - [j20]Ilya Obridko, Ran Ginosar:
Minimal Energy Asynchronous Dynamic Adders. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 1043-1047 (2006) - [j19]Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
High Rate Data Synchronization in GALS SoCs. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1063-1074 (2006) - [c36]Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny:
Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127 - [c35]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14 - 2005
- [j18]Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar:
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 427-438 (2005) - [c34]Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar:
An Asynchronous Router for Multiple Service Levels Networks on Chip. ASYNC 2005: 44-53 - [c33]Tsachy Kapschitz, Ran Ginosar:
Formal Verification of Synchronizers. CHARME 2005: 359-362 - [c32]Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603 - [c31]Ilya Obridko, Ran Ginosar:
Low energy asynchronous architectures. ISCAS (5) 2005: 5238-5241 - 2004
- [j17]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Cost considerations in network on chip. Integr. 38(1): 19-42 (2004) - [j16]Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50(2-3): 105-128 (2004) - [j15]Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 847-856 (2004) - [c30]Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
Data Synchronization Issues in GALS SoCs. ASYNC 2004: 170-180 - [c29]Alex Branover, Rakefet Kol, Ran Ginosar:
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE 2004: 870-877 - [c28]Ilya Obridko, Ran Ginosar:
Low energy asynchronous adders. ICECS 2004: 164-167 - [c27]Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Automatic hardware-efficient SoC integration by QoS network on chip. ICECS 2004: 479-482 - [c26]Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Micro-modem - reliability solution for NoC communications. ICECS 2004: 483-486 - [c25]Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Comparative analysis of serial vs parallel links in NoC. SoC 2004: 185-188 - [c24]Uri Frank, Ran Ginosar:
A Predictive Synchronizer for Periodic Clock Domains. PATMOS 2004: 402-412 - 2003
- [j14]Ken S. Stevens, Ran Ginosar, Shai Rotem:
Relative timing [asynchronous design]. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 129-140 (2003) - [j13]Y. Elboim, Avinoam Kolodny, Ran Ginosar:
A clock-tuning circuit for system-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 616-626 (2003) - [c23]Yaron Semiat, Ran Ginosar:
Timing Measurements of Synchronization Circuits. ASYNC 2003: 68-77 - [c22]Ran Ginosar:
Fourteen Ways to Fool Your Synchronizer. ASYNC 2003: 89-97 - 2002
- [c21]Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar:
Parallel VLSI architecture for MAP turbo decoder. PIMRC 2002: 384-388 - 2001
- [j12]Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. IEEE J. Solid State Circuits 36(2): 217-228 (2001) - [j11]Yevgeny Perelman, Ran Ginosar:
A low-light-level sensor for medical diagnostic applications. IEEE J. Solid State Circuits 36(10): 1553-1558 (2001)
1990 – 1999
- 1999
- [c20]Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70 - [c19]Ken S. Stevens, Shai Rotem, Ran Ginosar:
Relative Timing. ASYNC 1999: 208-218 - [c18]Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken:
CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121 - 1998
- [j10]Stuart G. Wolf, Ran Ginosar, Yehoshua Y. Zeevi:
Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing. J. Vis. Commun. Image Represent. 9(1): 25-37 (1998) - [c17]Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80- - [c16]Ran Ginosar, Rakefet Kol:
Adaptive synchronization. ICCD 1998: 188-189 - [c15]Rakefet Kol, Ran Ginosar:
Kin: A High Performance Asynchronous Processor Architecture. International Conference on Supercomputing 1998: 433-440 - [c14]Uzi Zangi, Ran Ginosar:
A low power video processor. ISLPED 1998: 136-138 - 1997
- [c13]Rakefet Kol, Ran Ginosar:
A Double-Latched Asynchronous Pipeline. ICCD 1997: 706-712 - 1996
- [c12]Rakefet Kol, Ran Ginosar, Goel Samuel:
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. ASYNC 1996: 164-174 - 1995
- [j9]Ilana David, Ran Ginosar, Michael Yoeli:
Self-timed is self-checking. J. Electron. Test. 6(2): 219-228 (1995) - 1994
- [c11]Sarit Chen, Ran Ginosar:
Adaptive sensitivity CCD image sensor. ICPR (3) 1994: 363-365 - [c10]Stuart G. Wolf, Ran Ginosar, Yehoshua Y. Zeevi:
Spatio-chromatic model for colour image processing. ICPR (1) 1994: 599-601 - 1993
- [j8]Alan Rotman, Ran Ginosar:
Control unit synthesis from a high-level language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 162-167 (1993) - [c9]Ilana David, Ran Ginosar, Michael Yoeli:
Self-Timed Architecture of a Reduced Instruction Set Computer. Asynchronous Design Methodologies 1993: 29-43 - 1992
- [j7]Ilana David, Ran Ginosar, Michael Yoeli:
An Efficient Implementation of Boolean Functions as Self-Timed Circuits. IEEE Trans. Computers 41(1): 2-11 (1992) - [j6]Ilana David, Ran Ginosar, Michael Yoeli:
Implementing Sequential Machines as Self-Timed Circuits. IEEE Trans. Computers 41(1): 12-17 (1992) - 1991
- [c8]Arie Harsat, Ran Ginosar:
CARMEL-4: The Unify-Spawn Machine for FCP. ICLP 1991: 840-854 - 1990
- [j5]Arie Harsat, Ran Ginosar:
CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. New Gener. Comput. 7(2-3): 197-218 (1990) - [j4]Ran Ginosar, Nick Michell:
On the potential of asynchronous pipelined processors. SIGARCH Comput. Archit. News 18(4): 27-34 (1990) - [c7]Arie Harsat, Ran Ginosar:
An Extended RISC Methodology and its Application to FCP. ICLP 1990: 67-82 - [c6]Yehoshua Y. Zeevi, Ran Ginosar:
Foveating vision systems architecture: image acquisition and display. VCIP 1990
1980 – 1989
- 1989
- [j3]Ran Ginosar, David Egozi:
Topological comparison of perfect shuffle and hypercube. Int. J. Parallel Program. 18(1): 37-68 (1989) - [j2]Llana David, Ran Ginosar, Michael Yoeli:
An efficient implementation of Boolean functions nd finite state machine as self-timed circuit. SIGARCH Comput. Archit. News 17(6): 91-104 (1989) - 1988
- [c5]Arie Harsat, Ran Ginosar:
CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. FGCS 1988: 962-969 - 1985
- [c4]Ran Ginosar, Dwight D. Hill:
Design and Implementation of Switching Systems for Parallel Processors. ICPP 1985: 674-680 - 1983
- [c3]Bruce W. Arden, Ran Ginosar:
Performance evaluation of the MP/C. AFIPS National Computer Conference 1983: 539-555 - 1982
- [j1]Bruce W. Arden, Ran Ginosar:
MP/C: A Multiprocessor/Computer Architecture. IEEE Trans. Computers 31(5): 455-473 (1982) - 1981
- [c2]Bruce W. Arden, Ran Ginosar:
MP/C: A Multiprocessor/Computer Architecture. ISCA 1981: 3-20 - [c1]Bruce W. Arden, Ran Ginosar:
A Single-Relation Module for a Data Base Machine. ISCA 1981: 227-238
Coauthor Index
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