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Static analysis to mitigate soft errors in register files

Published: 20 April 2009 Publication History
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  • Abstract

    With continuous technology scaling, soft errors are becoming an increasingly important design concern even for earth-bound applications. While compiler approaches have the potential to mitigate the effect of soft errors with minimal runtime overheads, static vulnerability estimation---an essential part of compiler approaches---is lacking due to its inherent complexity. This paper presents a static analysis approach for Register File (RF) vulnerability estimation. We decompose the vulnerability of a register into intrinsic and conditional basic-block vulnerabilities. This decomposition allows us to develop a fast, yet reasonably accurate, linear equation-based RF vulnerability estimation mechanism. We demonstrate its practical application to compiler optimizations. Our experimental results on benchmarks from MiBench suite indicate that not only our static RF vulnerability estimation is fast and accurate, but also compiler optimizations enabled by our static estimation can achieve very cost-effective protection of register files against soft errors.

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    1. Static analysis to mitigate soft errors in register files

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      Published In

      cover image ACM Conferences
      DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe
      April 2009
      1776 pages
      ISBN:9783981080155

      Sponsors

      • EDAA: European Design Automation Association
      • ECSI
      • EDAC: Electronic Design Automation Consortium
      • SIGDA: ACM Special Interest Group on Design Automation
      • The IEEE Computer Society TTTC
      • The IEEE Computer Society DATC
      • The Russian Academy of Sciences: The Russian Academy of Sciences

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      European Design and Automation Association

      Leuven, Belgium

      Publication History

      Published: 20 April 2009

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      DATE '09
      Sponsor:
      • EDAA
      • EDAC
      • SIGDA
      • The Russian Academy of Sciences

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      Overall Acceptance Rate 518 of 1,794 submissions, 29%

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      • (2018)Bit Impact FactorMicroprocessors & Microsystems10.1016/j.micpro.2014.04.00938:6(598-604)Online publication date: 28-Dec-2018
      • (2014)ASACACM SIGPLAN Notices10.1145/2666357.259781249:5(95-104)Online publication date: 12-Jun-2014
      • (2014)ASACProceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2597809.2597812(95-104)Online publication date: 12-Jun-2014
      • (2014)Exploiting Narrow Data-Width to Mask Soft Errors in Register FilesProceedings of the 33rd International Conference on Computer Safety, Reliability, and Security - Volume 866610.1007/978-3-319-10506-2_9(125-138)Online publication date: 10-Sep-2014
      • (2010)Cache vulnerability equations for protecting data in embedded processor caches from soft errorsACM SIGPLAN Notices10.1145/1755951.175591045:4(143-152)Online publication date: 13-Apr-2010
      • (2010)Cache vulnerability equations for protecting data in embedded processor caches from soft errorsProceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems10.1145/1755888.1755910(143-152)Online publication date: 13-Apr-2010
      • (2009)A compiler optimization to reduce soft errors in register filesACM SIGPLAN Notices10.1145/1543136.154245944:7(41-49)Online publication date: 19-Jun-2009
      • (2009)A compiler optimization to reduce soft errors in register filesProceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1542452.1542459(41-49)Online publication date: 19-Jun-2009

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