Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
research-article

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

Published: 23 May 2017 Publication History

Abstract

Diagnosis of scan chain faults is important for yield learning and improvement. Procedures that generate tests for diagnosis of scan chain faults produce scan-based tests with one or more functional capture cycles between a scan-in and a scan-out operation. The approach to test generation referred to as transparent-scan has several advantages in this context. (1) It allows functional capture cycles and scan shift cycles to be interleaved arbitrarily. This increases the flexibility to assign to the scan cells values that are needed for diagnosis. (2) Test generation under transparent-scan considers a circuit model where the scan logic is included explicitly. Consequently, the test generation procedure takes into consideration the full effect of a scan chain fault. It thus produces accurate tests. (3) For the same reason, it can also target faults inside the scan logic. (4) Transparent-scan results in compact test sequences. Compaction is important because of the large volumes of fail data that scan chain faults create. The cost of transparent-scan is that it requires simulation procedures for sequential circuits, and that arbitrary sequences would be applicable to the scan select input. Motivated by the advantages of transparent-scan, and the importance of diagnosing scan chain faults, this article describes a procedure for generating transparent-scan sequences for diagnosis of scan chain faults. The procedure is also applied to produce transparent-scan sequences for diagnosis of faults inside the scan logic.

References

[1]
M. Abramovici, M. A. Breuer, and A. D. Friedman. 1995. Digital Systems Testing and Testable Design. IEEE Press.
[2]
M. Abramovici, C. Stroud, and M. Emmert. 2002. Using embedded FPGAs for SoC yield improvement. In Proceedings of the Design Automation Conference. ACM, 713--724.
[3]
R. Adapa, E. Flanigan, and S. Tragoudas. 2008. A novel test generation methodology for adaptive diagnosis. In Proceedings of the International Symposium on Quality Electronic Design. IEEE, 242--245.
[4]
P. Camurati, D. Medina, P. Prinetto, and M. Sonza Reorda. 1990. A diagnostic test pattern generation algorithm. In Proceedings of the International Test Conference. IEEE, 52--58.
[5]
Y.-H. Chen, C.-L. Chang, and C. H.-P. Wen. 2012. Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow. IET Computers 8 Digital Techniques 6, 3, 186--193.
[6]
M. Chen and A. Orailoglu. 2011. Diagnosing scan chain timing faults through statistical feature analysis of scan images. In Proceedings of the Design, Automation 8 Test in Europe Conference. IEEE, 1--6.
[7]
H. Chen, Z. Qi, L. Wang, and C. Xu. 2015. A scan chain optimization method for diagnosis. In Proceedings of the International Conference on Computer Design. IEEE, 613--620.
[8]
Z. Chen, S. Seth, D. Xiang, and B. B. Bhattacharya. 2011. Diagnosis of multiple scan-chain faults in the presence of system logic defects. In Proceedings of the Asian Test Symposium. IEEE, 297--302.
[9]
W. S. Chuang, S. T. Lin, W. C. Liu, and J. C. M. Li. 2008. Diagnosis of multiple scan chain timing faults. IEEE Transactions on Computer-Aided Design 27, 6 (June 2008), 1104--1116.
[10]
S. Chun and A. Orailoglu. 2010. DiSC: A new diagnosis method for multiple scan chain failures. IEEE Transactions on Computer-Aided Design 19, 12 (Dec. 2010), 2051--2055.
[11]
F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda. 1995. GARDA: A diagnostic ATPG for large synchronous sequential circuits. In Proceedings of the European Design 8 Test Conference. IEEE, 267--271.
[12]
T. Gruning, U. Mahlstedt, and H. Koopmeiners. 1991. DIATEST: A fast diagnostic test pattern generator for combinational circuits. In Proceedings of the International Conference on Computer-Aided Design. IEEE, 194--197.
[13]
R. Guo, W.-T. Cheng, T. Kobayashi, and K.-H. Tsai. 2010. Diagnostic test generation for small delay defect diagnosis. In Proceedings of the International Symposium on VLSI Design Automation and Test. IEEE, 224--227.
[14]
R. Guo, Y. Huang, and W.-T. Cheng. 2007. A complete test set to diagnose scan chain failures. In Proceedings of the International Test Conference. IEEE, 1--10.
[15]
R. Guo and S. Venkataraman. 2001. A technique for fault diagnosis of defects in scan chains. In Proceedings of the International Test Conference. IEEE, 268--277.
[16]
Y. Higami, Y. Kurose, S. Ohno, H. Yamaoka, H. Takahashi, Y. Shimizu, T. Aikyo, and Y. Takamatsu. 2009. Diagnostic test generation for transition faults using a stuck-at ATPG Tool. In Proceedings of the International Test Conference. IEEE, 1--9.
[17]
Y. Huang. 2007. Dynamic learning based scan chain diagnosis. In Proceedings of the Design, Automation 8 Test in Europe Conference. IEEE, 1--6.
[18]
Y. Huang, W. T. Cheng, and R. Guo. 2008. Diagnose multiple stuck-at scan chain faults. In Proceedings of the European Test Symposium. IEEE, 105--110.
[19]
Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski, R. Klingenberg, W. Hsu, and Y. S. Chen. 2006. Diagnosis with limited failure information. In Proceedings of the International Test Conference. IEEE, 1--10.
[20]
Y. Huang, X. Fan, H. Tang, M. Sharma, W.-T. Cheng, B. Benware, and S. M. Reddy. 2013. Distributed dynamic partitioning based diagnosis of scan chain. In Proceedings of the VLSI Test Symposium. IEEE, 1--6.
[21]
Y. L. Kao, W. S. Chuang, and J. C. M. Li. 2006. Jump simulation: A technique for fast and precise scan chain fault diagnosis. In Proceedings of the International Test Conference. IEEE, 1--9.
[22]
S. Kundu. 1994. Diagnosing scan chain faults. IEEE Transactions on VLSI Systems 2, 4 (April 1994), 512--516.
[23]
S. Kundu, S. Chattopadhyay, I. Sengupta, and R. Kapur. 2013. An ATE assisted DFD technique for volume diagnosis of scan chains. In Proceedings of the Design Automation Conference. ACM, 1--6.
[24]
S. Kundu, S. Chattopadhyay, I. Sengupta, and R. Kapur. 2015. Scan chain masking for diagnosis of multiple chain failures in a space compaction environment. IEEE Transactions on VLSI Systems 23, 7 (July 2015), 1185--1195.
[25]
M. Kurimoto, J. Matsushima, S. Ohbayashi, Y. Fukui, M. Komoda, and N. Tsuda. 2012. A yield and reliability improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule. ACM Transactions on Design Automation of Electronic Systems 17, 2 (April 2012), Article 17.
[26]
J.-F. Li, F. Zheng, and K.-T. Cheng. 2007. Diagnosing scan chains using SAT-based diagnostic pattern generation. In Proceedings of the International SOC Conference. IEEE, 273--276.
[27]
W.-H. Lo, A.-C. Hsieh, C.-M. Lan, M.-H. Lin, and T. Hwang. 2014. Utilizing circuit structure for scan chain diagnosis. IEEE Transactions on VLSI Systems 22, 12 (Dec. 2014), 2766--2778.
[28]
S. R. Makar and E. J. McCluskey. 1995. Functional tests for scan chain latches. In Proceedings of the International Test Conference. IEEE, 606--615.
[29]
S. Narayanan and A. Das. 1997. An efficient scheme to diagnose scan chains. In Proceedings of the International Test Conference. IEEE, 704--713.
[30]
I. Pomeranz. 2011. Generation of mixed broadside and skewed-load diagnostic test sets for transition faults. In Proceedings of the Pacific Rim International Symposium on Dependable Computing. IEEE, 45--52.
[31]
I. Pomeranz and S. M. Reddy. 1998. A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. In Proceedings of the International Test Conference. IEEE, 1074--1083.
[32]
I. Pomeranz and S. M. Reddy. 2003. Transparent scan: A new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Transactions on Computer-Aided Design 22, 12 (Dec. 2003), 1663--1670.
[33]
S. Prabhu, M. S. Hsiao, L. Lingappan, and V. Gangaram. 2012. A SMT-based diagnostic test generation method for combinational circuits. In Proceedings of the VLSI Test Symposium. IEEE, 215--220.
[34]
S. Ramprasath and V. Vasudevan. 2015. An efficient algorithm for statistical timing yield optimization. In Proceedings of the Design Automation Conference. ACM, Article 166.
[35]
M. A. Shukoor and V. D. Agrawal. 2009. A Two Phase Approach for Minimal Diagnostic Test Set Generation. In Proceedings of the European Test Symposium. IEEE, 115--120.
[36]
X. Tang, R. Guo, W.-T. Cheng, S. M. Reddy, and Y. Huang. 2009. On improving diagnostic test generation for scan chain failures. In Proceedings of the Asian Test Symposium. IEEE, 41--46.
[37]
M. Taouil, S. Hamdioui, and E. Jan Marinissen. 2015. Yield improvement for 3D wafer-to-wafer stacked ICs using wafer matching. ACM Transactions on Design Automation of Electronic Systems 20, 2 (Feb. 2015), Article 19.
[38]
W.-L. Tsai, W.-C. Liu, and J. C.-M. Li. 2012. Structural reduction techniques for logic-chain bridging fault diagnosis. IEEE Transactions on Computers 61, 7 (July 2012), 928--938.
[39]
A. Veneris, R. Chang, M. S. Abadir, and S. Seyedi. 2005. Functional fault equivalence and diagnostic test generation in combinational logic circuits using conventional ATPG. Journal of Electronic Testing: Theory and Applications (JETTA) 21, 5 (Oct. 2005), 495--502.
[40]
Y. Wu. 1998. Diagnosis of scan chain failures. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems. IEEE, 217--222.
[41]
J. Ye, Y. Huang, Y. Hu, W.-T. Cheng, R. Guo, L. Lai, T.-P. Tai, X. Li, W. Changchien, D.-M. Lee, J.-J. Chen, S. C. Eruvathi, K. K. Kumara, C. Liu, and S. Pan. 2015. Diagnosis and layout aware (DLA) scan chain stitching. IEEE Transactions on VLSI Systems 23, 3 (March 2015), 466--479.
[42]
J. Ye, X. Zhang, Y. Hu, and X. Li. 2010. Substantial fault pair at-a-time (SFPAT): An automatic diagnostic pattern generation method. In Proceedings of the Asian Test Symposium. IEEE, 192--197.
[43]
Y. Zhang and V. D. Agrawal. 2010. A diagnostic test generation system. In Proceedings of the International Test Conference. IEEE, 1--9.
[44]
Y. Zorian. 2002. Embedding infrastructure IP for SOC yield improvement. In Proceedings of the Design Automation Conference. ACM, 709--712.

Cited By

View all
  • (2023)Test Data Compression for Transparent-Scan SequencesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.324050531:4(601-605)Online publication date: Apr-2023
  • (2023)Optical Character Recognition (OCR)-Based and Gaussian Mixture Modeling-OCR-Based Slide-Level “With-Me-Ness”: Automated Measurement and Feedback of Learners’ Attention State during Video LecturesInternational Journal of Human–Computer Interaction10.1080/10447318.2023.220427240:15(3952-3971)Online publication date: 7-May-2023
  • (2018)Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation PointsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.274802037:6(1278-1287)Online publication date: Jun-2018
  • Show More Cited By

Index Terms

  1. Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 22, Issue 3
    July 2017
    440 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3062395
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 23 May 2017
    Accepted: 01 October 2016
    Revised: 01 August 2016
    Received: 01 June 2016
    Published in TODAES Volume 22, Issue 3

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. Diagnostic test generation
    2. full-scan circuits
    3. scan chain faults
    4. transparent-scan

    Qualifiers

    • Research-article
    • Research
    • Refereed

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)5
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 14 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2023)Test Data Compression for Transparent-Scan SequencesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.324050531:4(601-605)Online publication date: Apr-2023
    • (2023)Optical Character Recognition (OCR)-Based and Gaussian Mixture Modeling-OCR-Based Slide-Level “With-Me-Ness”: Automated Measurement and Feedback of Learners’ Attention State during Video LecturesInternational Journal of Human–Computer Interaction10.1080/10447318.2023.220427240:15(3952-3971)Online publication date: 7-May-2023
    • (2018)Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation PointsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.274802037:6(1278-1287)Online publication date: Jun-2018
    • (2017)Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults2017 IEEE 26th Asian Test Symposium (ATS)10.1109/ATS.2017.35(133-138)Online publication date: Nov-2017

    View Options

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media