Article

Cache conscious data layout organization for embedded multimedia applications

Authors:

C. Kulkarni,

C. Ghez,

M. Miranda,

F. Catthoor,

H. de ManAuthors Info & Claims

DATE '01: Proceedings of the conference on Design, automation and test in Europe

Pages 686 - 693

Published: 13 March 2001 Publication History

Get Access

References

[1]

P.Baglietto, M.Maresca and M.Migliardi, "Image processing on highperformance RISC systems", Proc. of the IEEE, vol. 84, no. 7, pp.917- 929, july 1996.

Crossref

Google Scholar

[2]

V.Bhaskaran and K. Konstantinides, "Image and Video Compression Standards : Algorithms and Architectures", Kluwer Acad. Publ., Boston, 1995.

Digital Library

Google Scholar

[3]

P.Clauss, B.Meister, "Automatic memory layout transformation to optimize spatial locality in parametrized loop nests", 4th Annual Workshop on Interaction between Compilers and Comp. Arch. (INTERACT- 4), Toulouse, France, Jan 2000.

Google Scholar

[4]

J.Covino, J.Connor, D.Evans, A.Roberts, M.Robillard, J.Sousa, L.Ternullo, "A 2ns zero wait state, 32KB semi-associative L1 cache", IEEE Intl Solid State Circuits Conference (ISSCC-96), pp. 154-155, 1996.

Google Scholar

[5]

E.De Greef, "Storage size reduction for multimedia applications", Doctoral Dissertation, Dept. of EE, K.U.Leuven, January 1998.

Google Scholar

[6]

F.Catthoor, S.Wuytack, E.De Greef, F.Balasa, L.Nachtergaele, A.Vandecappelle, "Custom Memory Management Methodology - Exploration of Memory Organization for Embedded Multimedia System Design", ISBN 0-7923-8288-9, Kluwer Acad. Publ., Boston, 1998.

Digital Library

Google Scholar

[7]

C.Ghez, M.Miranda, A.Vandecappelle, F.Catthoor, D.Verkest, "Systematic high-level address code transformations for piece-wise linear indexing: illustration on a medical imaging algorithm", Proc. IEEE Wsh. on Signal Processing Systems (SIPS), Lafayette LA, IEEE Press, Oct. 2000.

Crossref

Google Scholar

[8]

S.Ghosh, M.Martonosi, S.Malik, "Cache Miss Equations : A Compiler Framework for Analyzing and Tuning Memory Behaviour", ACM transactions on Programming Languages and Systems, vol. 21, No. 4, pp. 702-746, July 1999.

Digital Library

Google Scholar

[9]

N.Jouppi, et al., "A 300-MHz 115-W 32-b bipolar ECL microprocessor", In IEEE Journal of solid-state circuits, pp. 1152-1165, Nov 1993.

Crossref

Google Scholar

[10]

M.Kandemir, J.Ramanujam, A.Choudhary, "Improving cache locality by a combination of loop and data transformations", IEEE trans. on computers, vol. 48, no. 2, pp. 159-167, 1999.

Digital Library

Google Scholar

[11]

C.Kulkarni, F.Catthoor, H.De Man, "Advanced data layout optimization for multimedia applications", Lecture notes in computer science (PDIVM/IPDPS 2000), vol. 1800, pp. 186-193, May 2000.

Digital Library

Google Scholar

[12]

C.Kulkarni, F.Catthoor, H.De Man, "Cache optimization for multimedia applications", Doctoral Dissertation, Dept. of EE, K.U.Leuven, February 2001.

Google Scholar

[13]

C.Kulkarni, F.Catthoor, H.De Man, "Code transformations for low power caching in embedded multimedia processors,", Intnl. Parallel Proc. Symp.(IPPS/SPDP), Orlando FL, pp.292-297,April 1998.

Digital Library

Google Scholar

[14]

D.Kulkarni, M.Stumm, "Linear loop transformations in optimizing compilers for parallel machines", The Australian computer journal, pp.41-50, may 1995.

Google Scholar

[15]

M.Lam, E.Rothberg, M.Wolf, "The cache performance and optimizations of blocked algorithms", In Proc. 6th Intnl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV), pp.63-74, Santa Clara, Ca., 1991.

Digital Library

Google Scholar

[16]

N.Manjikian and T.Abdelrahman, "Array data layout for reduction of cache conflicts", Intl. Conference on Parallel and Distributed Computing Systems, 1995.

Google Scholar

[17]

G.L.Nemhauser, L.A.Wolsey, "Integer and Combinatorial Optimization", J.Wiley&Sons, New York, N.Y., 1988.

Digital Library

Google Scholar

[18]

P.R.Panda, N.Dutt, A.Nicolau, "Memory issues in embedded systems-onchip", Kluwer Academic Publishers, Boston, MA, 1999.

Digital Library

Google Scholar

[19]

D.A.Patterson, J.L.Hennessy, "Computer architecture: A quantitative approach", Morgan Kaufmann Publishers Inc., San Francisco,1996.

Digital Library

Google Scholar

[20]

G.Rivera, C.Tseng, "Compiler optimizations for eliminating cache conflict misses", Technical Report CS-TR-3819, Dept of Computer Science, University of Maryland, July 1997.

Digital Library

Google Scholar

[21]

D.Burger, T.Austin, "The Simplescalar Toolset", Version 2.0, online document available at http://ww.cs.wisc.edu/ mscalar/simplescalar.html.

Google Scholar

Cited By

View all

Elizeh KNicolici NSapatnekar S(2010)Embedded memory binding in FPGAsProceedings of the 47th Design Automation Conference10.1145/1837274.1837389(457-462)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837389
Geelen BFerentinos VCatthoor FLafruit GVerkest DLauwereins RStouraitis T(2010)Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirementsACM Transactions on Embedded Computing Systems10.1145/1698772.16987759:3(1-26)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698775
Geelen BFerentinos VCatthoor FToulatos SLafruit GStouraitis TLauwereins RVerkest D(2009)Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution EnvironmentsJournal of Signal Processing Systems10.1007/s11265-008-0223-556:2-3(125-139)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1007/s11265-008-0223-5
Show More Cited By

Index Terms

Cache conscious data layout organization for embedded multimedia applications

Recommendations

Cache-conscious structure layout
PLDI '99: Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation

Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating ...
Cache-conscious structure layout

Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating ...
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications

Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. In this ...

Comments

Information & Contributors

Information

Published In

DATE '01: Proceedings of the conference on Design, automation and test in Europe

March 2001

756 pages

ISBN:0769509932

Editors:
Wolfgang Nebel
Oldenburg Univ. and OFFIS, Germany
,
Ahmed Jerraya
TIMA, Grenoble, France

Publisher

IEEE Press

Publication History

Published: 13 March 2001

Check for updates

Qualifiers

Article

Conference

DATE01

Sponsor:

EDAA
IFIP WG 10.5
EDAC
SIGDA
IEEE-CS\TTTC
IEEE-CS\DATC
The Russian Academy of Sciences

DATE01: Design, Automation and Test in Europe

Munich, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
275
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)1

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Elizeh KNicolici NSapatnekar S(2010)Embedded memory binding in FPGAsProceedings of the 47th Design Automation Conference10.1145/1837274.1837389(457-462)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837389
Geelen BFerentinos VCatthoor FLafruit GVerkest DLauwereins RStouraitis T(2010)Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirementsACM Transactions on Embedded Computing Systems10.1145/1698772.16987759:3(1-26)Online publication date: 5-Mar-2010
https://dl.acm.org/doi/10.1145/1698772.1698775
Geelen BFerentinos VCatthoor FToulatos SLafruit GStouraitis TLauwereins RVerkest D(2009)Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution EnvironmentsJournal of Signal Processing Systems10.1007/s11265-008-0223-556:2-3(125-139)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1007/s11265-008-0223-5
Otoom MPaul JGebotys CMartin G(2008)Holistic design and caching in mobile computingProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450161(115-120)Online publication date: 19-Oct-2008
https://dl.acm.org/doi/10.1145/1450135.1450161
Choudhury MRinggenberg KRixner SMohanram KLauwereins RMadsen J(2007)Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memoryProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266597(1072-1077)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266597
Issenin IBrockmeyer EMiranda MDutt N(2007)DRDUACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080712:2(15-es)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1145/1230800.1230807
Senn ELaurent JJulien NMartin E(2005)SoftexplorerEURASIP Journal on Advances in Signal Processing10.1155/ASP.2005.26412005(2641-2654)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1155/ASP.2005.2641
Issenin IBrockmeyer EMiranda MDutt N(2004)Data Reuse Analysis Technique for Software-Controlled Memory HierarchiesProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.968995Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.968995
Mohanram KRixner S(2004)Context-independent codes for off-chip interconnectsProceedings of the 4th international conference on Power-Aware Computer Systems10.1007/11574859_8(107-119)Online publication date: 5-Dec-2004
https://dl.acm.org/doi/10.1007/11574859_8
Kumar TGovindarajan RKumar C(2003)Optimal Code and Data Layout in Embedded SystemsProceedings of the 16th International Conference on VLSI Design10.5555/832285.835604Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835604
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Cache-conscious structure layout

Cache-conscious structure layout

Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications

Comments

Published In

Sponsors

Publisher

Publication History

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

References

Cited By

Index Terms

Recommendations

Cache-conscious structure layout

Cache-conscious structure layout

Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications

Comments

Information

Published In

Sponsors

Publisher

Publication History

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations