article

Zero cost indexing for improved processor cache performance

Author:

Tony GivargisAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 1

Pages 3 - 25

https://doi.org/10.1145/1124713.1124715

Published: 01 January 2006 Publication History

Abstract

The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory address bus consists of the K least significant bits, where K = log₂ D and D is the depth of the cache. However, in devices where the application set is known and characterized (e.g., systems that execute a fixed application set) there is an opportunity to improve cache performance by choosing a near-optimal set of bits used as index into the cache. This technique does not add any overhead in terms of area or delay. In this article, we present an efficient heuristic algorithm for selecting K index bits for improved cache performance. We show the feasibility of our algorithm by applying it to a large number of embedded system applications as well as the integer SPEC CPU 2000 benchmarks. Specifically, for data traces, we show up to 45% reduction in cache misses. Likewise, for instruction traces, we show up to 31% reduction in cache misses. When a unified data/instruction cache architecture is considered, our results show an average improvement of 14.5% for the Powerstone benchmarks and an average improvement of 15.2% for the SPEC'00 benchmarks.

References

[1]

Abella, J., Gonzalez, A., Liosa, J., and Vera, X. 2002. Near-optimal loop tiling by means of cache miss equations and genetic algorithms. In Proceedings of the International Conference on Parallel Processing Workshops (Washington, DC). IEEE Computer Society Press, Los Alamitos, CA, 568--580.]]

[2]

Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., and Dwarkadas, S. 2000. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In Proceedings of the International Symposium on Microarchitecture. ACM, New York, 245--257.]]

[3]

Corman, T., Leiserson, C., Rivest, R., and Stein, C. 2001. Introduction to Algorithms, 2 ed. The MIT Press and McGraw-Hill, Cambridge, MA.]]

[4]

Ding, C. and Kennedy, K. 1999. Improving cache performance in dynamic applications through data and computation reorganization at run time. In Proceedings of the Conference on Programming Language Design and Implementation. ACM, New York, 229--241.]]

[5]

Grun, P., Dutt, N., and Nicolau, A. 2000. Memory aware compilation through accurate timing extraction. In Proceedings of the Design Automation Conference. ACM, New York, 316--321.]]

[6]

Grun, P., Dutt, N., and Nicolau, A. 2001. Aggressive memory-aware compilation. In Intelligent Memory Systems. Springer-Verlag, London, UK, 147--151.]]

[7]

Gurari, E. 1989. An introduction to the theory of computation. McGraw-Hill, New York.]]

[8]

Huang, Q., Xue, J., and Vera, X. 2003. Code tiling for improving the cache performance of pde solvers. In Proceedings of the International Conference on Parallel Processing. ACM, New York, 615--626.]]

[9]

ITRS. 2005. Technology roadmap for semiconductors. http://www.itrs.com.]]

[10]

Kozyrakis, C. and Patterson, D. 1998. A new direction for computer architecture research. IEEE Comput. 31, 11, 24--32.]]

Digital Library

[11]

Malik, A., Moyer, B., and Cermak, D. 2000. A low power unified cache architecture providing power and performance flexibility. In Proceedings of the Symposium on Low Power Electronics and Design. ACM, New York, 241--243.]]

[12]

Panda, P., Nakamura, H., Dutt, N., and Nicolau, A. 1997. Improving cache performance through riling and data alignment. In Proceedings of the Workshop on Parallel Algorithms for Irregularly Structured Problems. ACM, New York, 167--185.]]

[13]

Patterson, D. and Hennessy, J. 1997. Computer Organization and Design: The Hardware/Software Interface, 2 ed. Morgan-Kaufmann, San Francisco, CA.]]

[14]

Petrov, P. and Orailoglu, A. 2001. Towards effective embedded processors in codesigns: Customizable partitioned caches. In Proceedings of the International Conference on Hardware/Software Codesign. ACM, New York, 79--84.]]

[15]

PowerStone. 1999. The powerstone benchmarks. www.motorola.com.]]

[16]

Rivera, G. and Tseng, C.-W. 1997. Compiler optimizations for eliminating cache conflict misses. Tech. Rep. CS-TR-3819, University of Maryland.]]

[17]

SPEC'00. Spec cpu 2000. http://www.spec.org.]]

[18]

Su, C. L. and Despain, A. 1995. Cache design trade-offs for power and performance optimization: A case study. In Proceedings of the International Symposium on Low Power Electronics and Design. ACM, New York, 63--68.]]

[19]

Suzuki, K., Arai, T., Kouhei, N., and Kuroda, I. 1998. V830R/Av: Embedded multimedia superscalar RISC processor. IEEE Micro 18, 2, 36--47.]]

Digital Library

[20]

Tiwari, B. and Martonosi, M. 2000. Wattch: A framework for architecture-level power analysis and optimization. In Proceedings of the Symposium on Computer Architecture. ACM, New York, 83--94.]]

[21]

Vahid, F. and Givargis, T. 1999. The case for a configure-and-execute paradigm. In Proceedings of the International Conference on Hardware/Software Codesign. ACM, New York, 59--63.]]

[22]

Wong, S., Vassiliadis, S., and Cotofana, S. 2004. Future directions of (programmable and reconfigurable) embedded processors. In Domain-Specific Processors: Systems, Architecture, Modeling, and Simulation. Marcel Dekker, Inc., London, UK, 235--257.]]

Cited By

Azarian AM.P. Cardoso J(2016)Pipelining data-dependent tasks in FPGA-based multicore architecturesMicroprocessors and Microsystems10.1016/j.micpro.2016.02.00842(165-179)Online publication date: May-2016
https://doi.org/10.1016/j.micpro.2016.02.008
Díaz Álvarez JRisco-Martín JColmenar J(2016)Multi-objective optimization of energy consumption and execution time in a single level cache memory for embedded systemsJournal of Systems and Software10.1016/j.jss.2015.10.012111:C(200-212)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.jss.2015.10.012
Ros AXekalakis PCintra MAcacio MGarcıa J(2015)Adaptive Selection of Cache Indexing Bits for Removing Conflict MissesIEEE Transactions on Computers10.1109/TC.2014.233981964:6(1534-1547)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1109/TC.2014.2339819
Show More Cited By

Index Terms

Zero cost indexing for improved processor cache performance
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

Recommendations

Improved indexing for cache miss reduction in embedded systems
DAC '03: Proceedings of the 40th annual Design Automation Conference

The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory ...
A graph theoretic approach to cache-conscious placement of data for direct mapped caches
ISMM '10: Proceedings of the 2010 international symposium on Memory management

Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed data closer to the processor. Over the years the increasing gap between processor speed and memory access latency has made the cache a bottleneck for ...
A graph theoretic approach to cache-conscious placement of data for direct mapped caches
ISMM '10

Caches were designed to amortize the cost of memory accesses by moving copies of frequently accessed data closer to the processor. Over the years the increasing gap between processor speed and memory access latency has made the cache a bottleneck for ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 1

January 2006

250 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1124713

Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 January 2006

Published in TODAES Volume 11, Issue 1

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
664
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 09 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Azarian AM.P. Cardoso J(2016)Pipelining data-dependent tasks in FPGA-based multicore architecturesMicroprocessors and Microsystems10.1016/j.micpro.2016.02.00842(165-179)Online publication date: May-2016
https://doi.org/10.1016/j.micpro.2016.02.008
Díaz Álvarez JRisco-Martín JColmenar J(2016)Multi-objective optimization of energy consumption and execution time in a single level cache memory for embedded systemsJournal of Systems and Software10.1016/j.jss.2015.10.012111:C(200-212)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.jss.2015.10.012
Ros AXekalakis PCintra MAcacio MGarcıa J(2015)Adaptive Selection of Cache Indexing Bits for Removing Conflict MissesIEEE Transactions on Computers10.1109/TC.2014.233981964:6(1534-1547)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1109/TC.2014.2339819
Azarian ACardoso JWerner SBecker JShin SMaldonado J(2013)An FPGA-based multi-core approach for pipelining computing stagesProceedings of the 28th Annual ACM Symposium on Applied Computing10.1145/2480362.2480647(1533-1540)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.1145/2480362.2480647
Zhou XPetrov P(2009)Direct address translation for virtual memory in energy-efficient embedded systemsACM Transactions on Embedded Computing Systems10.1145/1457246.14572518:1(1-31)Online publication date: 4-Jan-2009
https://dl.acm.org/doi/10.1145/1457246.1457251
Petrov POrailoglu A(2007)Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual MemoryInternational Journal of Parallel Programming10.1007/s10766-006-0030-135:2(157-177)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1007/s10766-006-0030-1

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents