research-article

Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers

Authors:

Chun-Da DuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 1

Article No.: 6, Pages 1 - 36

https://doi.org/10.1145/1640457.1640463

Published: 28 December 2009 Publication History

Abstract

Solid-state disks (SSDs) are storage devices that emulate hard drives with flash memory. They have been widely deployed in mobile computers as disk drive replacements. Flash memory is organized in terms of erase blocks. With the current technology, a block can reach the end of its lifetime after thousands of erasure operations. Wear leveling is a technique to evenly erase the entire flash memory so that all blocks remain alive as long as possible. This study introduces a new wear-leveling algorithm based the observation that, under a real-life mobile PC's workload, most erasure operations are contributed by a small fraction of blocks. Our key ideas are 1) moving rarely updated data to a block that is extraordinarily worn and 2) avoiding repeatedly involving a block in wear-leveling activities. This study presents a successful implementation of the proposed wear-leveling algorithm using about 200 bytes of RAM in an SSD controller rated at 33 MHz. Evaluation results show that this algorithm achieves even wear of the entire flash memory while reducing the overheads of extra flash-memory operations.

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Cited By

Liu SKanniwadi SSchwarzl MKogler AGruss DKhan SCalandrino JTroncoso C(2023)Side-channel attacks on optane persistent memoryProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620618(6807-6824)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620618
Bartolo ASabry Aly MMichelogiannakis GMitra S(2023)MC-ELMM: Multi-Chip Endurance-Limited Memory ManagementProceedings of the International Symposium on Memory Systems10.1145/3631882.3631905(1-16)Online publication date: 2-Oct-2023
https://dl.acm.org/doi/10.1145/3631882.3631905
Jin YLee DJang HLee B(2022)ReCA-FTL: Resource Contention Aware Flash Translation Layer2022 IEEE International Conference on Networking, Architecture and Storage (NAS)10.1109/NAS55553.2022.9925368(1-8)Online publication date: Oct-2022
https://doi.org/10.1109/NAS55553.2022.9925368
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Index Terms

Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Garbage collection
        Secondary storage

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 15, Issue 1

December 2009

188 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1640457

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 December 2009

Accepted: 01 August 2009

Revised: 01 April 2009

Received: 01 September 2008

Published in TODAES Volume 15, Issue 1

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Cited By

Liu SKanniwadi SSchwarzl MKogler AGruss DKhan SCalandrino JTroncoso C(2023)Side-channel attacks on optane persistent memoryProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620618(6807-6824)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620618
Bartolo ASabry Aly MMichelogiannakis GMitra S(2023)MC-ELMM: Multi-Chip Endurance-Limited Memory ManagementProceedings of the International Symposium on Memory Systems10.1145/3631882.3631905(1-16)Online publication date: 2-Oct-2023
https://dl.acm.org/doi/10.1145/3631882.3631905
Jin YLee DJang HLee B(2022)ReCA-FTL: Resource Contention Aware Flash Translation Layer2022 IEEE International Conference on Networking, Architecture and Storage (NAS)10.1109/NAS55553.2022.9925368(1-8)Online publication date: Oct-2022
https://doi.org/10.1109/NAS55553.2022.9925368
Zhong ZLiang TChakrabarty K(2021)Enhancing the Reliability of MEDA Biochips Using IJTAG and Wear LevelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.303262940:10(2063-2076)Online publication date: Oct-2021
https://doi.org/10.1109/TCAD.2020.3032629
Cârstoiu GMicea MUngurean LMarcu M(2020)Novel battery wear leveling method for large‐scale reconfigurable battery packsInternational Journal of Energy Research10.1002/er.5879Online publication date: 7-Sep-2020
https://doi.org/10.1002/er.5879
Grossi AVianello ESabry MBarlas MGrenouillet LCoignus JBeigne EWu TLe BWootters MZambelli CNowak EMitra S(2019)Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning ApplicationsIEEE Transactions on Electron Devices10.1109/TED.2019.289438766:3(1281-1288)Online publication date: Mar-2019
https://doi.org/10.1109/TED.2019.2894387
Lin HHsieh J(2019)Revive Bad Flash-Memory Pages by HLC SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283442038:5(860-873)Online publication date: May-2019
https://doi.org/10.1109/TCAD.2018.2834420
Hiep NHsieh JHung CSaid L(2018)Timestamp-based hot/cold data identification scheme for solid state drivesProceedings of the 2018 Conference on Research in Adaptive and Convergent Systems10.1145/3264746.3264790(255-259)Online publication date: 9-Oct-2018
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