research-article

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Authors:

Gilles SicardAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16, Issue 3

Article No.: 35, Pages 1 - 17

https://doi.org/10.1145/1970353.1970369

Published: 01 June 2011 Publication History

Abstract

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

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Cited By

Lim YKamsani NSidek RHashim SRokhani F(2023)Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage OperationIEEE Access10.1109/ACCESS.2022.323089711(12536-12546)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2022.3230897
Valdes APossani VMarranghello FReis ARibas R(2016)Performance evaluation of optimized transistor networks built using independent-gate FinFET2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2016.7451051(227-230)Online publication date: Feb-2016
https://doi.org/10.1109/LASCAS.2016.7451051
Abouzeid FBienfait AAkyel KClerc SCiampolini LRoche P(2013)Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI2013 Proceedings of the ESSCIRC (ESSCIRC)10.1109/ESSCIRC.2013.6649108(205-208)Online publication date: Sep-2013
https://doi.org/10.1109/ESSCIRC.2013.6649108
Show More Cited By

Index Terms

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 16, Issue 3

June 2011

330 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1970353

Issue’s Table of Contents

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 June 2011

Accepted: 01 January 2011

Revised: 01 November 2010

Received: 01 January 2010

Published in TODAES Volume 16, Issue 3

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Cited By

Lim YKamsani NSidek RHashim SRokhani F(2023)Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage OperationIEEE Access10.1109/ACCESS.2022.323089711(12536-12546)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2022.3230897
Valdes APossani VMarranghello FReis ARibas R(2016)Performance evaluation of optimized transistor networks built using independent-gate FinFET2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2016.7451051(227-230)Online publication date: Feb-2016
https://doi.org/10.1109/LASCAS.2016.7451051
Abouzeid FBienfait AAkyel KClerc SCiampolini LRoche P(2013)Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI2013 Proceedings of the ESSCIRC (ESSCIRC)10.1109/ESSCIRC.2013.6649108(205-208)Online publication date: Sep-2013
https://doi.org/10.1109/ESSCIRC.2013.6649108
Kondo MNishizawa SIshihara TOnodera H(2013)A Standard Cell Optimization Method for Near-Threshold Voltage OperationsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-36157-9_4(32-41)Online publication date: 2013
https://doi.org/10.1007/978-3-642-36157-9_4
Abouzeid FClerc SPelloux-Prayer BArgoud FRoche P(2012)28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder2012 Proceedings of the ESSCIRC (ESSCIRC)10.1109/ESSCIRC.2012.6341282(153-156)Online publication date: Sep-2012
https://doi.org/10.1109/ESSCIRC.2012.6341282

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