article

Free access

Object-oriented cosynthesis of distributed embedded systems

Editor: C. L. Liu Author:

Wayne WolfAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 1, Issue 3

Pages 301 - 314

https://doi.org/10.1145/234860.234861

Published: 01 July 1996 Publication History

Abstract

This article describes a new hardware-software cosynthesis algorithm that takes advantage of the structure inherent in an object-oriented specification. The algorithm creates a distributed system implementation with arbitrary topology, using the object-oriented structure to partition functionality in addition to scheduling and allocating processes. Process partitioning is an especially important optimization for such systems because the specification will not, in general, take into account the process structure required for efficient execution on the distributed engine. The object-oriented specification naturally provides both coarse-grained and fine-grained partitions of the system. Our algorithm uses that multilevel structure to guide synthesis. Experimental results show that our algorithm takes advantage of the object-oriented specification to quickly converge on high-quality implementations.

References

[1]

BOOCH, G. 1989. Object-Oriented Design. Addison-Wesley, Reading, MA.

[2]

CALVEZ, J.P. 1993. Embedded Real-Time Systems: A Specification and Design Methodology. Wiley, New York.

[3]

BARROS, E., ROSENSTIEL, W., AND XIONG, X. 1994. A method for partitioning UNITY language in hardware and software. In Proceedings, EuroDAC '94, IEEE Computer Society Press, 220-225.

[4]

CHU, W. W. AND TAN, L.M.-T. 1987. Task allocation and precedence relations for distributed real-time systems. IEEE Trans. Comput. C-36, 6 (June), 667-679.

[5]

DASARATHY, B. AND FERIDUN, M. 1984. Task allocation problems in the synthesis of distributed real-time systems. In Proceedings, IEEE 1984 Real-Time Systems Symposium, IEEE, Piscataway, NJ, 135-144.

[6]

ERNST, R., HENKEL, g., AND BENNER, T. 1993. Hardware-software co-synthesis for microcontrollers. IEEE Des. Test Comput. 10, 4 (Dec.), 64-75.

[7]

GUPTA, R. K. AND DE MICHELI, G. 1993. Hardware-software cosynthesis for digital systems. IEEE Des. Test Comput. 10, 3 (Sept.), 29-41.

[8]

HUANG, J. P. 1985. Modeling of software partition for distributed real-time applications. IEEE Trans. Softw. Eng. SE-11, 10 (Oct.), 1113-1126.

[9]

ISMAIL, T. B., O'BRIEN, K., AND JERRAYA, A. 1994. Interactive system-level partitioning with PARTIF. In Proceedings, EDAC '94, IEEE Computer Society Press, Los Alamitos, CA.

[10]

LAGNESE, E. D. AND THOMAS, D.E. 1991. Architectural partitioning of system level synthesis of integrated circuits. IEEE Trans. CAD/ICAS 10, 7 (July), 847-860.

[11]

LIU, C. L. AND LAYLAND, J. W. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. ACM 20, 1 (Jan.) 46-61.

[12]

PRAKASH, S. AND PARKER, A.C. 1992. SOS: Synthesis of application-specific heterogeneous multiprocessor systems. J. Parallel Distrib. Comput. 16, 338-351.

[13]

PRESSMAN, R. S. 1992. Software Engineering: A Practitioner's Approach, 3rd ed. McGraw Hill, New York.

[14]

RAMAMRITHAM, K., STANKOVIC, J. A., AND SHIAH, P.-F. 1990. Efficient scheduling algorithms for real-time multiprocessor systems. IEEE Trans. Parallel Distrib. Syst. 1, 2 (April), 184-194.

[15]

RUMBAUGH, J., BLAHA, M., PREMERLANI, W., EDDY, F., AND LORENSEN, W. 1991. Object- Oriented Modeling and Design. Prentice Hall, Englewood Cliffs, NJ.

[16]

SELIC, B., GULLEKSON, G., AND WARD, P. T. 1984. Real-Time Object-Oriented Modeling. Wiley, New York.

[17]

SHLAER, S. AND MELLOR, S.J. 1992. Object Lifecycles: Modeling the World in States. Yourdon Press, Englewood Cliffs, NJ.

[18]

VAHID, F., GONG, J., AND GAJSKI, D. D. 1994. A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. In Proceedings, EuroDAC '94, IEEE Computer Society Press, Los Alamitos, CA, 214-219.

[19]

WOLF, W. 1994. Hardware-software co-design of embedded systems. Proc. IEEE 82, 7 (July) 967-989.

[20]

WOLF, W. 1996. An architectural co-synthesis for distributed, embedded computing systems. IEEE Trans. VLSI Syst., accepted for publication.

[21]

YEN, T.-Y. AND WOLF, W. 1995a. Sensitivity-driven co-synthesis of distributed embedded systems. In Proceedings, International Symposium on System Synthesis, IEEE Computer Society Press, Los Alamitos, CA.

[22]

YEN, T.-Y. AND WOLF, W. 1995b. Communication synthesis for distributed embedded sys- tems. In Proceedings, ICCAD-95, IEEE Computer Society Press, Los Alamitos, CA, 288-294.

[23]

ZAVE, P. 1989. A compositional approach to multiparadigm programming. IEEE Softw. (Sept.), 15-25.

Cited By

Wolf MSerpanos DWolf MSerpanos D(2019)ArchitecturesSafe and Secure Cyber-Physical Systems and Internet-of-Things Systems10.1007/978-3-030-25808-5_4(47-57)Online publication date: 25-Sep-2019
https://doi.org/10.1007/978-3-030-25808-5_4
Jiang GWu JLam SSrikanthan TSun J(2015)Algorithmic aspects of graph reduction for hardware/software partitioningThe Journal of Supercomputing10.1007/s11227-015-1381-471:6(2251-2274)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1007/s11227-015-1381-4
Olson JRozenblit JTalarico CJacak W(2007)Hardware/Software Partitioning Using Bayesian Belief NetworksIEEE Transactions on Systems, Man, and Cybernetics - Part A: Systems and Humans10.1109/TSMCA.2007.90262337:5(655-668)Online publication date: Sep-2007
https://doi.org/10.1109/TSMCA.2007.902623
Show More Cited By

Index Terms

Object-oriented cosynthesis of distributed embedded systems
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

Recommendations

Communication synthesis for distributed embedded systems
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Abstract: Communication synthesis is an essential step in hardware-software co-synthesis: many embedded systems use custom communication topologies and the communication links are often a significant part of the system cost. This paper describes new ...
Fingerprint image processing acceleration through run-time reconfigurable hardware

To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main ...
Automatic translation of software binaries onto FPGAs
DAC '04: Proceedings of the 41st annual Design Automation Conference

The introduction of advanced FPGA architectures, with built-in DSP support, has given DSP designers a new hardware alternative. By exploiting its inherent parallelism, it is expected that FPGAs can outperform DSP processors. This paper describes the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 1, Issue 3

July 1996

103 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/234860

Editor:
C. L. Liu
Univ. of Illinois at Urbana-Champaign, Urbana

Issue’s Table of Contents

Copyright © 1996 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 July 1996

Published in TODAES Volume 1, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

23
Total Citations
View Citations
500
Total Downloads

Downloads (Last 12 months)19
Downloads (Last 6 weeks)8

Reflects downloads up to 11 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wolf MSerpanos DWolf MSerpanos D(2019)ArchitecturesSafe and Secure Cyber-Physical Systems and Internet-of-Things Systems10.1007/978-3-030-25808-5_4(47-57)Online publication date: 25-Sep-2019
https://doi.org/10.1007/978-3-030-25808-5_4
Jiang GWu JLam SSrikanthan TSun J(2015)Algorithmic aspects of graph reduction for hardware/software partitioningThe Journal of Supercomputing10.1007/s11227-015-1381-471:6(2251-2274)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1007/s11227-015-1381-4
Olson JRozenblit JTalarico CJacak W(2007)Hardware/Software Partitioning Using Bayesian Belief NetworksIEEE Transactions on Systems, Man, and Cybernetics - Part A: Systems and Humans10.1109/TSMCA.2007.90262337:5(655-668)Online publication date: Sep-2007
https://doi.org/10.1109/TSMCA.2007.902623
Gopalakrishnan SCaccamo MSha L(2006)Switch Scheduling and Network Design for Real-Time SystemsProceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium10.1109/RTAS.2006.42(289-300)Online publication date: 4-Apr-2006
https://dl.acm.org/doi/10.1109/RTAS.2006.42
Damaševičius RŠtuikys V(2004)Application of the object-oriented principles for hardware and embedded system designIntegration, the VLSI Journal10.1016/j.vlsi.2004.08.00538:2(309-339)Online publication date: 1-Dec-2004
https://dl.acm.org/doi/10.1016/j.vlsi.2004.08.005
Noguera JBadia R(2002)HW/SW codesign techniques for dynamically reconfigurable architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80157510:4(399-415)Online publication date: 1-Aug-2002
https://dl.acm.org/doi/10.1109/TVLSI.2002.801575
Buchenrieder KNageldinger UPyttel ASedlmeier A(2002)System prototyping by integration of reconfigurable hardware into a heterogeneous system modelProceedings 13th IEEE International Workshop on Rapid System Prototyping10.1109/IWRSP.2002.1029746(115-121)Online publication date: 2002
https://doi.org/10.1109/IWRSP.2002.1029746
Buchenrieder KPyttel ASedlmeier A(2002)A powerful system design methodology combining OCAPI and Handel-C for concept engineeringProceedings 2002 Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2002.998401(870-874)Online publication date: 2002
https://doi.org/10.1109/DATE.2002.998401
Buchenrieder KNageldinger UPyttel ASedlmeier A(2002)Integration of Reconfigurable Hardware into System-Level DesignField-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream10.1007/3-540-46117-5_101(987-996)Online publication date: 16-Aug-2002
https://doi.org/10.1007/3-540-46117-5_101
Piguet CRenaudin MOmnés T(2001)Low-power systems on chips (SOCs)Proceedings of the conference on Design, automation and test in Europe10.5555/367072.367335Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367335
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents