research-article

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

Authors:

Steven J. E. WiltonAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 2

Article No.: 14, Pages 1 - 23

https://doi.org/10.1145/2566668

Published: 28 March 2014 Publication History

Abstract

FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of on-chip visibility when debugging. To counter this, trace-buffer-based instrumentation can be installed into the prototype, allowing designers to capture a predetermined window of signal data during live operation for offline analysis. However, instead of requiring the designer to recompile their entire circuit every time the window is modified, this article proposes that an overlay network is constructed using only spare FPGA routing multiplexers to connect all circuit signals through to the trace instruments. Thus, during debugging, designers would only need to reconfigure this network instead of finding a new place-and-route solution. Furthermore, we describe how this network can deliver signals to both the trigger and trace units of these instruments, which are implemented simultaneously using dual-port RAMs. Our results show that new network configurations connecting any subset of signals to 80--90% of the available RAM capacity can be computed in less than 70 seconds, for a 100,000 LUT circuit, as many times as necessary. Our tool—QuickTrace—is available for download.

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Cited By

Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Khan HKamal AGoehringer D(2018)An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_35(433-445)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_35
Lettnin DWinterholer M(2017)An Overview About Debugging and Verification Techniques for Embedded SoftwareEmbedded Software Verification and Debugging10.1007/978-1-4614-2266-2_1(1-18)Online publication date: 19-Apr-2017
https://doi.org/10.1007/978-1-4614-2266-2_1
Show More Cited By

Index Terms

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 19, Issue 2

March 2014

314 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2597648

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 March 2014

Accepted: 01 December 2013

Revised: 01 October 2013

Received: 01 June 2013

Published in TODAES Volume 19, Issue 2

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Cited By

Eslami FWilton S(2018)Rapid Triggering Capability Using an Adaptive Overlay during FPGA DebugACM Transactions on Design Automation of Electronic Systems10.1145/324104523:6(1-25)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3241045
Khan HKamal AGoehringer D(2018)An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_35(433-445)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_35
Lettnin DWinterholer M(2017)An Overview About Debugging and Verification Techniques for Embedded SoftwareEmbedded Software Verification and Debugging10.1007/978-1-4614-2266-2_1(1-18)Online publication date: 19-Apr-2017
https://doi.org/10.1007/978-1-4614-2266-2_1
Tessier RPocek KDeHon A(2015)Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2386883103:3(332-354)Online publication date: Mar-2015
https://doi.org/10.1109/JPROC.2014.2386883
Tamiya YTomita YIchiba TKawamura K(2015)Data-triggered breakpoint for in-circuit debug without re-implementation2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293997(1-4)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293997

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