research-article

A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications

Authors:

Nicola Bombieri,

Sara VincoAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 20, Issue 3

Article No.: 36, Pages 1 - 26

https://doi.org/10.1145/2720019

Published: 24 June 2015 Publication History

Abstract

With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW applications rather than dedicated HW is an increasing trend to fully exploit the computation power provided by the MPSoC CPUs. On the other hand, whole libraries of IP blocks are available as RTL descriptions, most of them without a corresponding high-level SW implementation. In this context, this article presents a methodology to automatically generate SW applications in C++, by starting from existing RTL IPs implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate implementation details typical of HW descriptions (such as cycle-accurate functionality and data types) to guarantee relevant performance of the generated code. The experimental results show that, in many cases, the C++ code automatically generated in a few seconds with the proposed methodology is as efficient as the corresponding code manually implemented from scratch.

References

[1]

ALDEC. 2014. HES-DVM. http://aldec.com (2014).

[2]

Gasser Ayad, Andrea Acquaviva, Enrico Macii, Brahim Sahbi, and Romain Lemaire. 2013. HW-SW integration for energy-efficient/variability-aware computing. In Proceedings of the ACM/IEEE Conference on Design, Automation and Test in Europe (DATE'13). 607--611.

Digital Library

[3]

Nicola Bombieri, Franco Fummi, and Graziano Pravadelli. 2010. Abstraction of RTL IPs into embedded software. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC'10). 24--29.

Digital Library

[4]

Nicola Bombieri, Franco Fummi, Graziano Pravadelli, and Joao Marques-Silva. 2007. Towards equivalence checking between TLM and RTL models. In Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE'07). 113--122.

Digital Library

[5]

Carbon Design Systems. 2014. Carbon Model Studio. http://carbondesignsystems.com/.

[6]

Kwang-Ting Cheng and A. S. Krishnakumar. 1996. Automatic generation of functional vectors using the extended finite state machine model. ACM Trans. Des. Autom. Electron. Syst. 1, 1, 57--79.

Digital Library

[7]

DIE.NET. 2014. FreeHDL-V2CC. http://linux.die.net/man/1/freehdl-v2cc.

[8]

Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, and Michael Hull. 2007. Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. In Proceedings of the ACM/IEEE Conference on Design, Automation and Test in Europe (DATE'07). 767--772.

Digital Library

[9]

EDALAB. 2014. HIFSuite: Tools for HDL code conversion and manipulation. http://hifsuite.edalab.it.

[10]

Stephen A. Edwards. 2003. Tutorial: Compiling concurrent languages for sequential processors. ACM Trans. Des. Autom. Electron. Syst. 8, 2, 141--187.

Digital Library

[11]

Freescale. 2009. Embedded multicore: An introduction. http://www.freescale.com/files/32bit/doc/ref_manual/EMBMCRM.pdf.

[12]

Robert S. French, Monica S. Lam, Jeremy R. Levitt, and Kunle Olukotun. 1995. A general method for compiling event-driven simulations. In Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference (DAC'95). 151--156.

Digital Library

[13]

Abdelaziz Guerrouat and Harald Richter. 2006. A component-based specification approach for embedded systems using FDTs. ACM SIGSOFT Softw. Eng. Notes 31, 2, 14--18.

Digital Library

[14]

Craig Hansen. 1988. Hardware logic simulation by compilation. In Proceedings of the 25th Annual ACM/IEEE Design Automation Conference (DAC'88). 712--715.

Digital Library

[15]

F. Herrera, H. Posadas, P. Sanchez, and E. Villar. 2003. Systematic embedded software generation from SystemC. In Proceedings of the ACM/IEEE Conference on Design, Automation and Test in Europe (DATE'03). 142--147.

Digital Library

[16]

Icarus. 2014. Icarus Verilog. http://iverilog.icarus.com.

[17]

ITRS. 2011. International Technology Roadmap for Semiconductors: 2011. http://www.itrs.net/Links/2011ITRS/2011Chapters/2011SysDrivers.pdf.

[18]

Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima, Teruo Higashino, and Kenichi Taniguchi. 2000. Hardware implementation of communication protocols modeled by concurrent efsms with multi-way synchronization. In Proceedings of the ACM/IEEE Design Automation Conference (DAC'00). 762--767.

Digital Library

[19]

T. John Koo, Bruno Sinopoli, Alberto Sangiovanni-Vincentelli, and Shankar Sastry. 1999. A formal approach to reactive system design: Unmanned aerial vehicle flight management system design example. In Proceedings of the IEEE International Symposium on Computer Aided Control System Design. 522--527.

[20]

Grant Martin. 2006. Overview of the MPSoC design challenge. In Proceedings of the 43rd Annual Design Automation Conference (DAC'06). 274--279.

Digital Library

[21]

Mentor Graphics. 1994. Introduction to VHDL. http://pages.cs.wisc.edu/sohi/cs552/Handouts/MentorDocs/mentor_graphics_introduction_to_VHDL.pdf.

[22]

OSCI. 2002. Functional specification for SystemC 2.0. http://www.systemc.org.

[23]

OSTATIC. 2014. VHDLC. http://ostatic.com.

[24]

Kalyan Saladi, Harikumar Somakumar, and Mahadevan Ganapathi. 2013. Concurrency-aware compiler optimizations for hardware description languages. ACM Trans. Des. Autom. Electron. Syst. 18, 1, Article 10, 10:1--10:16 pages.

Digital Library

[25]

W. Stoye, D. Greaves, N. Richards, and J. Green. 2003. Using RTL-to-C++ translation for large SoC concurrent engineering: A case study. IEEE Electronics Syst. Softw. 1, 1, 20--25.

[26]

SystemC. 2006. Standard SystemC Language Reference Manual. http:///ieeexplore.ieee.org.

[27]

ToucHMore. 2013. Automatic customizable tool-chain for heterogeneous multicore platform software development (FP7 ICT-288166). http://www.touchmore-project.eu.

[28]

VERILATOR. 2014. Verilator - Convert Verilog code to C++/SystemC. http://www.veripool.org/wiki/verilator.

[29]

Verilog. 2006. Standard for Verilog Hardware Description Language. http:///ieeexplore.ieee.org.

[30]

VHDL. 1994. Standard VHDL Language Reference Manual. http:///ieeexplore.ieee.org.

[31]

W. Wolf, A. A. Jerraya, and G. Martin. 2008. Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27, 10, 1701--1713.

Digital Library

[32]

Abdelkrim Zitouni, Sami Badrouchi, and Rached Tourki. 2006. Communication architecture synthesis for multi-bus SoC. J. Computer Science 2, 1, 63--71.

Cited By

Zeng YGupta AMalik S(2022)Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774527(460-465)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774527
Vinco SBombieri NPagliari DFummi FMacii EPoncino M(2019)A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing MonitorsACM Transactions on Design Automation of Electronic Systems10.1145/330856524:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3308565
Mahapatra ASchafer B(2019)Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702355(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702355
Show More Cited By

Index Terms

A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

Recommendations

Abstraction of RTL IPs into embedded software
DAC '10: Proceedings of the 47th Design Automation Conference

High performance provided by multi-processor System-on-Chips (MPSoCs) often induces designers to choose customized processors to execute specific functions rather than using dedicated hardware. On the other hand, reuse of pre-designed and pre-verified ...
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may ...
Automatic RTL Test Generation from SystemC TLM Specifications

SystemC transaction-level modeling (TLM) is widely used to enable early exploration for both hardware and software designs. It can reduce the overall design and validation effort of complex system-on-chip (SOC) architectures. However, due to lack of ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 20, Issue 3

June 2015

345 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2796316

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 24 June 2015

Accepted: 01 January 2015

Revised: 01 September 2014

Received: 01 March 2014

Published in TODAES Volume 20, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

EC co-funded SMAC (SMArt Systems Co-Design)

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
156
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Reflects downloads up to 03 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zeng YGupta AMalik S(2022)Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774527(460-465)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774527
Vinco SBombieri NPagliari DFummi FMacii EPoncino M(2019)A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing MonitorsACM Transactions on Design Automation of Electronic Systems10.1145/330856524:3(1-23)Online publication date: 11-Mar-2019
https://dl.acm.org/doi/10.1145/3308565
Mahapatra ASchafer B(2019)Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702355(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702355
Mahapatra ASchafer B(2019)VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space ExplorationIntegration10.1016/j.vlsi.2018.03.01164(1-12)Online publication date: Jan-2019
https://doi.org/10.1016/j.vlsi.2018.03.011

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents