Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
research-article

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation

Published: 24 June 2015 Publication History

Abstract

Globalization of the integrated circuit design and manufacturing flow has successfully ameliorated design complexity and fabrication cost challenges, and helped deliver cost-effective products while meeting stringent time-to-market requirements. On the flip side, it has resulted in various forms of security vulnerabilities in the supply chain that involves designers, fabs, test facilities, and distributors until the end-product reaches customers. One of the biggest threats to semiconductor industry today is the entry of aged, reject, or cloned parts, that is, counterfeit chips, into the supply chain, leading to annual revenue losses in the order of billions of dollars. While traceability of chips between trusted parties can help monitor the supply chain at various points in the flow, existing solutions are in the form of integrating costly hardware units on chip, or utilizing easy-to-circumvent inspection-based detection techniques. In this article, we propose a technique for adaptive unique ID generation that leverages process variations, enabling chip traceability. The proposed method stimulates digital chips with an analog signal from the supply lines, which serve as primary inputs to each gate in the signal path. Using a sinusoidal signal that exercises the transistors as gain components, we create a chip-specific response that can be post-processed into a digital ID. The proposed technique enables quick and cost-effective authenticity validation that requires no on-chip hardware support. Our simulation and experimentation on actual chips show that the proposed technique is capable of generating unique IDs even in the presence of environmental noise.

References

[1]
Y. Alkabani and F. Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the USENIX Security Symposium (SS'07). 291--306.
[2]
F. Armknecht. 2011. A formalization of the security features of physical functions. In Proceedings of the IEEE Symposium on Security and Privacy (SP'11). 397--412.
[3]
R. S. Chakraborty and S. Bhunia. 2009a. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28, 10, 1493--1502.
[4]
R. S. Chakraborty and S. Bhunia. 2009b. Security against hardware Trojan through a novel application of design obfuscation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'09). 113--116.
[5]
K. Chatterjee and D. Das. 2007. Semiconductor manufacturers efforts to improve trust in the electronic part supply chain. IEEE Trans. Compon. Packag. Technol. 30, 3, 547--549.
[6]
W. Chou. 2002. Inside SSL: The secure socket layer protocol. IEEE IT Profess. 4, 4, 47--52.
[7]
DIGITIMES. 2012. Trends in the global IC design service market. http://www.digitimes.com/Reports/Report.asp?datepublish=2012/3/13n\&pages=RSn\&seq=400n\&read=toc.
[8]
B. Gassend. 2002. Silicon physical random functions. In Proceedings of the ACM Conference on Computer and Communications Security (CCS'02). 148--160.
[9]
W., Griffin A. Raghunathan, and K. Roy. 2012. CLIP: Circuit level IC protection through direct injection of process variations. IEEE Trans. VLSI. Syst. 20, 5, 791--803.
[10]
U. Guin, X. Zhang, D. Forte, and M. Tehranipoor. 2014. Low-cost on-chip structures for combating die and IC recycling. In Proceedings of the IEEE/ACM Design Automation Conference (DAC'14).
[11]
D. E. Holcomb, W. P. Burleson, and K. Fu. 2009. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE J. Solid-State Circ. 58, 9, 1198--1210.
[12]
W. Hu, D. Mu, J. Oberg, B. Mao, M. Tiwari, T. Sherwood, and R. Kastner. 2014. Gate-level information flow tracking for security lattices. ACM Trans. Des. Autom. Electron. Syst. 20, 1.
[13]
K. Huang, J. Carulli, and Y. Makris. 2012. Path-delay fingerprinting for identification of recovered ICs. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'12). 7--12.
[14]
IARPA. 2011. Trusted integrated circuits program. https://www.fbo.gov/utils/view?id=b8be3d2c5d5babbdffc6975c370247a6.
[15]
ITRS. 2011. International technology roadmap for semiconductors. http://www.itrs.net/Links/2011ITRS/Home2011.htm.
[16]
N. Kae-Nune and S. Pesseguier. 2013. Qualification and testing process to implement anti-counterfeiting technologies into IC package. In Proceedings of the IEEE/ACM Conference on Design Automation Test in Europe (DATE'13). 1131--1136.
[17]
J. Keane, X. Wang, P. Jain, and C. H. Kim. 2014. On-chip silicon odometers for circuit aging characterization. In Bias Temperature Instability for Devices and Circuits, Springer, New York, 679--717.
[18]
F. Koushanfar. 2012. Can EDA combat the rise of electronic counterfeiting? In Proceedings of the IEEE/ACM Design Automation Conference (DAC'12). 133--138.
[19]
F. Liu, P. K. Nikolov, and S. Ozev. 2006. Parametric fault diagnosis for analog circuits using a Bayesian framework. In Proceedings of the IEEE VLSI Test Symposium.
[20]
A. Maiti, V. Gunreddy, and P. Schaumont. 2012. A systematic method to evaluate and compare the performance of physical unclonable functions. In Embedded System Design with FPGAs, Springer, New York, 245--267.
[21]
M. Majzoobi, F. Koushanfar, and M. Potkonjak. 2009. Techniques for design and implementation of secure reconfigurable PUFs. ACM Trans. Reconfig. Technol. Syst. 2, 1, 1--33.
[22]
A. Oppenheim, A. Willsky, H. Nawab, and S. Hamid. 1996. Signal and Systems 2nd Ed. Prentice-Hall.
[23]
M. Pecht and S. Tiku. 2006. Bogus: Electronic manufacturing and consumers confront a rising tide of counterfeit electronics. IEEE Spectrum 43, 5, 37--46.
[24]
M. Plotkin. 1960. Binary codes with specified minimum distance. IRE Trans. Inf. Theory 6, 1, 445--450.
[25]
J. Rajendran, Y. Pino, and O. Sinanoglu. 2012a. Logic encryption: A fault analysis perspective. In Proceedings of the IEEE/ACM Conference on Design Automation Test in Europe (DATE'12). 953--958.
[26]
J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012b. Security analysis of logic obfuscation. In Proceedings of the IEEE/ACM Design Automation Conference (DAC'12). 83--89.
[27]
P. S. Ravikanth. 2001. Physical one-way functions--Doctoral dissertation. http://cba.mit.edu/docs/theses/01.03.pappuphd.powf.pdf.
[28]
S. Rosenblatt, D. Fainstein, A. Cestero, and J. Safran. 2013. Field tolerant dynamic intrinsic chip ID using 32 nm high-/metal gate SOI embedded DRAM. IEEE J. Solid-State Circ. 48, 4, 940--947.
[29]
R. Roth. 2006. Introduction to Coding Theory. Cambridge University Press.
[30]
J. Roy, F. Koushanfar, and I. Markov. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the IEEE/ACM Conference on Design Automation Test in Europe (DATE'08). 1069--1074.
[31]
U. Ruhrmair, S. Devadas, and F. Koushanfar. 2011. Security based on physical unclonability and disorder. In Introduction to Hardware Security and Trust, Springer, New York, 65--102.
[32]
SEMI. 2008. www.semi.org/en/Press/P043775.
[33]
Y. Su, J. Holleman, and B. Otis. 2008. A digital 1.6 pJ/bit chip identification circuit using process variations. IEEE J. Solid-State Circ. 43, 1, 69--77.
[34]
K. Tae-Hyoung, R. Persaud, and C. H. Kim. 2008. Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE J. Solid-State Circ. 43, 4, 874--880.
[35]
M. Tehranipoor. 2013. Integrated Circuit Authentication: Hardware Trojans and Counterfeit Detection. Springer.
[36]
M. Wang, A. Yates, and I. L. Markov. 2014. SuperPUF: Integrating heterogeneous physically unclonable functions. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14). 454--461.
[37]
J. Wendt and M. Potkonjak. 2014. Hardware obfuscation using PUF-based logic. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'14). 270--277.
[38]
X. Zhang, N. Tuzzio, and M. Tehranipoor. 2012a. Identification of recovered ICs using fingerprintings from a light-weight on-chip sensor. In Proceedings of the IEEE/ACM Design Automation Conference (DAC'12). 703--708.
[39]
X. Zhang, K. Xiao, and M. Tehranipoor. 2012b. Path-delay fingerprinting for identification of recovered ICs. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'12). 13--18.
[40]
W. Zhao and Y. Cao. 2006. New generation of predictive technology model for sub-45nm early design exploration. IEEE Trans. Electron. Dev. 53, 11, 2816--2823.
[41]
Y. Zheng, A. Basak, and S. Bhunia. 2014. CACI: Dynamic current analysis towards robust recycled chip identification. In Proceedings of the IEEE/ACM Design Automation Conference (DAC'14).

Cited By

View all
  • (2019)Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC ComponentsACM Transactions on Embedded Computing Systems10.1145/330127918:2(1-26)Online publication date: 18-Mar-2019

Index Terms

  1. Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation

          Recommendations

          Comments

          Information & Contributors

          Information

          Published In

          cover image ACM Transactions on Design Automation of Electronic Systems
          ACM Transactions on Design Automation of Electronic Systems  Volume 20, Issue 3
          June 2015
          345 pages
          ISSN:1084-4309
          EISSN:1557-7309
          DOI:10.1145/2796316
          • Editor:
          • Naehyuck Chang
          Issue’s Table of Contents
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Journal Family

          Publication History

          Published: 24 June 2015
          Accepted: 01 February 2015
          Revised: 01 January 2015
          Received: 01 November 2014
          Published in TODAES Volume 20, Issue 3

          Permissions

          Request permissions for this article.

          Check for updates

          Author Tags

          1. Hardware security
          2. ID generation
          3. counterfeiting

          Qualifiers

          • Research-article
          • Research
          • Refereed

          Funding Sources

          Contributors

          Other Metrics

          Bibliometrics & Citations

          Bibliometrics

          Article Metrics

          • Downloads (Last 12 months)5
          • Downloads (Last 6 weeks)0
          Reflects downloads up to 06 Oct 2024

          Other Metrics

          Citations

          Cited By

          View all
          • (2019)Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC ComponentsACM Transactions on Embedded Computing Systems10.1145/330127918:2(1-26)Online publication date: 18-Mar-2019

          View Options

          Get Access

          Login options

          Full Access

          View options

          PDF

          View or Download as a PDF file.

          PDF

          eReader

          View online with eReader.

          eReader

          Media

          Figures

          Other

          Tables

          Share

          Share

          Share this Publication link

          Share on social media