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Locality-Aware Network Utilization Balancing in NoCs

Published: 02 December 2015 Publication History
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  • Abstract

    Hierarchical and multi-network networks-on-chip (NoCs) have been proposed in the literature to improve the energy- and performance-efficient scalability of the traditional flat-mesh NoC architecture. Theoretically, based on a small-world network-based analysis, traditional hierarchical NoCs are expected to provide good scalability. However, the traditional theoretical analysis (e.g. for small-worldness) does not take into account the congestion phenomenon experienced in such networks. Counterintuitively, as shown in this work, breaking the hierarchy in traditional hierarchical NoCs and utilizing the proposed locality-aware network utilization (NU) balancing technique performs better. This improvement in performance is observed through experimental analysis, which is contrasted with the theoretical analysis that does not account for congestion. In addition to the novelties for hierarchical networks, the application of the proposed locality-aware NU balancing scheme is extended to multi-network NoC topologies (with already separated networks). Results of the analysis show the superiority of applying the locality-aware NU balancing technique for a throughput and energy-efficient scaling of the multi-network NoC architectures, much like those of the hierarchical NoCs. For instance, for a NoC with 1024 nodes, the proposed NU balancing technique provides up to 95% higher throughput efficiency and consumes up to 29% less energy per flit compared to the best NoC topology without the NU balancing technique. The analysis also helps to render the choice of a NoC topology for traffic patterns varying in locality and nonlocality on exascale computing CMPs.

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    Cited By

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    • (2016)Energy aware routing of multi-level Network-on-Chip traffic2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753330(480-486)Online publication date: Oct-2016

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    1. Locality-Aware Network Utilization Balancing in NoCs

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      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 21, Issue 1
      November 2015
      464 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2852253
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 02 December 2015
      Accepted: 01 March 2015
      Revised: 01 July 2013
      Received: 01 January 2013
      Published in TODAES Volume 21, Issue 1

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      Author Tags

      1. Network-on-chip (NoC)
      2. hierarchical networks
      3. network utilization balancing

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      • (2016)Energy aware routing of multi-level Network-on-Chip traffic2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753330(480-486)Online publication date: Oct-2016

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