research-article

Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing

Authors:

Youngsun HanAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 2

Article No.: 16, Pages 1 - 21

https://doi.org/10.1145/3131241

Published: 05 October 2017 Publication History

Abstract

Recently, scaling down dynamic random access memory (DRAM) has become more of a challenge, with more faults than before and a significant degradation in yield. To improve the yield in DRAM, a redundancy repair technique with intra-subarray replacement has been extensively employed to replace faulty elements (i.e., rows or columns with defective cells) with spare elements in each subarray. Unfortunately, such technique cannot efficiently handle a biased distribution of faulty cells because each subarray has a fixed number of spare elements. In this article, we propose a novel redundancy repair technique that uses a hashing method to solve this problem. Our hashing technique reorganizes replacement regions by changing the way in which their replacement information is referred, thus making faulty cells become evenly distributed to the regions. We also propose a fast repair algorithm to find the best hash function among all possible candidates. Even if our approach requires little hardware overhead, it significantly improves the yield when compared with conventional redundancy techniques. In particular, the results of our experiment show that our technique saves spare elements by about 57% and 55% for a yield of 99% at BER 1e-6 and 5e-7, respectively.

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Cited By

Lee SLee HLee JKang S(2025)A New Pipelined Output Data Reducer of BOST for Improved ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344525844:2(765-776)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3445258
Choi KJun JKim MKim S(2019)Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy RepairACM Transactions on Design Automation of Electronic Systems10.1145/333985124:5(1-31)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.1145/3339851
Jun JPaik YMin GKim SHan Y(2019)Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory ManagementACM Transactions on Design Automation of Electronic Systems10.1145/332907924:4(1-25)Online publication date: 5-Jun-2019
https://dl.acm.org/doi/10.1145/3329079

Index Terms

Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing
1. Hardware
  1. Hardware test
    1. Memory test and repair
  2. Robustness
    1. Fault tolerance
      1. Redundancy

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 2

March 2018

341 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3149546

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2017 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 October 2017

Accepted: 01 August 2017

Revised: 01 August 2017

Received: 01 March 2007

Published in TODAES Volume 23, Issue 2

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Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC
Development of Processing in Memory Architecture and Parallel Processing for Data Bounding Applications
IT R8D program of MOTIE/KEIT

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Cited By

Lee SLee HLee JKang S(2025)A New Pipelined Output Data Reducer of BOST for Improved ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344525844:2(765-776)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3445258
Choi KJun JKim MKim S(2019)Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy RepairACM Transactions on Design Automation of Electronic Systems10.1145/333985124:5(1-31)Online publication date: 10-Jul-2019
https://dl.acm.org/doi/10.1145/3339851
Jun JPaik YMin GKim SHan Y(2019)Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory ManagementACM Transactions on Design Automation of Electronic Systems10.1145/332907924:4(1-25)Online publication date: 5-Jun-2019
https://dl.acm.org/doi/10.1145/3329079

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