research-article

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs

Authors:

Chun Jason Xue,

Edwin ShaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 2

Article No.: 15, Pages 1 - 29

https://doi.org/10.1145/3131850

Published: 05 October 2017 Publication History

Abstract

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I/O performance will be significantly impacted because of the access conflict between them. In this work, in order to improve the access conflict induced performance degradation, a novel access conflict minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.

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Cited By

Cai ZTang CLi MTrahay FLi JSha ZWu JYang FLiao J(2023)Re-aligning Across-page Requests for Flash-based Solid-state DrivesProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605652(736-745)Online publication date: 7-Aug-2023
https://dl.acm.org/doi/10.1145/3605573.3605652
Long LHuang JGao CLiu DLiu RJiang Y(2023)ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321039042:6(1824-1837)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3210390
Sun HDai SHuang JYue YQin X(2023)DAC: A dynamic active and collaborative cache management scheme for solid state disksJournal of Systems Architecture10.1016/j.sysarc.2023.102896140(102896)Online publication date: Jul-2023
https://doi.org/10.1016/j.sysarc.2023.102896
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Index Terms

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
  2. Embedded and cyber-physical systems
    1. Embedded systems
      1. Embedded software
2. Hardware
  1. Communication hardware, interfaces and storage
    1. External storage

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 2

March 2018

341 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3149546

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2017 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 October 2017

Accepted: 01 July 2009

Revised: 01 July 2009

Received: 01 January 2007

Published in TODAES Volume 23, Issue 2

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National 863 Programs
NSFC
Fundamental Research Funds for the Central Universities
Huawei Innovation Research Program (HIRP)
Fundamental Research Funds for Graduate Scientific Research and Innovation Foundation of Chongqing, China

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Cited By

Cai ZTang CLi MTrahay FLi JSha ZWu JYang FLiao J(2023)Re-aligning Across-page Requests for Flash-based Solid-state DrivesProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605652(736-745)Online publication date: 7-Aug-2023
https://dl.acm.org/doi/10.1145/3605573.3605652
Long LHuang JGao CLiu DLiu RJiang Y(2023)ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321039042:6(1824-1837)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3210390
Sun HDai SHuang JYue YQin X(2023)DAC: A dynamic active and collaborative cache management scheme for solid state disksJournal of Systems Architecture10.1016/j.sysarc.2023.102896140(102896)Online publication date: Jul-2023
https://doi.org/10.1016/j.sysarc.2023.102896
Peng GLi JZhao MLi MSha ZHuang MCai Z(2022)Delaying Large Write Requests to Trade off I/O Performance and Long-tail Latency in SSDs2022 IEEE 24th Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys)10.1109/HPCC-DSS-SmartCity-DependSys57074.2022.00196(1249-1254)Online publication date: Dec-2022
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Sun HCheng XZhang CYue YQin X(2022)HIPA: A hybrid load balancing method in SSDs for improved parallelism performanceJournal of Systems Architecture10.1016/j.sysarc.2022.102705131(102705)Online publication date: Oct-2022
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Sha ZLi JSong LTang JHuang MCai ZQian LLiao JLiu Z(2021)Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDsACM Transactions on Architecture and Code Optimization10.1145/346043318:4(1-25)Online publication date: 31-Dec-2021
https://doi.org/10.1145/3460433
Xu XCai ZLiao JIshiakwa Y(2020)Frequent Access Pattern-based Prefetching Inside of Solid-State Drives2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116382(720-725)Online publication date: Mar-2020
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Gao CShi LLiu KXue CYang JZhang Y(2020)Boosting the Performance of SSDs via Fully Exploiting the Plane Level ParallelismIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2020.298789431:9(2185-2200)Online publication date: 1-Sep-2020
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Choi JKim KKwak J(2020)WPA: Write Pattern Aware Hybrid Disk Buffer Management for Improving Lifespan of NAND Flash MemoryIEEE Transactions on Consumer Electronics10.1109/TCE.2020.298161866:2(193-202)Online publication date: May-2020
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Wu CChang YYang MKuo T(2020)When Storage Response Time Catches Up with Overall Context Switch Overhead, What is NextIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012322(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012322
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