research-article

Routable and Matched Layout Styles for Analog Module Generation

Authors:

Shigetoshi NakatakeAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 23, Issue 4

Article No.: 47, Pages 1 - 17

https://doi.org/10.1145/3182169

Published: 28 June 2018 Publication History

Abstract

Two¹ novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common-centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing-based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well-arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion-sharing of MOS transistors and less routing layer usage for common-centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two-stage operating amplifier and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.

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Cited By

Liu BWang PLiu XZhang L(2024)Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulatorMicroelectronics Journal10.1016/j.mejo.2023.106045143(106045)Online publication date: Jan-2024
https://doi.org/10.1016/j.mejo.2023.106045
Liu BZhang WDuan WMeng Q(2023)BP Neural Network Modeling and Solving Acceleration of Analog ICsCircuits, Systems, and Signal Processing10.1007/s00034-023-02443-x42:12(7023-7044)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1007/s00034-023-02443-x
Liu BZhang WLi KDuan WLiu MMeng Q(2023)High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICsCircuits, Systems, and Signal Processing10.1007/s00034-022-02219-942:4(1984-2006)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1007/s00034-022-02219-9
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Index Terms

Routable and Matched Layout Styles for Analog Module Generation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
    1. Analog and mixed-signal circuits
      1. Analog and mixed-signal circuit synthesis

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 23, Issue 4

Special Section on Advances in Physical Design Automation and Regular Papers

July 2018

316 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3217208

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 June 2018

Accepted: 01 January 2018

Revised: 01 October 2017

Received: 01 May 2017

Published in TODAES Volume 23, Issue 4

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Funding Sources

National Natural Science Foundation of China
China Postdoctoral Science Foundation
Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry

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Cited By

Liu BWang PLiu XZhang L(2024)Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulatorMicroelectronics Journal10.1016/j.mejo.2023.106045143(106045)Online publication date: Jan-2024
https://doi.org/10.1016/j.mejo.2023.106045
Liu BZhang WDuan WMeng Q(2023)BP Neural Network Modeling and Solving Acceleration of Analog ICsCircuits, Systems, and Signal Processing10.1007/s00034-023-02443-x42:12(7023-7044)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1007/s00034-023-02443-x
Liu BZhang WLi KDuan WLiu MMeng Q(2023)High-Efficiency Multiobjective Synchronous Modeling and Solution of Analog ICsCircuits, Systems, and Signal Processing10.1007/s00034-022-02219-942:4(1984-2006)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1007/s00034-022-02219-9
Yenuchenko MPilipko M(2022)A Metric of Elements Placement Properties for Nonlinearity Reduction Prediction in Binary DACs2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus54750.2022.9755486(215-219)Online publication date: 25-Jan-2022
https://doi.org/10.1109/ElConRus54750.2022.9755486
Yenuchenko MPilipko M(2022)Comparative Analysis of Switching Schemes for 8-bit Arrays in Binary DACs2022 International Conference on Electrical Engineering and Photonics (EExPolytech)10.1109/EExPolytech56308.2022.9950860(40-43)Online publication date: 20-Oct-2022
https://doi.org/10.1109/EExPolytech56308.2022.9950860
Liu BWang PLi KXu BZhang JZhang L(2022)A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layoutIntegration, the VLSI Journal10.1016/j.vlsi.2022.06.00387:C(74-81)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.06.003
Yenuchenko MPilipko M(2020)Comparative Analysis of Switching Schemes for 6-bit Arrays in Binary DACs2020 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech)10.1109/EExPolytech50912.2020.9243952(71-75)Online publication date: 15-Oct-2020
https://doi.org/10.1109/EExPolytech50912.2020.9243952
Liu BHuang ZZhang JLiu MMeng Q(2020)A full-transistor fine-grain multilevel delay element with compact regularity layoutAnalog Integrated Circuits and Signal Processing10.1007/s10470-020-01588-y103:1(163-172)Online publication date: 3-Feb-2020
https://dl.acm.org/doi/10.1007/s10470-020-01588-y
GENG CLIU BNAKATAKE S(2019)Density Optimization for Analog Layout Based on Transistor-ArrayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E102.A.1720E102.A:12(1720-1730)Online publication date: 1-Dec-2019
https://doi.org/10.1587/transfun.E102.A.1720

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