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A Survey on PCM Lifetime Enhancement Schemes

Published: 30 August 2019 Publication History

Abstract

Phase Change Memory (PCM) is an emerging memory technology that has the capability to address the growing demand for memory capacity and bridge the gap between the main memory and the secondary storage. As a resistive memory, PCM is able to store data based on its resistance values. The wide resistance range of PCM makes it possible to store even multiple bits per cell (MLC) rather than a single bit per cell (SLC). Unfortunately, PCM cells suffer from short lifetime. That means PCM cells could tolerate a limited number of write operations, and afterward they tend to permanently stick at a constant value.
Limited lifetime is an issue related to PCM memory; hence, in recent years, many studies have been conducted to prolong PCM lifetime. These schemes have vast variety and are applied at different architectural levels. In this survey, we review the important works of such schemes to give insights to those starting to research on non-volatile memories (NVMs). These schemes are not limited to PCM and are applicable on other NVM technologies due to the similarities between them and the generality of lifetime-prolonging schemes.

Supplementary Material

a76-rashidi-supp.pdf (rashidi.zip)
Supplemental movie, appendix, image and software files for, A Survey on PCM Lifetime Enhancement Schemes

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Published In

cover image ACM Computing Surveys
ACM Computing Surveys  Volume 52, Issue 4
July 2020
769 pages
ISSN:0360-0300
EISSN:1557-7341
DOI:10.1145/3359984
  • Editor:
  • Sartaj Sahni
Issue’s Table of Contents
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 August 2019
Accepted: 01 May 2019
Revised: 01 May 2019
Received: 01 February 2018
Published in CSUR Volume 52, Issue 4

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Author Tags

  1. Stuck-at faults
  2. Wear-Leveling
  3. approximate memory
  4. cache management
  5. hard failures
  6. resistance drift

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  • (2023)Relieving Compression-Induced Local Wear on Non-Volatile Memory Block via Sliding WritesMicromachines10.3390/mi1403056814:3(568)Online publication date: 27-Feb-2023
  • (2023)Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071093(964-976)Online publication date: Feb-2023
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  • (2023)Nonvolatile Memory Technologies: Characteristics, Deployment, and Research ChallengesFrontiers of Quality Electronic Design (QED)10.1007/978-3-031-16344-9_4(137-173)Online publication date: 12-Jan-2023
  • (2022)A Metadata Prefetching Mechanism for Hybrid Memory ArchitecturesIEICE Transactions on Electronics10.1587/transele.2021LHP0004E105.C:6(232-243)Online publication date: 1-Jun-2022
  • (2022)MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memoryACM Journal on Emerging Technologies in Computing Systems10.1145/348582418:3(1-24)Online publication date: 29-Jan-2022
  • (2022)Gray counters for non-volatile memoriesMemories - Materials, Devices, Circuits and Systems10.1016/j.memori.2022.1000142(100014)Online publication date: Oct-2022
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