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Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks

Published: 22 November 2019 Publication History
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  • Abstract

    Field Programmable Gate Arrays (FPGAs) have become an attractive choice for diverse applications due to their reconfigurability and unique security features. However, designs mapped to FPGAs are prone to malicious modifications or tampering of critical functions. Besides, targeted modifications have demonstrably compromised FPGA implementations of various cryptographic primitives. Existing security measures based on encryption and authentication can be bypassed using their side-channel vulnerabilities to execute bitstream tampering attacks. Furthermore, numerous resource-constrained applications are now equipped with low-end FPGAs, which may not support power-hungry cryptographic solutions. In this article, we propose a novel obfuscation-based approach to achieve strong resistance against both random and targeted pre-configuration tampering of critical functions in an FPGA design. Our solution first identifies the unique structural and functional features that separate the critical function from the rest of the design using a machine learning guided framework. The selected features are eliminated by applying appropriate obfuscation techniques, many of which take advantage of “FPGA dark silicon”—unused lookup table resources—to mask the critical functions. Furthermore, following the same obfuscation principle, a redundancy-based technique is proposed to thwart targeted, rule-based, and random tampering. We have developed a complete methodology and custom software toolflow that integrates with commercial tools. By applying the masking technique on a design containing AES, we show the effectiveness of the proposed framework in hiding the critical S-Box function. We implement the redundancy integrated solution in various cryptographic designs to analyze the overhead. To protect 16.2% critical component of a design, the proposed approach incurs an average area overhead of only 2.4% over similar redundancy-based approaches, while achieving strong security.

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    Cited By

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    • (2023)A Framework for Automated Exploration of Trojan Attack Space in FPGA NetlistsIEEE Transactions on Computers10.1109/TC.2023.326659272:10(2740-2751)Online publication date: Oct-2023
    • (2023)FPGA Bitstream Modification: Attacks and CountermeasuresIEEE Access10.1109/ACCESS.2023.333150711(127931-127955)Online publication date: 2023
    • (2023)FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream LevelJournal of Hardware and Systems Security10.1007/s41635-022-00130-y7:1(11-24)Online publication date: 16-Feb-2023
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    1. Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks

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      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 25, Issue 1
      January 2020
      299 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/3370083
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Publication History

      Published: 22 November 2019
      Accepted: 01 September 2019
      Revised: 01 July 2019
      Received: 01 December 2018
      Published in TODAES Volume 25, Issue 1

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      Author Tags

      1. FPGA bitstream tampering
      2. FPGA security
      3. Trojan prevention

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      Cited By

      View all
      • (2023)A Framework for Automated Exploration of Trojan Attack Space in FPGA NetlistsIEEE Transactions on Computers10.1109/TC.2023.326659272:10(2740-2751)Online publication date: Oct-2023
      • (2023)FPGA Bitstream Modification: Attacks and CountermeasuresIEEE Access10.1109/ACCESS.2023.333150711(127931-127955)Online publication date: 2023
      • (2023)FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream LevelJournal of Hardware and Systems Security10.1007/s41635-022-00130-y7:1(11-24)Online publication date: 16-Feb-2023
      • (2022)A Survey on FPGA Cybersecurity Design StrategiesACM Transactions on Reconfigurable Technology and Systems10.1145/356151516:2(1-33)Online publication date: 15-Sep-2022
      • (2022)FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level2022 IEEE European Test Symposium (ETS)10.1109/ETS54262.2022.9810466(1-2)Online publication date: 23-May-2022
      • (2021)Hardware Trojan Attack in Embedded MemoryACM Journal on Emerging Technologies in Computing Systems10.1145/342235317:1(1-28)Online publication date: 6-Jan-2021
      • (2020)Ten years of hardware Trojans: a survey from the attacker's perspectiveIET Computers & Digital Techniques10.1049/iet-cdt.2020.0041Online publication date: 12-Aug-2020

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