research-article

Machine Learning for Congestion Management and Routability Prediction within FPGA Placement

Authors:

Hannah Szentimrey,

Abeer Al-Hyari,

Jeremy Foxcroft,

Timothy Martin,

Gary Grewal, and

Shawki AreibiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 25, Issue 5

Article No.: 37, Pages 1 - 25

https://doi.org/10.1145/3373269

Published: 21 August 2020 Publication History

Abstract

Placement for Field Programmable Gate Arrays (FPGAs) is one of the most important but time-consuming steps for achieving design closure. This article proposes the integration of three unique machine learning models into the state-of-the-art analytic placement tool GPlace3.0 with the aim of significantly reducing placement runtimes. The first model, MLCong, is based on linear regression and replaces the computationally expensive global router currently used in GPlace3.0 to estimate switch-level congestion. The second model, DLManage, is a convolutional encoder-decoder that uses heat maps based on the switch-level congestion estimates produced by MLCong to dynamically determine the amount of inflation to apply to each switch to resolve congestion. The third model, DLRoute, is a convolutional neural network that uses the previous heat maps to predict whether or not a placement solution is routable. Once a placement solution is determined to be routable, further optimization may be avoided, leading to improved runtimes. Experimental results obtained using 372 benchmarks provided by Xilinx Inc. show that when all three models are integrated into GPlace3.0, placement runtimes decrease by an average of 48%.

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Cited By

Zheng SZou LXu PLiu SYu BWong M(2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323800
Zheng SZou LLiu SLin YYu BWong M(2023)Mitigating Distribution Shift for Congestion Optimization in Global Placement2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247660(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247660
Nie TZhao MZhu ZZhao KWang Z(2023)Estimating feature importance in circuit network using machine learningMultimedia Tools and Applications10.1007/s11042-023-16814-8Online publication date: 15-Sep-2023
https://doi.org/10.1007/s11042-023-16814-8
Show More Cited By

Index Terms

Machine Learning for Congestion Management and Routability Prediction within FPGA Placement
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs

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Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 25, Issue 5

Special Issue on Machine Learning

September 2020

303 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3409648

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 21 August 2020

Online AM: 07 May 2020

Accepted: 01 November 2019

Revised: 01 November 2019

Received: 01 June 2019

Published in TODAES Volume 25, Issue 5

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Cited By

Zheng SZou LXu PLiu SYu BWong M(2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323800
Zheng SZou LLiu SLin YYu BWong M(2023)Mitigating Distribution Shift for Congestion Optimization in Global Placement2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247660(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247660
Nie TZhao MZhu ZZhao KWang Z(2023)Estimating feature importance in circuit network using machine learningMultimedia Tools and Applications10.1007/s11042-023-16814-8Online publication date: 15-Sep-2023
https://doi.org/10.1007/s11042-023-16814-8
Purkayastha SMukherjee S(2023)PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed PackingCircuits, Systems, and Signal Processing10.1007/s00034-022-02159-442:2(801-827)Online publication date: 1-Feb-2023
https://dl.acm.org/doi/10.1007/s00034-022-02159-4
Baig IFarooq U(2022)Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement LearningElectronics10.3390/electronics1114224011:14(2240)Online publication date: 18-Jul-2022
https://doi.org/10.3390/electronics11142240
Pal DDeng CUstun EYu CZhang Z(2022)Machine Learning for Agile FPGA DesignMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_16(471-504)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_16
Tariq OShan JFloros GSotiriou CCasu MLazarescu MLavagno L(2021)High-Level Annotation of Routing Congestion for Xilinx Vivado HLS DesignsIEEE Access10.1109/ACCESS.2021.30674539(54286-54297)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3067453

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