research-article

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

Authors:

Krishnaswamy Nagaraj,

Leroy Winemberg,

Sule OzevAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 3

Article No.: 20, Pages 1 - 18

https://doi.org/10.1145/3427911

Published: 08 January 2021 Publication History

Abstract

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

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Cited By

Kashyap SRaghavendra CNatarajan SOzev S(2024)Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538672(1-7)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VTS60656.2024.10538672
Modala NBalasubramanian LParekhji ROzev S(2024)Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS60917.2024.10658865(693-697)Online publication date: 11-Aug-2024
https://doi.org/10.1109/MWSCAS60917.2024.10658865
Aksoy TModala NBalasubramanian LParekhji ROzev S(2024)Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling2024 IEEE European Test Symposium (ETS)10.1109/ETS61313.2024.10567425(1-6)Online publication date: 20-May-2024
https://doi.org/10.1109/ETS61313.2024.10567425
Show More Cited By

Index Terms

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
1. Hardware
  1. Hardware test
    1. Analog, mixed-signal and radio frequency test

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 3

May 2021

171 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3444754

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Copyright © 2021 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 08 January 2021

Accepted: 01 September 2020

Revised: 01 September 2020

Received: 01 March 2020

Published in TODAES Volume 26, Issue 3

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Cited By

Kashyap SRaghavendra CNatarajan SOzev S(2024)Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538672(1-7)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VTS60656.2024.10538672
Modala NBalasubramanian LParekhji ROzev S(2024)Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS60917.2024.10658865(693-697)Online publication date: 11-Aug-2024
https://doi.org/10.1109/MWSCAS60917.2024.10658865
Aksoy TModala NBalasubramanian LParekhji ROzev S(2024)Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling2024 IEEE European Test Symposium (ETS)10.1109/ETS61313.2024.10567425(1-6)Online publication date: 20-May-2024
https://doi.org/10.1109/ETS61313.2024.10567425
Saikiran MSekyere MGanji MChen D(2023)Digital Assisted Defect Detection Methods for Analog and Mixed Signal Circuits: An Overview2023 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS59469.2023.10297053(1-5)Online publication date: 22-Sep-2023
https://doi.org/10.1109/EWDTS59469.2023.10297053
Pavlidis AFaehn ELouerat MStratigopoulos H(2022)Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs2022 IEEE 40th VLSI Test Symposium (VTS)10.1109/VTS52500.2021.9794208(1-8)Online publication date: 25-Apr-2022
https://doi.org/10.1109/VTS52500.2021.9794208

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