Modeling layout tools to derive forward estimates of area and delay at the RTL level
Abstract
References
Index Terms
- Modeling layout tools to derive forward estimates of area and delay at the RTL level
Recommendations
A Reduction of Grid-Bag Layout to Auckland Layout
ASWEC '10: Proceedings of the 2010 21st Australian Software Engineering ConferenceMany major programming platforms support layout managers in Grid-bag style, where GUI elements can be placed on a rectangular grid. In Grid-bag layout mangers, cells of the underlying grid can be merged in order to create more complex layouts. In this ...
A study on the accuracy of minimum width transistor area in estimating FPGA layout area
Integrating reconfigurable fabrics in SOCs requires an accurate estimation of the layout area of the reconfigurable fabrics in order to properly optimize the architectural-level design of the fabrics and accommodate early floor-planning. This work ...
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures
Special Section on FCCM 2016 and Regular PapersThis work provides an evaluation on the accuracy of the minimum-width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts ...
Comments
Information & Contributors
Information
Published In
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Check for updates
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 512Total Downloads
- Downloads (Last 12 months)52
- Downloads (Last 6 weeks)9
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in