Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs
Authors: 
Benzheng Li, Xi Zhang, Hailong You, Zhongdong Qi, and Yuming ZhangAuthors Info & Claims
Benzheng Li, Xi Zhang, Hailong You, Zhongdong Qi, and Yuming ZhangAuthors Info & ClaimsArticle No.: 24, Pages 1 - 16
Abstract
Field-programmable gate arrays (FPGAs) have grown to be an important platform for integrated circuit design and hardware emulation. However, with the dramatic increase in design scale, it has become a key challenge to partition very large scale integration into multi-FPGA systems. Fast estimation of FPGA on-chip resource usage for individual sub-circuit blocks early in the circuit design flow will provide an essential basis for reasonable circuit partition. It will also help FPGA designers to tune the circuits in hardware description language. In this article, we propose a framework for fast estimation of the on-chip resources consumed by register transfer level (RTL) designs with machine learning methods. We extensively collect RTL designs as a dataset, extract features from the result of a parser tool and analyze their roles, and train a targeted three-stage ensemble learning model. A 5,513× speedup is achieved while having 27% relative absolute error. Although the effect is sufficient to support RTL circuit partition, we discuss how the estimation quality continues to be improved.
References
[1]
OpenCores. 1999. OpenCores Home Page. Retrieved October 6, 2022 from https://www.opencores.org.
[2]
Verific. 2000. Verific Design Automation. Retrieved October 6, 2022 from https://www.verific.com/.
[3]
GitHub. 2008. GitHub Home Page. Retrieved October 6, 2022 from https://www.github.com.
[4]
Keras. 2015. Keras Home Page. Retrieved October 6, 2022 from https://keras.io.
[5]
Xilinx. 2021. UG1399—Vitis High-Level Synthesis User Guide. Available at https://www.xilinx.com.
[6]
Xilinx. 2021. Vivado ML Standard Edition. Available at https://www.xilinx.com.
[7]
Mariette Awad and Rahul Khanna. 2015. Support vector regression. In Efficient Learning Machines. Springer, 67–80.
[8]
Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, and Lilian Bossuet. 2003. Fast prototyping of reconfigurable architectures from a C program. In Proceedings of the 2003 International Symposium on Circuits and Systems (ISCAS’03), Vol. 5. IEEE, Los Alamitos, CA.
[9]
Sebastien Bilavarn, Guy Gogniat, J.-L. Philippe, and Lilian Bossuet. 2006. Design space pruning through early estimations of area/delay tradeoffs for FPGA implementations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 10 (2006), 1950–1968.
[10]
C. Brandolese, W. Fornaciari, and F. Salice. 2004. An area estimation methodology for FPGA based designs at systemc-level. In Proceedings of the 41st Design Automation Conference.
[11]
Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, et al. 2020. Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: Industrial product. In Proceedings of the 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA’20). IEEE, Los Alamitos, CA, 52–64.
[12]
Tianqi Chen, Tong He, Michael Benesty, Vadim Khotilovich, Yuan Tang, Hyunsu Cho, Kailong Chen, et al. 2015. XGBoost: Extreme gradient boosting. R Package Version 0.4-2 1, 4 (2015), 1–4.
[13]
S. Dai, Y. Zhou, H. Zhang, E. Ustun, and Z. Zhang. 2018. Fast and accurate estimation of quality of results in high-level synthesis with machine learning. In Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’18).
[14]
T. G. Dietterich. 2000. An experimental comparison of three methods for constructing ensembles of decision trees: Bagging, boosting, and randomization. Machine Learning 40, 2 (2000), 139–157.
[15]
Harris Drucker, Christopher J. Burges, Linda Kaufman, Alex Smola, and Vladimir Vapnik. 1996. Support vector regression machines. In Advances in Neural Information Processing Systems 9 (1996).
[16]
Rolf Enzler, Tobias Jeger, Didier Cottet, and Gerhard Tröster. 2000. High-level area and performance estimation of hardware building blocks on FPGAs. In Proceedings of the International Workshop on Field Programmable Logic and Applications. 525–534.
[17]
Jerome Friedman, Trevor Hastie, and Robert Tibshirani. 2000. Additive logistic regression: A statistical view of boosting (with discussion and a rejoinder by the authors). Annals of Statistics 28, 2 (2000), 337–407.
[18]
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii. 2008. CHStone: A benchmark program suite for practical C-based high-level synthesis. In Proceedings of the 2008 IEEE International Symposium on Circuits and Systems. IEEE, Los Alamitos, CA, 1192–1195.
[19]
Jonathan Babb, Russell Tessier, and Anant Agarwal. 1993. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines. IEEE, 142–151.
[20]
K. Hornik, M. Stinchcombe, and H. White. 1989. Multilayer feedforward networks are universal approximators. Neural Networks 2, 5 (1989), 359–366.
[21]
Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, et al. 2021. Machine learning for electronic design automation: A survey. ACM Transactions on Design Automation of Electronic Systems 26, 5 (2021), Article 40, 46 pages.
[22]
William N. N. Hung and Richard Sun. 2018. Challenges in large FPGA-based logic emulation systems. In Proceedings of the 2018 International Symposium on Physical Design. 26–33.
[23]
Benzheng Li, Zhongdong Qi, Zhengguang Tang, Xiyi He, and Hailong You. 2021. High quality hypergraph partitioning for logic emulation. Integration 83 (2021), 67–76.
[24]
Mariem Makni, Mouna Baklouti, Smail Niar, and Mohamed Abid. 2017. Hardware resource estimation for heterogeneous FPGA-based SoCs. In Proceedings of the 32nd ACM Symposium on Applied Computing (SAC’17).
[25]
H. M. Makrani, F. Farahmand, H. Sayadi, S. Bondi, S. Manoj, H. Homayoun, and S. Rafatirad. 2019. Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL’19).
[26]
Roel Meeuws, S. Arash Ostadzadeh, Carlo Galuzzi, Vlad Mihai Sima, Razvan Nane, and Koen Bertels. 2013. Quipu: A statistical model for predicting hardware resources. ACM Transactions on Reconfigurable Technology and Systems 6, 1 (2013), 1–25.
[27]
Anshuman Nayak, Malay Haldar, Alok Choudhary, and Prithviraj Banerjee. 2002. Accurate area and delay estimators for FPGAs. In Proceedings of the 2002 Design, Automation, and Test in Europe Conference and Exhibition (DATE’02). IEEE, Los Alamitos, CA, 862–869.
[28]
Fabian Pedregosa, Gaël Varoquaux, Alexandre Gramfort, Vincent Michel, Bertrand Thirion, Olivier Grisel, Mathieu Blondel, et al. 2011. Scikit-learn: Machine learning in Python. Journal of Machine Learning Research 12 (2011), 2825–2830.
[29]
B. Reagen, R. Adolf, Y. S. Shao, G. Y. Wei, and D. Brooks. 2014. MachSuite: Benchmarks for accelerator design and customized architectures. In Proceedings of the IEEE International Symposium on Workload Characterization. 110–119.
[30]
Paul Schumacher and Pradip Jha. 2008. Fast and accurate resource estimation of RTL-based designs targeting FPGAs. In Proceedings of the 2008 International Conference on Field Programmable Logic and Applications. IEEE, Los Alamitos, CA, 59–64.
[31]
M. Shahshahani and D. Bhatia. 2021. Resource and performance estimation for CNN models using machine learning. In Proceedings of the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’21).
[32]
Changchun Shi, James Hwang, Scott Mcmillan, Ann Root, and Vinay Singh. 2004. A system level resource estimation tool for FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’04). 424–433.
[33]
Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, and Zhiru Zhang. 2019. LAMDA: Learning-assisted multi-stage autotuning for FPGA design closure. In Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’19). IEEE, Los Alamitos, CA, 74–77.
Index Terms
- Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs
Recommendations
LUT based realization of fixed-point multipliers targeting state-of-art FPGAs
Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of ...
Finite state machine optimization in FPGAs
CCSEIT '12: Proceedings of the Second International Conference on Computational Science, Engineering and Information TechnologySynthesis optimization plays a vital role in modern FPGAs in order to achieve high performance, in terms of resource utilization and reducing time consuming test process. Cell-based design techniques, such as standard-cells and FPGAs, together with ...
HyperPipelining of High-Speed Interface Logic
FPGA '16: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysThe throughput needs of networking designs on FPGAs are constantly growing -- from 40Gbps to 100Gbps, 400Gbps and beyond. A 400G Ethernet MAC needs to process wide data at high speeds to meet the throughput needs. Altera recently introduced HyperFlexTM [...
Comments
Information & Contributors
Information
Published In
March 2023
409 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 24 December 2022
Online AM: 29 September 2022
Accepted: 24 July 2022
Revised: 15 July 2022
Received: 14 February 2022
Published in TODAES Volume 28, Issue 2
Check for updates
Author Tags
Qualifiers
- Research-article
- Refereed
Funding Sources
- Key-Area Research and Development Program of Guangdong Province
- National 111 Center
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 480Total Downloads
- Downloads (Last 12 months)243
- Downloads (Last 6 weeks)33
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign inFull Access
View options
View or Download as a PDF file.
PDFeReader
View online with eReader.
eReaderFull Text
View this article in Full Text.
Full TextHTML Format
View this article in HTML Format.
HTML Format