Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay
Article No.: 56, Pages 1 - 17
Abstract
In this article, we focus on chip floorplanning, which aims to determine the location and orientation of circuit macros simultaneously, so the chip area and wirelength are minimized. As the highest level of abstraction in hierarchical physical design, floorplanning bridges the gap between the system-level design and the physical synthesis, whose quality directly influences downstream placement and routing. To tackle chip floorplanning, we propose an end-to-end reinforcement learning (RL) methodology with a hindsight experience replay technique. An edge-aware graph attention network (EAGAT) is developed to effectively encode the macro and connection features of the netlist graph. Moreover, we build a hierarchical decoder architecture mainly consisting of transformer and attention pointer mechanism to output floorplan actions. Since the RL agent automatically extracts knowledge about the solution space, the previously learned policy can be quickly transferred to optimize new unseen netlists. Experimental results demonstrate that, compared with state-of-the-art floorplanners, the proposed end-to-end methodology significantly optimizes area and wirelength on public GSRC and MCNC benchmarks.
References
[1]
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, and Yoji Kajitani. 1996. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 15, 12 (1996), 1518–1524.
[2]
K.-S. The and D. F. Wong. 1991. Area optimization for higher order hierarchical floorplans. In IEEE International Conference on Computer Design (ICCD’91). 520–521.
[3]
Tung-Chieh Chen and Yao-Wen Chang. 2005. Modern floorplanning based on fast simulated annealing. In ACM International Symposium on Physical Design (ISPD’05). 104–112.
[4]
Song Chen and Takeshi Yoshimura. 2008. Fixed-outline floorplanning: Block-position enumeration and a new method for calculating area costs. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 27, 5 (2008), 858–871.
[5]
Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, and Chung-Kuan Cheng. 2015. ePlace-MS: Electrostatics-based placement for mixed-size circuits. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 34, 5 (2015), 685–698.
[6]
Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, and Lutong Wang. 2018. Replace: Advancing solution quality and routability validation in global placement. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 38, 9 (2018), 1717–1730.
[7]
Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, and Martin D. F. Wong. 2020. Learn to floorplan through acquisition of effective local search heuristics. In IEEE International Conference on Computer Design (ICCD’20). 324–331.
[8]
Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, and Xiaoqing Wen. 2021. GoodFloorplan: Graph convolutional network and reinforcement learning-based floorplanning. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 41, 10 (2021), 3492–3502.
[9]
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, and Jeff Dean. 2021. A graph placement methodology for fast chip design. Nature 594, 7862 (2021), 207–212.
[10]
David Silver, Aja Huang, Chris J. Maddison, Arthur Guez, Laurent Sifre, George van den Driessche, Julian Schrittwieser, Ioannis Antonoglou, Veda Panneershelvam, Marc Lanctot, Sander Dieleman, Dominik Grewe, John Nham, Nal Kalchbrenner, Ilya Sutskever, Timothy Lillicrap, Madeleine Leach, Koray Kavukcuoglu, Thore Graepel, and Demis Hassabis. 2016. Mastering the game of Go with deep neural networks and tree search. Nature 529, 7587 (2016), 484–489.
[11]
Mohammad Amini, Zhanguang Zhang, Surya Penmetsa, Yingxue Zhang, Jianye Hao, and Wulong Liu. 2022. Generalizable floorplanner through corner block list representation and hypergraph embedding. In ACM International Conference on Knowledge Discovery and Data Mining (KDD’22). 2692–2702.
[12]
Richard S. Sutton and Andrew G. Barto. 2018. Reinforcement Learning: An Introduction. MIT Press.
[13]
Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, Łukasz Kaiser, and Illia Polosukhin. 2017. Attention is all you need. In Conference on Neural Information Processing Systems (NIPS’17). 6000–6010.
[14]
Khushro Shahookar and Pinaki Mazumder. 1991. VLSI cell placement techniques. ACM Comput. Surv. 23, 2 (1991), 143–220.
[15]
Pei-Ning Guo, Chung-Kuan Cheng, and Takeshi Yoshimura. 1999. An O-tree representation of non-slicing floorplan and its applications. In ACM/IEEE Design Automation Conference (DAC’99). 268–273.
[16]
Sung Kyu Lim. 2008. Practical Problems in VLSI Physical Design Automation. Springer.
[17]
Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, and Shu-Wei Wu. 2000. B*-trees: A new representation for non-slicing floorplans. In ACM/IEEE Design Automation Conference (DAC’00). 458–463.
[18]
Jai Ming Lin and Yao Wen Chang. 2004. TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans. IEEE Trans. Comput.-aid. Des. Integ. Circ. Syst. 23, 6 (2004), 968–980.
[19]
Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, and Jun Gu. 2004. Corner block list representation and its application to floorplan optimization. IEEE Trans. Circ. Syst. II: Expr. Briefs 51, 5 (2004), 228–233.
[20]
Adrià Puigdomènech Badia, Bilal Piot, Steven Kapturowski, Pablo Sprechmann, Alex Vitvitskyi, Zhaohan Daniel Guo, and Charles Blundell. 2020. Agent57: Outperforming the Atari human benchmark. In International Conference on Machine Learning (ICML’20). 507–517.
[21]
Md Shamim Hussain, Mohammed J. Zaki, and Dharmashankar Subramanian. 2022. Global self-attention as a replacement for graph convolution. In ACM International Conference on Knowledge Discovery and Data Mining (KDD’22). 655–665.
[22]
Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. 2015. Delving deep into rectifiers: Surpassing human-level performance on ImageNet classification. In IEEE International Conference on Computer Vision (ICCV’15). 1026–1034.
[23]
Hangbo Bao, Wenhui Wang, Li Dong, Qiang Liu, Owais Khan Mohammed, Kriti Aggarwal, Subhojit Som, Songhao Piao, and Furu Wei. 2022. VLMo: Unified vision-language pre-training with mixture-of-modality-experts. In Conference on Neural Information Processing Systems (NIPS’22). 32897–32912.
[24]
William Fedus, Barret Zoph, and Noam Shazeer. 2022. Switch transformers: Scaling to trillion parameter models with simple and efficient sparsity. J. Mach. Learn. Res. 23, 1 (2022), 5232–5270.
[25]
Ruoxi Wang, Rakesh Shivanna, Derek Cheng, Sagar Jain, Dong Lin, Lichan Hong, and Ed Chi. 2021. DCN V2: Improved deep & cross network and practical lessons for web-scale learning to rank systems. In the Web Conference (WWW’21). 1785–1797.
[26]
Oriol Vinyals, Meire Fortunato, and Navdeep Jaitly. 2015. Pointer networks. In Conference on Neural Information Processing Systems (NIPS’15). 2692–2700.
[27]
Marcin Andrychowicz, Filip Wolski, Alex Ray, Jonas Schneider, Rachel Fong, Peter Welinder, Bob McGrew, Josh Tobin, Pieter Abbeel, and Wojciech Zaremba. 2017. Hindsight experience replay. In Conference on Neural Information Processing Systems (NIPS’17). 5055–5065.
[28]
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang. 2022. Floorplanning with graph attention. In ACM/IEEE Design Automation Conference (DAC’22). 1303–1308.
[29]
Adam Paszke, Sam Gross, Soumith Chintala, Gregory Chanan, Edward Yang, Zachary DeVito, Zeming Lin, Alban Desmaison, Luca Antiga, and Adam Lerer. 2017. Automatic differentiation in PyTorch. In NIPS Workshop.
[30]
MCNC Benchmark. 2007. University of Michigan. Retrieved from http://vlsicad.eecs.umich.edu/BK/MCNCbench
[31]
GSRC Benchmark. 2007. University of Michigan. Retrieved from http://vlsicad.eecs.umich.edu/BK/GSRCbench
[32]
John Schulman, Filip Wolski, Prafulla Dhariwal, Alec Radford, and Oleg Klimov. 2017. Proximal policy optimization algorithms. arXiv preprint arXiv:1707.06347 (2017).
Index Terms
- Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay
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Publication History
Published: 03 May 2024
Online AM: 22 March 2024
Accepted: 14 March 2024
Revised: 06 March 2024
Received: 17 October 2023
Published in TODAES Volume 29, Issue 3
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- National Natural Science Foundation of China
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