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Oxide based resistive memories (OxRAMs) is one of the potential candidates for non-volatile logic circuits and neuromorphic circuits in the applications of wearable devices, internet of things (IoT), cloud computing, and big-data... more
Oxide based resistive memories (OxRAMs) is one of the potential candidates for non-volatile logic circuits and neuromorphic circuits in the applications of wearable devices, internet of things (IoT), cloud computing, and big-data processing. One of the main OxRAMs issue is the noise behavior of the high resistance state (HRS). In this work, we will demonstrate a hybrid (CMOS logic plus ReRAM devices) Non Volatile Flip Flop designed to face OxRAM variability. Concerning neuromorphic circuits, we will focus on the impact of resistance variability on the performance of Convolutional Neural Network (CNN) systems for visual pattern recognition applications.
Research Interests: Computer Science, Pattern Recognition, Embedded Systems, Neural Networks, Neuromorphic Engineering, and 11 moreBig Data, Cmos, Internet of Things (IoT), Data Handling, Computation Theory, Resistive Random Access Memory, Pattern Recognition Systems, Convolutional Neural Network, Electronic Circuit, Logic circuits, and Neuromorphic systems
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Deploying Deep Neural Networks in low-power embedded devices for real time-constrained applications requires optimization ofmemory and computational complexity of the networks, usually by quantizing the weights. Most of the existing works... more
Deploying Deep Neural Networks in low-power embedded devices for real time-constrained applications requires optimization ofmemory and computational complexity of the networks, usually by quantizing the weights. Most of the existing works employ linear quantization which causes considerable degradation in accuracy for weight bit widths lower than 8. Since the distribution of weights is usually non-uniform (with most weights concentrated around zero), other methods, such as logarithmic quantization, are more suitable as they are able to preserve the shape of the weight distribution more precise. Moreover, using base-2 logarithmic representation allows optimizing the multiplication by replacing it with bit shifting. In this paper, we explore non-linear quantization techniques for exploiting lower bit precision and identify favorable hardware implementation options. We developed the Quantization Aware Training (QAT) algorithm that allowed training of low bit width Power-of-Two (PoT) ne...
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In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics.... more
In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance.
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In this work we quantify the impact of dots size and dots number fluctuations on the programming window dispersion of multi-nanocrystal memory devices. Concerning dots size distribution, experimental imaging (i.e. transmission electron... more
In this work we quantify the impact of dots size and dots number fluctuations on the programming window dispersion of multi-nanocrystal memory devices. Concerning dots size distribution, experimental imaging (i.e. transmission electron microscopy) is used and generalized assumptions are made, according to well known theoretical distributions. Concerning dots number distribution, a Poisson dispersion is assumed. Both a Monte Carlo simulation and a deep theoretical analysis (i.e. compound distributions theory) are exploited to assess in two different ways the overall results. Eventually clear guidelines, concerning dot density and dot distribution requirements, are provided for future memory generations.
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Abstract—We propose an analytical model of the effects of a nonuniform distribution of trapped charge on the electrical characteristics and on the perspectives of 2-bit operation of dis-crete-trap memories. To keep the model tractable, we... more
Abstract—We propose an analytical model of the effects of a nonuniform distribution of trapped charge on the electrical characteristics and on the perspectives of 2-bit operation of dis-crete-trap memories. To keep the model tractable, we consider an idealized nonuniform distribution, represented by a step function, so that the concentration of trapped charge can assume only two possible values in two different regions. Notwithstanding the simplicity of our assumptions, which limits the range of validity of our model to the subthreshold and weak inversion regions of the I–V characteristics, we can investigate a series of important aspects for 2-bit storage of nonvolatile memories. Our model is then validated through comparison with detailed numerical simu-
Brain-inspired architectures in neuromorphic hardware are currently subject to intensive research as an alternative to the limits of traditional computer organisation. The remarkable computing performance and efficiency of biological... more
Brain-inspired architectures in neuromorphic hardware are currently subject to intensive research as an alternative to the limits of traditional computer organisation. The remarkable computing performance and efficiency of biological nervous systems are widely attributed to the co-localisation of memory and computation spatially throughout the structure. Moreover, it appears that a number of local self-organising neural mechanisms play their part in efficient biological computation. An example is neuronal intrinsic plasticity, where a neuron adapts its parameters to maximise its information capacity based on the statistical properties of its input while minimising the power it consumes. CMOS circuits implementing neuron models have been proposed but require their parameters to be set by biases originating from a centralised memory. In this work, we propose a hybrid CMOS-RRAM circuit that addresses this problem through storing neuron parameters within programmable nonvolatile resistive memories incorporated into the CMOS neuron. Additional circuits exploit the stochastic switching properties of resisitive memories to map a local intrinsic plasticity algorithm onto the proposed neuron. We demonstrate the computational advantages of this algorithm through simulation, calibrated on experimental data, whereby the neuron maximises its information capacity while minimising its power consumption, as is the case for biological neurons.
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The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at the end-devices instead of... more
The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at the end-devices instead of in the Cloud. To map the embedded-systems requirements, we present a holistic research approach to the development of low-power architectures inspired by the human brain, where process development and integration, circuit design, system architecture, and learning algorithms are simultaneously optimized. This paper is organized as follows: We begin with a survey of recent research on the human brain and a historical perspective of cognitive neuroscience. Then, artificial intelligence is introduced, and the challenges of Deep Learning systems (in terms of power requirements) are addressed. The key reasons to distribute intelligence over the whole network are discussed. To emphasize the need for low-power solutions, a quantitative benchmark of existing specialized edge platforms that can execute machine-learning algorithms on conventional embedded hardware is presented. The primary focus of this paper will be on the implementation of optimized neuromorphic hardware as a highly promising solution for future ultra-low-power cognitive systems. We show that emerging technologies (such as advanced CMOS, 3D technologies, emerging resistive memories, and Silicon photonics), coupled with novel brain-inspired paradigms, such as spike-coding and spike-time-dependent-plasticity, have extraordinary potential to provide intelligent features in hardware, approaching the way knowledge is created and processed in the human brain. Finally, we conclude with our vision of the enabled future disruptive applications and a discussion of the main challenges which should be tackled to exploit the full potential of brain-inspired technologies.
Research Interests: Computer Science and IEEE
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The miniaturization of systems toward System-On-Chip is a long term trend that will continue after the end of Moore's Law. In the context of Internet-of Things (IoT), this means looking for components, integration schemes and data... more
The miniaturization of systems toward System-On-Chip is a long term trend that will continue after the end of Moore's Law. In the context of Internet-of Things (IoT), this means looking for components, integration schemes and data treatment paradigms enabling the reduction of both power consumption and cost. In this paper we will present some emerging devices for sensing and local data treatment that could enable future energy efficient IOT systems.
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In the last decade machine learning algorithms have proven unprecedented performance to solve many real-world detection and classification tasks, for example in image or speech recognition. Despite these advances, there are still some... more
In the last decade machine learning algorithms have proven unprecedented performance to solve many real-world detection and classification tasks, for example in image or speech recognition. Despite these advances, there are still some deficits. First, these algorithms require significant memory access thus ruling out an implementation using standard platforms (e.g. GPUs, FPGAs) for embedded applications. Second, most machine leaning algorithms need to be trained with huge data sets (supervised learning). Resistive memories (RRAM) have demonstrated to be a promising candidate to overcome both these constrains. RRAM arrays can act as a dot product accelerator, which is one of the main building blocks in neuromorphic computing systems. This approach could provide improvements in power and speed with respect to the GPU-based networks. Moreover RRAM devices are promising candidates to emulate synaptic plasticity, the capability of synapses to enhance or diminish their connectivity between neurons, which is widely believed to be the basis for learning and memory in the brain. Neural systems exhibit various types and time periods of plasticity, e.g. synaptic modifications can last anywhere from seconds to days or months. In this work we proposed an architecture that implements both Short- and Long-Term Plasticity rules (STP and LTP) using RRAM arrays. We showed the benefits of utilizing both kinds of plasticity with two different applications, visual pattern extraction and decoding of neural signals. LTP allows the neural networks to learn patterns without training data set (unsupervised learning), and STP makes the learning process very robust against environmental noise.
Research Interests: Computer Science and IEEE
In this work, we will focus on the role that non-volatile resistive memory technologies (RRAM) can play for modeling key features of biological synapses. We will present an architecture and a reading/programming strategy to emulate both... more
In this work, we will focus on the role that non-volatile resistive memory technologies (RRAM) can play for modeling key features of biological synapses. We will present an architecture and a reading/programming strategy to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile OxRAM arrays. A visual-pattern extraction application is discussed using spiking neural networks. We demonstrated that Long-Term plasticity allows the neural networks to learn patterns and the Short Term plasticity allows to improve accuracy (reduction of the false positive events generated by white noise in the input data) in presence of significant background noise in the input data.
Research Interests: Computer Science and Acm
An innovative approach for decoding of brain signals based on Spiking Neural Networks is presented in this paper. Synapses are implemented by BEOL compatible oxide resistive RAM (OxRAM) devices providing low programming voltages... more
An innovative approach for decoding of brain signals based on Spiking Neural Networks is presented in this paper. Synapses are implemented by BEOL compatible oxide resistive RAM (OxRAM) devices providing low programming voltages (<2.5V) and currents (∼30μA). Spike-timing-dependent plasticity enables the network for autonomous online spike sorting of measured biological signals. Ultra-low synaptic power consumption in the range of 10nW, recognition rates around 90% and real-time functionality bear high potential for future healthcare applications.
Research Interests: Computer Science and IEEE
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This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid... more
This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.
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The steady improvement in the performance of computing systems seen for many decades is levelling off as the miniaturization of semiconducting technology approaches the atomic limit, facing severe physical and technological issues.... more
The steady improvement in the performance of computing systems seen for many decades is levelling off as the miniaturization of semiconducting technology approaches the atomic limit, facing severe physical and technological issues. Neuromorphic computing is an emerging solution which makes use of silicon technology in a different way, inline with the computational principles observed in animal nervous systems. In this article, we argue that the nervous systems of insects in particular offer themselves as an ideal starting point for incorporation into realistic neuromorphic systems and review research in developing insect-inspired neuromorphic systems. We conclude with an exciting yet tangible vision of a full neuromorphic sensory-motor system where a liquid state machine modelling the function of the insect mushroom body links input to output and allows for amalgamation of the work discussed in a hierarchical framework of a full system inspired by the concept of how information flows through insects.
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Non-Volatile Resistive Memory (NVRM) such as Phase-Change Memory, Oxide-based Memory and Conductive Bridging Memory has rapidly increased in maturity in the last decade. In a memory market context dominated by DRAM and Flash technologies,... more
Non-Volatile Resistive Memory (NVRM) such as Phase-Change Memory, Oxide-based Memory and Conductive Bridging Memory has rapidly increased in maturity in the last decade. In a memory market context dominated by DRAM and Flash technologies, the evolving memory hierarchy and the strong differentiation of the applications portfolio represent a real opportunity for NVRM to emerge. The real revolution of this technology resides in its versatility made possible by general trade-offs existing between the different NVRM performances, highlighted in the last years by the research and the development in several fields (e.g. materials science, engineering, etc.). We present here some of these trade-offs, and how they can be used to target specific applications.
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In this paper, we present an alternative approach to perform spike sorting of complex brain signals based on spiking neural networks (SNN). The proposed architecture is suitable for hardware implementation by using resistive random access... more
In this paper, we present an alternative approach to perform spike sorting of complex brain signals based on spiking neural networks (SNN). The proposed architecture is suitable for hardware implementation by using resistive random access memory (RRAM) technology for the implementation of synapses whose low latency (<1μs) enables real-time spike sorting. This offers promising advantages to conventional spike sorting techniques for brain-computer interfaces (BCI) and neural prosthesis applications. Moreover, the ultra-low power consumption of the RRAM synapses of the spiking neural network (nW range) may enable the design of autonomous implantable devices for rehabilitation purposes. We demonstrate an original methodology to use Oxide based RRAM (OxRAM) as easy to program and low energy (<75 pJ) synapses. Synaptic weights are modulated through the application of an online learning strategy inspired by biological Spike Timing Dependent Plasticity. Real spiking data have been rec...
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In this paper, a detailed reliability analysis of metal-oxide conductive bridge memories (CBRAM) is presented. This paper mostly focuses on electrical characterization of metal-oxide CBRAM devices endurance, using optimized program/erase... more
In this paper, a detailed reliability analysis of metal-oxide conductive bridge memories (CBRAM) is presented. This paper mostly focuses on electrical characterization of metal-oxide CBRAM devices endurance, using optimized program/erase conditions, and data retention at high temperature. The addition of a thin metal-oxide layer (0.5 nm-thick Al2O3) in the bottom of the GdOx memory stack significantly increases the ROFF and the memory window (more than one decade), with improved endurance performance (up to 105 cycles) with respect to the monolayer CBRAM device. Meanwhile, high thermal stability was also achieved (two decades of window margin are constantly maintained beyond 24 h at 250 °C). The bilayer oxide GdOX/Al2O3 CBRAM is a promising technology for potential future high density memory applications.
Research Interests: Engineering and IEEE
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We investigate in detail the effects of metal electrodes on the switching performance and conductive filament (CF) stability of HfO2-based RRAM. The current- voltage characteristics of the devices exhibit different electrodedependent... more
We investigate in detail the effects of metal electrodes on the switching performance and conductive filament (CF) stability of HfO2-based RRAM. The current- voltage characteristics of the devices exhibit different electrodedependent RESET profiles which we attempt to clarify. With the insight from the experimental data, we employ first-principles calculations to have a better microscopic understanding of the devices. We study the charge injection, formation of Frenkel pairs, and diffusion of oxygen defects (oxygen vacancies Vo and oxygen interstitials Oi) that are important in the CF creation and stability during the device operation. Since the presence of Ti in RRAM has been associated with the creation of substoichiometric TiOy region at the Ti/HfO2 interface, we also explore different Ti and Hf suboxides to understand the possible composition of that interface. Our calculations suggest that the composition of the interface would be Ti2O/Hf2O3 from thermodynamic perspective. By combining the experimental and calculations results, we show that the concentration of oxygen interstitial (Oi) ions in the oxide after CF formation is larger for RRAM devices with inert electrodes (like Pt) compared with O reactive electrodes (like Ti) which results in degraded device performance. The lower Oi concentration in HfO2 layer with Ti electrodes results in improved CF thermal stability and device variability.
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We study in detail the impact of alloying HfO<sub>2</sub> with Al (Hf<sub>1_x</sub>Al<sub>2</sub>xO<sub>2+x</sub>) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal... more
We study in detail the impact of alloying HfO<sub>2</sub> with Al (Hf<sub>1_x</sub>Al<sub>2</sub>xO<sub>2+x</sub>) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed comprehensive diffusion barrier calculations in HfO<sub>2</sub>, Hf<sub>1_x</sub>Al<sub>2</sub>xO<sub>2+x</sub>, and Hf<sub>1_x</sub>TixO<sub>2</sub> relative to the oxygen vacancy (Vo) movement involved in low-resistance state (RON) thermal stability. Calculations are performed at the best level using ab initio techniques. This paper provides an insight on the improved RON stability of our Hf<sub>1_x</sub>Al<sub>2</sub>xO<sub>2+x</sub>-based RRAM devices and predicts the degraded retention of Hf<sub>1_x</sub>TixO<sub>2</sub>-based RRAM measured in the literature. Our theoretical calculations link the origin of RON retention failure to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in HfO<sub>2</sub>-based RRAM.
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Germanium enrichment process also known as condensation can be used for the integration of stressors in the fully depleted silicon on insulator technology. Using multi-physics modeling combined with advanced TEM characterization we... more
Germanium enrichment process also known as condensation can be used for the integration of stressors in the fully depleted silicon on insulator technology. Using multi-physics modeling combined with advanced TEM characterization we studied the formation of stressors with condensation. We first observed in blanket 1D structures that the diffusion rate is substantially reduced during Ge condensation compared to the typical diffusion in neutral atmosphere. We postulate this is due to the injection of interstitial at the oxide/SiGe interface and to a reduced stress effect on the kinetics. We then studied self-aligned in plane stressors (SAIPS) formed in the source/drain region using localized Ge condensation. It is shown that the SAIPS methodology almost doubles the channel stress generated by the source drain stressor. Combining Si0.65Ge0.35 and SAIPS source/drain stressors with in-situ Si0.79Ge0.21 strained channel allows achieving a stress of -2 GPa in the p-type channel with gate fi...
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This paper presents some experimental results and a simple model for the study of capacitors containing silicon dots in silicon dioxide to be integrated in a new generation of nonvolatile single electron memories. This work is essential... more
This paper presents some experimental results and a simple model for the study of capacitors containing silicon dots in silicon dioxide to be integrated in a new generation of nonvolatile single electron memories. This work is essential for the stabilisation of the technology to be used in the future for these devices aimed at very high memory arrays.
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In this paper, a detailed reliability analysis of metal-oxide CBRAM devices is presented. We demonstrated that the addition of a thin metal-oxide layer in the bottom of the memory stack significantly increases the ROFF and the memory... more
In this paper, a detailed reliability analysis of metal-oxide CBRAM devices is presented. We demonstrated that the addition of a thin metal-oxide layer in the bottom of the memory stack significantly increases the ROFF and the memory window (more than 1 decade), with improved endurance performance. At the same time, high thermal stability was also achieved (window margin constant during more than 24 hours at 250°C). The origin of the window margin degradation during endurance is discussed and interpreted by means of a Trap Assisted Tunneling Model, putting in evidence the role of defect generation and Cu residual atoms in the resistive layer.
Research Interests: Computer Science and IEEE
Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si /... more
Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si / Si1-xGex bilayers and the selective removal of the top Si1-xGex film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted- SOI (CMOS FD-SOI) devices at 14 nm node design rules were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.
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In this chapter, we will start by introducing the main features and scaling limits of current Flash memory technologies. Then, the main strategy of the innovative research in this field will be presented. Today, two main research paths... more
In this chapter, we will start by introducing the main features and scaling limits of current Flash memory technologies. Then, the main strategy of the innovative research in this field will be presented. Today, two main research paths can be identified. To extend the classical ...
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'Dipartimento di Ingegneria dell'Informazione, University of Parma, Parma PR, 1-43 100, ITALY Phone: +39 521 905809, Fax: +39 521 905822, Email: chi@ee.unipr.it "Laboratoire de Physique des Composants Semiconducteurs,... more
'Dipartimento di Ingegneria dell'Informazione, University of Parma, Parma PR, 1-43 100, ITALY Phone: +39 521 905809, Fax: +39 521 905822, Email: chi@ee.unipr.it "Laboratoire de Physique des Composants Semiconducteurs, ENSERG, 23 Avenue des Martyrs, BP 257,38016 ...
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ABSTRACT We show experimentally that the first reset operation of forming-free HfOx based RRAM devices is of bulk type where the reset current is area dependent. Moreover, the device pristine resistance shows a weak inverse... more
ABSTRACT We show experimentally that the first reset operation of forming-free HfOx based RRAM devices is of bulk type where the reset current is area dependent. Moreover, the device pristine resistance shows a weak inverse proportionality to temperature, which we associate to a sub-stoichiometric HfOx matrix created during device fabrication. Finally, we use ab initio calculations to gain insight into the atomistic structure of these forming-free RRAM devices.
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ABSTRACT UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to... more
ABSTRACT UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.
ABSTRACT This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS... more
ABSTRACT This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS technologies. The device electrical characteristics show: (i) a switching time of 100ns at 1V, (ii) an excellent data retention at 150°C and (iii) a high endurance up to 108 cycles. The second part of this paper focuses on circuit design. The benefits of 3D integration of non-volatile devices on CMOS are highlighted. Performance and area gains are discussed as well as new application features.
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ABSTRACTA systematic study on the Si dot formation after chemical vapor deposition on silicon oxide substrates is presented. The process has been followed from the early stages of the dot formation up to 25% of coverages. Structural... more
ABSTRACTA systematic study on the Si dot formation after chemical vapor deposition on silicon oxide substrates is presented. The process has been followed from the early stages of the dot formation up to 25% of coverages. Structural characterization has been performed by means of energy filtered transmission electron microscopy, which allowed us to observe dot sizes down to 0.5 nm in radius. The nanodots are shown to be surrounded by a depleted zone, where no new Si dots are observed to nucleate. This has been attributed to the adatoms capture mechanism by pre-existing dots, during the deposition. The dot radius and the capture size are shown to collapse onto the same curve, thus indicating the scaling behavior of the process. The adatom diffusion process is shown to restrict the number of nucleation sites, the final dot size and the dot position, thus driving the process toward partial self-order.
Research Interests: Materials Science and MRS
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ABSTRACT We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of... more
ABSTRACT We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.