Tillmann Krauss

Recently, unique novel characteristics of ambipolar transistors have been explored in various forms on both device and cell level. Most of these so called reconfigurable or polarity controllable devices are based on silicon nanowires, carbon nanotubes or similar gate-all-around topologies, thus requiring sophisticated or even non-standard manufacturing processes. Such complex processes limit the capability to build large circuits, due to associated maturity issues and cost.Here, we preview the DeFET technology, featuring our ambipolar, electrostatically-doped planar device based on an FDSOI CMOS-compatible manufacturing process. After a short introduction to the device itself, we present characteristics of full-swing DeFET XOR gate. For the XOR gate, we show a reduction from 12 transistors in classical CMOS to 8 transistors in DeFET technology.

Ambipolar transistors have emerged recently and are presented on device and cell level. The ability to conduct both electrons and holes is often provided by the use of silicon nanowires, carbon nanotubes or similar gate-all-around topologies. Large scale integration of these devices is difficult due to the complex manufacturing process. In this paper we present an ambipolar “Dehancement Mode Field Effect Transistor (DeFET)” which is an electrostatically doped planar device. After introducing the device itself, we show its performance by analyzing it in the TCAD simulation of a digital inverter configuration. We present characteristics of our full output swing CMOS-style inverter and compare it to an inverter which consists of MOSFETs from a similar 180 nm SOI technology. The bias for the electrostatic doping of the DeFETs is provided by the cell supply voltages, therefore no additional voltage has to be provided to reconfigure our ambipolar DeFET as n-type or p-type with performance similar to 180 nm SOI MOSFETs.

Recently, unique novel characteristics of ambipolar transistors have been explored in various forms on both device and cell level. Most of these so called reconfigurable or polarity controllable devices are based on silicon nanowires, carbon nanotubes or similar gate-all-around topologies, thus requiring sophisticated or even non-standard manufacturing processes. Such complex processes limit the capability to build large circuits, due to associated maturity issues and cost.Here, we preview the DeFET technology, featuring our ambipolar, electrostatically-doped planar device based on an FDSOI CMOS-compatible manufacturing process. After a short introduction to the device itself, we present characteristics of full-swing DeFET XOR gate. For the XOR gate, we show a reduction from 12 transistors in classical CMOS to 8 transistors in DeFET technology.

In this paper we focus on the implementation of a process flow of SB-MOSFETs into the process simulator of the Synopsys TCAD Sentaurus tool-chain. An improved structure containing topography is briefly discussed and further device simulations are applied with the latest physical models available. Key parameters are discussed and finally the results are compared with fabricated SB-MOSFETs in terms of accuracy and capability of process simulations.

In this paper we focus on the implementation of a process flow of SB-MOSFETs into the process simulator of the Synopsys TCAD Sentaurus tool-chain. The improved structure containing topography is briefly discussed and further device simulations are applied with the latest physical models available for these type of devices. Afterwards, some key parameters are discussed and finally the results are compared with fabricated SB-MOSFETs in terms of accuracy and capability of process simulations.

In this paper we present a simulation framework to account for the Schottky barrier lowering models in SB-MOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus predict accurately the on- and off-current regions are adressed.

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

In this paper, we investigate by simulation and by evaluation of experimental data the feasibility of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect-transistor (FET) structure which is based on our already published Si-nanowire (SiNW) technology. The key technology for this dual-gated general purpose FET contains Schottky S/D junctions on a silicon-on-insulator (SOI) platform. In combination with electrostatic doping and a dual-gate configuration, the Schottky junctions significantly increase the temperature robustness of the device.

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying a control-gate voltage, which significantly increases the flexibility and versatility in digital integrated circuits.

In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

In this paper, we demonstrate by extending TCAD simulations based on experimental data of fabricated electrostatically doped, reconfigurable planar double-gate field-effect transistors, the improved characteristics of a triple gate device design. The technological cornerstones for this general-purpose FET comprise mid-gap Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type, is interchangeable during operation by applying a control-gate voltage which significantly increases the flexibility and versatility in the design of integrated circuits.

High-temperature transistors are of great interest for industrial applications, for instance, oil&gas and geothermal exploration, avionic, space, automotive and energy conversion. Especially, energy conversion electronics using wide-bandgap power transistors, i.e. SiCFET, in combination with high-temperature silicon gate-driver circuits can significantly increase system efficiency and reduce costs [1]. Our improved planar virtually dopant-free silicon-based double gate SOI FET with Ni and WTiN front-gate electrodes demonstrates ultra-low drain leakage currents at high-temperatures opening a path to record operating temperatures for silicon-based FET devices. Device Structure The long-channel device fabrication relies on a standard CMOS-compatible prototyping process using SOITEC Smart-Cut™ SOI-substrates with the lowest commercially available boron background doping of 1E15cm-3 enabling high carrier mobilities. Mid-gap Schottky barrier (SB) contacts are fabricated via nickel silicidation. The metal front-gate (FG) electrode consist of reactively sputtered WTiN for NMOS or Nickel for PMOS operation on a 8nm thick SiO2 gate dielectric. Channel height (CH) is approximated to 15nm. The back-gate (BG) formed by the silicon handle wafer is insulated by 145nm buried SiO2 (BOX) (Fig.1). Device Operation The device is modeled as a combination of two interacting FETs, one fully ambipolar Schottky barrier backside FET and a second unipolar junctionless (JL) topside FET [2,3]. The BG influences the whole body layer including the S/D Schottky barriers forming an ambipolar enhancement mode SBFET. Therefore, the dominant charge carrier type, i.e. electrons (VBG»0V) or holes (VBG«0V) in the channel region is defined by the BG polarity. In this configuration, the channel is located close to the body silicon to BOX interface (Fig.3). The charge carriers originate from the mid-gap NiSi SB contacts and enter the body layer at room temperature mainly by thermionic field emission (TFE) and at elevated temperatures by thermionic emission (TE) (Fig.2). In contrast, the depletion mode JLFET formed by the FG electrode only locally affects the charge carrier density in the middle of the channel and controls the current flow between source and drain with excellent electrostatic control as illustrated by the carrier density simulation in Fig.3. The combination of the enhancement and depletion mode operation in one device can appositely be summarized as enhancement suppression or dehancement mode operation (DeFET). Results & Discussion P- and NMOS transistor behavior is realized by applying the appropriate BG polarity to the very same device enabling transistor level reconfigurability (Fig.4). Maximum on-state current and threshold voltage are proportional to the magnitude of VBG (Fig.4). The work function difference between Ni and WTiN metal front-gate devices as well as process variations result in a significant threshold shift (Fig.4). The channel height (Fig.1) is a crucial parameter in device fabrication as it directly affects the off-state leakage current and threshold voltage [7]. Regarding high-temperature performance, the use of the SOI substrate eliminates bulk drain leakage while the introduction of SB contacts minimizes the band-to-band tunneling effect in comparison to classic steep S/D pn-junctions. For rising operating temperatures up to 470K, the on-state current increases from 8 to 46µA as TFE and TE increase allowing an overcompensation of the temperature dependent carrier mobility degradation effect (Fig.5,right). At the same time the drain leakage current is only increasing from <100fA to 2nA from 300 to 470K due to the high potential barrier induced by the FG (Fig.5,left). Gate leakage currents are <6pA during all measurements. Furthermore, PMOS behavior with nickel metal front-gate follows the same trends. Device simulations predict that reducing the channel height and introducing mid-κ gate dielectrics, i.e. Al2O3, renders record operating temperatures possible even for scaled devices limited only by reliability. Comparing the here presented DeFET generation with previous generations and other long-channel Si-based high-temperature FET structures illustrates the clear advantage of our device concept in suppressing drain leakage currents at high temperatures (Fig.6) [4-7]. Conclusion In this contribution, we demonstrate by means of experimental measurement data and device simulations the significantly improved drain leakage suppression at high operating temperatures of the planar dehancement mode FET CMOS technology in comparison to our previously published results in [7]. The combination of SB and JLFET properties opens a possible path for silicon based FET operation up to temperatures of 700K for various industrial applications. References [1] Blalock et al., IEEE Trans. on Power Electronics, 30(3), 2015. [2] Walter et al., Phys. Status Solidi C, 11(11), 2014. [3] Larson and Snyder, IEEE Trans. on…

In this work we investigate the in situ growth of carbon nanotubes (CNTs) on different dielectric stacks for use in discrete field-effect transistor devices. While CNT growth is demonstrated on all stacks, only devices fabricated on atomic layer deposited aluminum oxide show sufficiently reliable gate dielectrics. Electrical burn pulses are applied to the devices to selectively remove undesired metallic CNTs in order to obtain proper transistor behavior with an on/off current ratio of five orders of magnitude.

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons

In this work, we present MOS capacitors and MOS transistors with a crystalline gadolinium oxide (Gd2O3) gate dielectric and metal gate electrode (titanium nitride) fabricated in a replacement gate process. Initial results on ALD-TiN/Gd2O3/Si gate stacks on p- and n-substrates with equivalent oxide thicknesses (EOT) of 3.0 nm and 1.5 nm, respectively, are presented in this work.

In this paper, we propose and demonstrate by simulation an electrostatically doped and therefore voltage-programmable planar field-effect-transistor (FET) structure which is based on our results of already published Si-nanowire (SiNW) devices. The key technology for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) platform. The desired transistor type, i.e. NFET or PFET, is selectable on the fly by applying an appropriate control-voltage which significantly enhances flexibility in design of integrated circuits.

In this paper we report on a newly developed multi-gate nanowire-field-effect device (NWFET) in which the transistor type (i.e. PMOS and NMOS) is freely selectable by the application of a control-voltage. This significantly adds to flexibility in design of integrated circuits and their fabrication, respectively. We will show, that the use of midgap Schottky-barrier source and drain contacts are the key enabler for this device concept to be functional. A fully functional freely configurable CMOS-NWFET inverter circuit is presented, demonstrating the capability of this SOI technology platform. All this makes the presented NWFET-technology suitable for the fabrication multi-purpose devices for many applications.

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

In this paper we report on a newly developed multigate nanowire (NW) based field-effect device (NWFET) where the transistor type is freely selectable by the application of a control-voltage, adding to design flexibility in integrated circuit fabrication. Moreover, the midgap Schottky-barrier source and drain contacts of the NWFET make it feasible for the usa in high temperature environments, since the devices posses both stability against high temperatures and low OFF-state current at the same time. This makes the presented NWFET a multi-purpose device for many specific circuit applications.

... 1482-1485 [3] Wanlass, FM and Sah, CT "Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes," International Solid State Circuits Conference Digest of Technical Papers (February 20, 1963) pp. 32-33. [4] Seong-Dong Kim, Cheol-Min Park, and Jason CS Woo ...

In this paper we report on a newly de- veloped nanowire based field-effect device-architecture (NWFET) that can be used in high temperature envi- ronments. Our devices posess both high temperature stability and low OFF-state current. By changes in source/drain bias-polarity the electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific application. I. Introduction Silicon nanowires are intensively investigated by many research groups and considered as promising replacement for standard planar MOSFET based transistor technol- ogy, since classic geometric downscaling of the MOSFET devices dimensions is approaching critical physical bar- riers and is reported to come to an end (1). Our pro- posed NWFET (2)-(4) is an unipolar nanowire device, using midgap Schottky-barrier contacts as source and drain (S/D) electrodes, where the NWFET device type (i.e. NMOS or PMOS) can be selected by a back-gate control voltage. Additionally, we investigated the high- temperature properties of these novel NWFETs devices, since with shrinking device dimensions oxide-leakage and pn-junction leakage becomes increasingly dominant, thus degrading the device behavior, i.e. the optimal values for the ION and IOF F. The described problems become even more severe when the operating ambient temperature increases. In addition, the ability to select the device type (i.e. NMOS or PMOS) by back-gate voltage of the NWFETs transistor adds to the versatility of the device concept in which the two complementary device types are interchangeable on the fly. For device fabrication, a standard top-down fabrication technology has been used, forming the nanowire by means of well established lithog- raphy and subsequent reactive ion etching. Fig. 1 gives a schematic view of the device set-up on a conventional SOI substrate, that was used to demonstrate the process technology and device functionality. Latter, these devices are intended to be realized on MultiSOI substrates.