M. Berroth
Universität Stuttgart, Electrical Engineering, Faculty Member
We present an analytical charge conservative large signal model for MODFETs, which is valid up to MM-wave frequencies. Although the model equations are simple, an excellent accuracy in the representation of the nonlinear elements of the... more
We present an analytical charge conservative large signal model for MODFETs, which is valid up to MM-wave frequencies. Although the model equations are simple, an excellent accuracy in the representation of the nonlinear elements of the FET is achieved. The model was used for the successful design of a 2-stage power amplifier for 60 GHz
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ABSTRACT For the realisation of mobile communication products in the low GHz range a lot of different technologies are available. The well known GaAs technologies with MESFETs and heterostructures are in keen competition with Si and SiGe... more
ABSTRACT For the realisation of mobile communication products in the low GHz range a lot of different technologies are available. The well known GaAs technologies with MESFETs and heterostructures are in keen competition with Si and SiGe bipolar and latterly CMOS technologies. Some of these circuits, such as low noise amplifiers (LNA's), require a optimisation for minimum noise figure. Thus an evaluation of the different technologies with regard to the noise figure is of great interest. This paper aims at classifying different technologies concerning their noise performance
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ABSTRACT A receive equalizer IC implemented in 0.13 mum standard CMOS technology is presented. The equalizer filter works with sampled analog signals within a half-rate architecture. Due to its discrete-time nature, the circuit operates... more
ABSTRACT A receive equalizer IC implemented in 0.13 mum standard CMOS technology is presented. The equalizer filter works with sampled analog signals within a half-rate architecture. Due to its discrete-time nature, the circuit operates continuously on bit rates ranging from 0.5 Gbit/s to 10 Gbit/s. The equalizer core consists of a 3-tap finite-impulse-response filter and a subsequent decision-feedback filter with first and second post cursor feedback taps. Up to 24 dB channel loss at the Nyquist frequency can be compensated. The reception of a 2 31-1 PRBS binary data stream transmitted over a 90 cm long trace on FR4 with 10 Gbit/s and over a 173 cm long trace with 7 Gbit/s with a BER < 10-12 and receive-only equalization is presented. The power consumption of the equalizer core is 21 mW and the core area is 60 mum times 56 mum
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In this paper an envelope tracking system with a maximum output power of 38 dBm operating at 2.06 GHz is presented. Static and dynamic measurements are performed. For a UMTS test signal with a peak-to-average power ratio of 11.2 dB... more
In this paper an envelope tracking system with a maximum output power of 38 dBm operating at 2.06 GHz is presented. Static and dynamic measurements are performed. For a UMTS test signal with a peak-to-average power ratio of 11.2 dB power-added efficiency can be enhanced by 4 % to a value of 16.4 %.
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In this paper a phase shifter for optically generated RF signals at 5 GHz including a liquid crystal (LC) amplitude modulator is presented. A fibre coupled polymer dispersed liquid crystal cell is used to achieve a polarisation... more
In this paper a phase shifter for optically generated RF signals at 5 GHz including a liquid crystal (LC) amplitude modulator is presented. A fibre coupled polymer dispersed liquid crystal cell is used to achieve a polarisation independent setup. The phase shifter covers the full 360° range and offers the possibility to adjust phase and amplitude of the RF signal
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ABSTRACT This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is... more
ABSTRACT This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is applied which reduces the total input capacitance by 50%. High-impedance inputs with emitter followers and internal reference voltage generation make it suitable for applications that require precise on-chip voltage monitoring. For a low-frequency input signal, measured SNDR and SFDR of the presented SAR ADC are 48.7 dB and 57.8 dB. The effective resolution bandwidth (ERBW) is 19 MHz. The ADC draws 17.4 rnA from a 2.6 V supply including reference voltage generation, clock drivers and emitter follower buffers for input and reference voltages. The die area is 2.1 × 0.7 mm2 with the ADC core occupying 1 × 0.5 mm2. A formula for relating static nonlinearity (INL) measurements with dynamic SNDRIENOB measurements is derived. From output codes recorded with constant input voltages, the distortion power caused by nonlinearity and the noise of the reference voltage source and the comparator are determined. After adapting them to sinusoidal inputs, the expected impact on SNDR and ENOB is derived.
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ABSTRACT A novel architecture of a track and hold (T&H) circuit for the realization of a high speed analog demultiplexer is presented in InP DHBT Technology. The architecture allows a sampling rate flexible demultiplexing of an... more
ABSTRACT A novel architecture of a track and hold (T&H) circuit for the realization of a high speed analog demultiplexer is presented in InP DHBT Technology. The architecture allows a sampling rate flexible demultiplexing of an analog input signal. The demultiplexer features a measured THD above 32 dB and a SFDR above 35 dB with a differential input voltage of 0.5V-PP when operating at 25 GHz. This allows the realization of a 50 GS/s analog-to-digital conversion system.
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Speeding up the data rate in today's fiber optical networks requires a sophisticated higher order modulation. For this purpose high speed ADCs and DACs are necessary with sampling rates above 25 GS/s and a resolution of 6 bit. This... more
Speeding up the data rate in today's fiber optical networks requires a sophisticated higher order modulation. For this purpose high speed ADCs and DACs are necessary with sampling rates above 25 GS/s and a resolution of 6 bit. This drives the combined data rate to 150 Gbit/s. To realize a cost-efficient and fully scalable measurement system for the characterization of the high speed ADCs and DACs, a FPGA board is used which is equipped with gigabit interfaces. These interfaces provide data rates between 6.5 Gbit/s and 11Gbit/s. In this paper we describe the hardware which is necessary to build up the measurement system and we describe the architecture of the FPGA logic which is implemented by means of VHDL.
Research Interests: Electronic Engineering, Computer Science, FPGA, Synchronization, Hardware Description Languages, and 14 moreVhdl, Radiation Detectors, Protocols, Hardware, Field Programmable Gate Array, Decoding, High Speed, Cost Efficiency, Fiber Optic, Logic Design, Measurement System, GIGABIT, Higher order, and Field programmable gate arrays
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M. Grözing, M. Berroth, E. Gerhardt, B. Franz, W. Templ, High-speed ADC building blocks in 90 nm CMOS, 4th Joint Symposium on Opto-and Microelectronics Devices and Circuits (SODC) 2006, Duisburg, Germany, September 2-8. ... UNIVERSITÄT... more
M. Grözing, M. Berroth, E. Gerhardt, B. Franz, W. Templ, High-speed ADC building blocks in 90 nm CMOS, 4th Joint Symposium on Opto-and Microelectronics Devices and Circuits (SODC) 2006, Duisburg, Germany, September 2-8. ... UNIVERSITÄT STUTTGART Institut ...
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We present a sealed, permanent, compact and efficient optical fiber-to-chip interface utilizing the wide-spread grating coupler. The easily produced fiber link is based on the reflection in an angle-polished fiber with a reflective metal... more
We present a sealed, permanent, compact and efficient optical fiber-to-chip interface utilizing the wide-spread grating coupler. The easily produced fiber link is based on the reflection in an angle-polished fiber with a reflective metal coating. Efficiencies for different coupling methods to grating couplers are compared.
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Using ST 0.13-mum CMOS technology, a class A power amplifier has been developed for the global system for mobile communication in Europe. To solve the problem of low breakdown voltage in deep-submicrometer CMOS technology, the... more
Using ST 0.13-mum CMOS technology, a class A power amplifier has been developed for the global system for mobile communication in Europe. To solve the problem of low breakdown voltage in deep-submicrometer CMOS technology, the high-voltage/high-power (HiVP) device configuration is used. With the HiVP configuration, a large voltage can be divided by several devices so that the voltage drop on each device can be limited under the breakdown voltage. The measurement results show that the output power of 29.5 dBm has been achieved at the frequency of 900 MHz. The linear power gain reaches 11.5 dB and the maximum power-added efficiency is as high as 34.5%.
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I. INTRODUCTION THE POWER divider and combiner are very important components for microwave power amplifiers. Recent years have seen a worldwide effort to develop dual-band power dividers [1][5] due to the trend of multiband mobile... more
I. INTRODUCTION THE POWER divider and combiner are very important components for microwave power amplifiers. Recent years have seen a worldwide effort to develop dual-band power dividers [1][5] due to the trend of multiband mobile phones. One of the frequently used power ...
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A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented. In experimental tests, the ADC front-end achieves more than 35 dBc SFDR and more than 28 dB SNDR up to 43 GHz. Furthermore, sampling of 100... more
A 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS based on charge sampling is presented. In experimental tests, the ADC front-end achieves more than 35 dBc SFDR and more than 28 dB SNDR up to 43 GHz. Furthermore, sampling of 100 Gbaud (=200 Gb/s) PAM-4 signals with an EVM of 11.3% for 400k received symbols is demonstrated.
ABSTRACT This paper reports a GaN switching power amplifier with a complementary SiGe driver stage in a hybrid setup. The gain of the overall amplifier module is higher than 40 dB. Drain efficiency and an overall lineup efficiency of 60 %... more
ABSTRACT This paper reports a GaN switching power amplifier with a complementary SiGe driver stage in a hybrid setup. The gain of the overall amplifier module is higher than 40 dB. Drain efficiency and an overall lineup efficiency of 60 % and 47 % respectively could be achieved at a bit rate of 1 Gbps when operating with a periodic drive signal. An operation up to 4 Gbps using a pseudo random pulse sequence is demonstrated. To the author's knowledge, this is the first time a GaN switching amplifier with a SiGe driver is demonstrated. Furthermore, such a high gain combined with the efficiencies at bit rates above 1 Gbps has not been presented yet.
ABSTRACT A limiting amplifier implemented in 0.35 μm SiGe-bipolar technology for bit rates up to 56 Gbit/s is presented. The amplifier input sensitivity for a bit error rate of 10^(-6) is 7 mVpp at 12.5 Gbit/s and 25 mVpp at 50 Gbit/s.... more
ABSTRACT A limiting amplifier implemented in 0.35 μm SiGe-bipolar technology for bit rates up to 56 Gbit/s is presented. The amplifier input sensitivity for a bit error rate of 10^(-6) is 7 mVpp at 12.5 Gbit/s and 25 mVpp at 50 Gbit/s. The large-signal bandwidth at a sinusoidal input voltage of 56 mVrms is 41 GHz and the small-signal gain-bandwidth-product at an input voltage of 5.6 mVrms is 2.4 THz. The output differential voltage swing can be varied from 0.36 Vpp to 1.8 Vpp. The circuit can operate from a 1.9 V to 3.0 V supply and consumes 38 mW to 420 mW depending on the supply and bias control voltage. The circuit consists of a main output path and two auxiliary paths that can be controlled independently of the main one. The amplifier gain cells employ emitter followers and a differential pair amplifier without any inductive peaking.
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An 15th order bandpass delta-sigma modulator for class-S power amplifiers is presented. The modulator is based on a third order low pass prototype which is designed to meet the requirements for signal-to-noise ratio (SNR) of major mobile... more
An 15th order bandpass delta-sigma modulator for class-S power amplifiers is presented. The modulator is based on a third order low pass prototype which is designed to meet the requirements for signal-to-noise ratio (SNR) of major mobile communication standards in a bandwidth of around 30 MHz. The transform z−1 → z−5 leads to a repetition of the low pass notch in the noise transfer function (NTF) at frequencies f = n/5fs, n = 1, 2, 3, 4, 5, &. Apart from sinc filtering due to rectangular output pulses the NTF shape is equal in all frequency bands. The two lower frequency bands at f = 1/5fs, 2/5 fs are independent from each other and can be used for concurrent transmission in the 450 MHz and 900 MHz band. The paper investigates the modulator with respect to the signal to noise ratio, the stability and the coding efficiency versus input amplitudes of tones in both frequency bands.
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The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes.... more
The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10
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M. Berroth, M. Lang, Z.-G. Wang, Z. Lao, A. Thiede, M. Rieger Motzer, W. Bronner, G. Kaufel, K. Kohler, A. Hulsmann, Jo. Schneider ... Fraunhofer Institut fur angewandte Festkorperphysik, Tullastr. 72 D-79108 Freiburg, Germany Fax:... more
M. Berroth, M. Lang, Z.-G. Wang, Z. Lao, A. Thiede, M. Rieger Motzer, W. Bronner, G. Kaufel, K. Kohler, A. Hulsmann, Jo. Schneider ... Fraunhofer Institut fur angewandte Festkorperphysik, Tullastr. 72 D-79108 Freiburg, Germany Fax: 49-761-5 159-565, ...
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In this paper an 8 W GaAs HEMT power amplifier for operation in envelope tracking systems is presented. The application targeted is UMTS downlink operation with a peak-to-average ratio of about 7 dB. By varying the drain bias voltage... more
In this paper an 8 W GaAs HEMT power amplifier for operation in envelope tracking systems is presented. The application targeted is UMTS downlink operation with a peak-to-average ratio of about 7 dB. By varying the drain bias voltage between 5 V and 12 V the compression point can be shifted in the required area. Power-added efficiency is more than 45 % in this area and above 52% in the area of average output power of a UMTS signal. Gain can be kept above 14 dB in this operation mode with a variation of 3 dB.
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Es werden Untersuchungen zur Transmission von Flüssigkristallmodulen im Bereich der beiden optischen Fenster um 1300 nm und 1550 nm vorgestellt. Teststrukturen werden als optische Schalter betrieben und das on-off-Kontrastverhältnis... more
Es werden Untersuchungen zur Transmission von Flüssigkristallmodulen im Bereich der beiden optischen Fenster um 1300 nm und 1550 nm vorgestellt. Teststrukturen werden als optische Schalter betrieben und das on-off-Kontrastverhältnis charakteri-siert. Darüber hinaus werden speziell gefertigte Fabry-Perot-Zellen vorgestellt und deren Transmissionsverhalten sowie die Temperatur-und Langzeitstabilität unter-sucht.
In this paper an FPGA-based test system for high-speed transmission experiments with integrated photonic receivers is presented. Pseudorandom binary sequences are generated inside the FPGA and encoded as either differential quadrature... more
In this paper an FPGA-based test system for high-speed transmission experiments with integrated photonic receivers is presented. Pseudorandom binary sequences are generated inside the FPGA and encoded as either differential quadrature phase shift keying (DQPSK) or quadrature phase shift keying (QPSK) signals. The DQPSK encoder uses a 64-fold parallel-prefix-layers architecture for real-time operation which allows for a maximum internal encoder data rate of 64 Gbit/s. Two-fold parallel data streams of I and Q signals suitable for driving an optical IQ-modulator can be transmitted and received by four 12.5 Gbit/s transceivers. Integrated bit error testers are used to determine bit error rates in real-time.
ABSTRACT This paper investigates the supply modulation concept to improve the efficiency of power amplifiers in back off. The modulator is a class AD modulator which has a high efficiency while keeping a large signal bandwidth. In an... more
ABSTRACT This paper investigates the supply modulation concept to improve the efficiency of power amplifiers in back off. The modulator is a class AD modulator which has a high efficiency while keeping a large signal bandwidth. In an experimental setup the efficiency of a 5 W GaAs power amplifier can be improved from 28% to 40% at 7dB back off.
We present a 1×2 phased array antenna with optical beamforming and integrated phase shifter. We are able to steer the radiation pattern by a continuous phase shift up to 360°.
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... IC.-A. Chakam, **W. Vogel ,**H. Yilmaz, **M. Berroth, *W. Freude 'High-Frequency and Quantum Electronics Laboratory, University of Karlsruhe Kaiserstr. 12 D-76128 Karlsruhe, Germany ... The middle layer (RT du-roid 5880, dd =... more
... IC.-A. Chakam, **W. Vogel ,**H. Yilmaz, **M. Berroth, *W. Freude 'High-Frequency and Quantum Electronics Laboratory, University of Karlsruhe Kaiserstr. 12 D-76128 Karlsruhe, Germany ... The middle layer (RT du-roid 5880, dd = 0.508 mm) is metallized on its up-per side. ...
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High speed time-interleaved analog-to-digital converters (TIADCs) suffer from gain, offset and timing errors wich reduce their effective resolution. By a posterior digital error correction this errors can be corrected. To achieve this,... more
High speed time-interleaved analog-to-digital converters (TIADCs) suffer from gain, offset and timing errors wich reduce their effective resolution. By a posterior digital error correction this errors can be corrected. To achieve this, known error models are applied to the converters. Error estimation and error correction approaches are derived from these models. A realization of a digital real-time posterior error estimation and error correction is implemented in VHDL for a 3 to 6 bit analogto- digital converter with a sampling rate up to 24GS/s.
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ABSTRACT Envelope tracking is a promising means to enhance radio frequency power amplifier efficiency for signals with non-constant envelope. The adaption of the power amplifier supply voltage is performed by a voltage modulator circuit,... more
ABSTRACT Envelope tracking is a promising means to enhance radio frequency power amplifier efficiency for signals with non-constant envelope. The adaption of the power amplifier supply voltage is performed by a voltage modulator circuit, which is mainly based upon power electronics circuits, but requires bandwidths up to the MHz region. This paper introduces the benefits and challenges of envelope tracking and gives an overview of several voltage modulator architectures. Current measurement data of a class-G modulator is presented as well.