2028
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
RF Circuit Design Aspects of
Spiral Inductors on Silicon
Joachim N. Burghartz, Senior Member, IEEE, D. C. Edelstein, Mehmet Soyuer, Senior Member, IEEE,
H. A. Ainspan, and Keith A. Jenkins, Member, IEEE
Abstract—The design and optimization of spiral inductors on
silicon substrates, the related layout issues in integrated circuits,
and the effect of the inductor-Q on the performance of radiofrequency (RF) building blocks are discussed. Integrated spiral
inductors with inductances of 0.5–100 nH and Q’s up to 40
are shown to be feasible in very-large-scale-integration silicon
technology. Circuit design aspects, such as a minimum inductor
area, the cross talk between inductors, and the effect of a
substrate contact on the inductor characteristics are addressed.
Important RF building blocks, such as a bandpass filter, low-noise
amplifier, and voltage-controlled oscillator are shown to benefit
substantially from an improved inductor-Q.
(a)
I. INTRODUCTION
PIRAL inductors are important, performance-limiting
components in monolithic radio-frequency (RF) circuits,
such as voltage-controlled oscillators (VCO’s), low-noise
amplifiers (LNA’s), and passive-element filters [1], [2].
The quality factor (Q) of the inductors is limited by the
resistive losses in the spiral coil and by the substrate losses
im
/re
with
the impedance of the inductor].
[
It has been shown recently that high Q’s can be achieved
in state-of-the-art silicon fabrication processes [3], [4]. Here,
we discuss inductor optimization for RF circuit design and
specific layout issues, verified by experiments. In particular,
design, modeling, and specific circuit layout issues of spiral
inductors on silicon substrates are discussed in Section II. In
Section III, we evaluate and demonstrate the significance of
the inductor-Q in three basic RF circuits, and Section IV will
provide a summary of the results and some conclusions.
S
II. DESIGN AND CIRCUIT IMPLEMENTATION
OF SPIRAL INDUCTORS ON SILICON
A. Basic Design, Modeling, and Optimization
A spiral inductor can be built on a silicon substrate by using
the multilevel interconnects that are routinely provided with
today’s mainstream silicon fabrication processes. A minimum
of two metal layers is needed to build the basic spiral coil (M3
in Fig. 1) and an underpass contact (M2 in Fig. 1) to return the
inner terminal of the coil to the outside. The lateral structure
, the wire
of an inductor is defined by the number of turns
and space
, and the total area covered
,
width
Manuscript received April 15, 1998; revised June 26, 1998.
The authors are with the IBM Research Division, T. J. Watson Research
Center, Yorktown Heights, NY 10598 USA (e-mail: burgh@us.ibm.com).
Publisher Item Identifier S 0018-9200(98)08857-X.
(b)
Fig. 1. (a) Plan and (b) cross-sectional views of a spiral inductor structure
(metal layer M1 is omitted to reduce COx ).
as shown in Fig. 1(a). A simple lumped-element model is
instrumental in describing the electrical device characteristics
(Fig. 2). The spiral coil itself is modeled by an ideal inductance
, a series resistance
, representing the ohmic losses
. With the
in the coil, and an interwire capacitance
integration on a silicon substrate, oxide capacitances
and bulk resistances
have to be added to the model
to represent the RF signal flow through the silicon substrate
(the capacitance of the silicon substrate was neglected). In
BiCMOS processes, silicon substrates with a typical resistivity
of 10 -cm are used so that eddy currents in the silicon are
negligible [3]. CMOS, in contrast, usually has p/p substrates
( 0.01 -cm), in which eddy currents can be considerable.
The effect of the eddy currents can be represented in the model
.
and
also depend on the
in Fig. 2 by a reduced
substrate thickness and whether the chip is mounted onto a
metal plate in the package or onto a lossless substrate [5].
In the preferred configuration of a substrate with a high, but
still conventional, resistivity such as 10 -cm, the substrate
potential can only be defined laterally spaced from the spiral
coil, which is represented in Fig. 2 as a contact to the node in
and
near the outer terminal. The substrate
between
0018–9200/98$10.00 1998 IEEE
BURGHARTZ et al.: RF CIRCUIT DESIGN ASPECTS
2029
Fig. 2. Lumped-element model of a spiral inductor on silicon, including a
possible substrate contact.
Fig. 4. Plan and cross-sectional (inset) views of Cu inductors. Also shown
are inductors with metal dummy arrays in their center area.
Fig. 3. Electrical characteristics and lumped-element model (inset) of a
3.3-nH Cu inductor (lines
modeling, markers
measurements).
=
=
in
contact can be placed close to the inductor (small
Fig. 2) or can be left floating by spacing any substrate contact
in Fig. 2). The effect of
away from the device (large
the substrate contact on the inductor characteristics will be
explained in Section II-C. The Q develops a distinct maximum
Q
at a frequency
, which depends on the coil losses
and the substrate losses
and
. For good
parameter control and ease in circuit design, it is important
. This is
that the inductance be constant near
achieved by using a minimum doping concentration under
), so that self-resonance
the inductor (i.e., a high value of
occurs mainly via the small interwire capacitance
sufficiently beyond
instead of via the comparably much
, near
(Fig. 3). The agreement of modeling and
larger
are usually very good in spite
measurements results near
of the simplicity of the model, as shown in Fig. 3.
From the typical frequency dependence of Q, as shown
in Fig. 3, it is obvious that the optimization of a spiral
and
inductor has to aim for a coordinated reduction of
, determined by the total impedance
the substrate losses in
and
, in order to arrive at the highest possible
of
Q
at
. The parasitics
and
are responsible
is small.
for the falloff of Q beyond , provided that
In mainstream silicon fabrication processes, one can take
advantage of multilevel interconnects by looking for a tradeoff
between the shunting of several metal layers in order to
and by omitting the lowest metal layers to reduce
lower
(M1 omitted in Fig. 1). Further, the available blockout
Fig. 5. Frequency dependence of inductance and quality factor of an 80-nH
Cu inductor on silicon and on quartz substrates.
masks should be applied in the fabrication process to keep
the doping level under the spiral coil at a minimum in order
[Fig. 1(b)]. This is a conservative approach
to maximize
since it does not require any alteration of the fabrication
processes that are used in today’s manufacturing lines. An
values by
innovative approach can lead to much higher Q
introducing low-resistive metallization and low-loss substrates.
Recent results of inductor optimization have benefited in
particular from the introduction of copper (Cu) Damascene
interconnect technology (Fig. 4), which leads to a reduced
and thus an increased Q
at the currently relevant
frequencies in comparison to aluminum (Al) interconnects.
Figs. 3 and 5 show that this new interconnect technology
enables Q values beyond ten even for very large inductances.
It is also shown in Fig. 5 that the elimination of the substrate
losses by using micromachining techniques
in addition to the lower coil resistance leads to a further
at a higher
(“quartz” versus “silicon” in
increase of Q
Fig. 5). In this experiment, the substrate silicon was removed
by using selective etching of the silicon, and the remaining
thin-film structure was bonded onto a quartz substrate. The
micromachined version of the Cu inductor in Fig. 3 had a
at 6 GHz. The electrical characteristics of a 16Q
turn inductor with 80-nH inductance in Fig. 5 show that the Cu
10 (“silicon”), but with
metallization already leads to Q
2030
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
(a)
Fig. 6. Maximum quality factors versus inductances for Al and Cu inductors.
The ranges of f0 , and of the inductor total areas, are listed as insets at the
top and bottom, respectively.
the additional removal of the substrate losses, an additional
and an elevation of
become
twofold increase of Q
possible (“Quartz”).
Fig. 6 shows that the 2 lower resistivity and the 2
greater conductor thickness [ 4 m versus 2 m ( in inset
of Fig. 4)] of Cu compared to the Al process led to a 3–4
increased Q
over the entire range of feasible inductance
is, to first order, set
values. The figure also shows that
by the inductor area. It is further obvious from the results
in Fig. 6 that large inductance values typically combine with
comparably small Q’s, while the opposite is the case for small
inductances. That is mainly a result of the substrate losses: an
increase of the number of turns in the spiral coil or an increase
of the coil area results in an increased magnetic flux, and thus
a high inductance value, but also in a proportionally higher
series resistance. From that point of view, the Q should not
be very different if one compares large to small inductances.
Taking into account the RF current flow through the substrate,
however, results in a comparably stronger degradation of Q for
large inductance values, as observed in Fig. 6. Also, for the
same total area—i.e., the same “footprint”—of the spiral coil,
a small inductance value combines with a comparably larger Q
[3]. Fortunately, in many RF building blocks, such as filters or
impedance matching networks, the required inductance values
are smaller at the higher frequencies, at which a comparably
higher Q is needed.
B. Design for Minimum Inductor Area
The inductor size should be minimized, as inductors consume a large fraction of the circuit area [6]. This can first be
achieved by choosing a minimum width of the coil conductor.
226
For three Al test inductors with the same area (226
m ) and
, we measured that Q
, was the largest for
m
nH Q
, Q
was
medium for
m and
m
nH,
, and Q
was the smallest for
m and
Q
m
nH, Q
, all at
GHz
nH,
[Fig. 7(a)]. (For the Cu process, those values were
Q
versus
nH, Q
versus
nH, Q
.) Fig. 7(a) shows that the main reason for
this difference in Q is likely caused by the skin effect in the
(b)
Fig. 7. Inductance and Q versus frequency of (a) inductors with two different
widths but the same total area and (b) inductors with different total areas but
similar electrical characteristics.
coil conductor layer, which leads to current’s crowding to
the edges of the conductor. The increase in conductor width
m to
m does not lead to a
from
significant reduction of the high-frequency resistance, as seen
from the very similar increase of Q with frequency below in
Fig. 7(a). The falloff of Q beyond , however, occurs at lower
[2].
frequencies for the wider conductor due to the larger
For those reasons, the width of the coil conductor should only
be large enough to reduce the ohmic losses in balance with
other losses in the inductor structure. An increase beyond this
level will have detrimental effects on the inductor-Q.
m did provide a sufficiently high
(20
Since
GHz), the inductor could be fabricated with a minimum
and
m, reducing the area consumption significantly.
m and
Based on this conclusion, an Al inductor with
m had
nH and Q
at
GHz, with a reduced area of 160 160 m , a result that was
very similar to that of the 2 larger inductor with an area of
m [Fig. 7(b)]. The results
225 225 m and with
certainly do not indicate a general design rule for the spiral coil
layout, but they illustrate how effectively the inductor area can
be minimized without sacrificing the electrical characteristics.
Chip area can also be conserved by constructing an inductor
with two vertically stacked spiral coils instead of using one
coil with an underpass contact [7]. An inductance of 7 nH
were achieved with two stacked Cu coils
and Q
compared to
nH and Q
for a single-coil
Cu inductor, showing that a higher inductance value can be
. The improvement,
gained for a given area and a similar Q
BURGHARTZ et al.: RF CIRCUIT DESIGN ASPECTS
2031
(a)
Fig. 9. Insertion loss as a function of the spacing of inductor pairs.
(b)
Fig. 8. Frequency dependence of inductance and Q of inductors built at metal
levels M5 and M6 over SRAM interconnects at M1–M3 or over silicon.
however, comes at the expense of ’s being reduced from 2.2
’s being lowered from 12.8 to 4.3 GHz,
to 1.8 GHz and
restricting the range of operating frequency.
Another potential way to conserve chip area is to build the
inductors over circuitry or to place circuitry in the open center
space of an inductor. To explore the first option, an inductor
was built at the metal levels M5 and M6 over dense SRAM
interconnects fabricated at M1–M3. The result in Fig. 8(a)
showed that fabrication of inductors over circuitry was not
was
a viable option to conserve chip area because Q
4 smaller and
was 5 lower compared to the case
without the SRAM wiring. Hollow Cu inductors with two turns
and with or without metal dummy features (not grounded)
with different metal pitches in the center area (Fig. 4) were
fabricated to investigate qualitatively the option of placing
circuitry in the inductor’s center space. While the structure
, Q
was
with the free center area had Q
measured for the less dense dummy features, and with the
was 14 [Fig. 8(b)]. The inductance,
dense dummy lines Q
however, changed by less than 5%, showing that devices can
be added to the inductor’s center area as long as the density
is moderate, no closed wire loops are formed, and control of
the Q is not critical.
C. Circuit Layout Issues
Besides the inductor-size optimization, the electromagnetic
coupling between inductors can complicate the RF circuit
design and layout. We investigated this issue by fabricating
226 m area each) with differpairs of inductors (226
ent spacings, wired for two-port -parameter testing (Fig. 9,
inset). The inductor pairs were built over 10- -cm silicon
substrates. The insertion loss, which indicates the degree of
coupling, was found to be 29 dB at 5 GHz if the two
inductors were placed as close as possible (i.e., 236 m
center–center). The insertion loss was reduced with increasing
inductor spacing, having a value close to that measured for
the open contact pads near 500 m. With the inductor of the
second port shorted, we found that even for the minimum
distance, an effect on was not noticeable and Q was degraded
by only 5%. If, however, the inductor pairs were built over
p p substrates, as typically used in CMOS technology, a
considerable capacitive coupling between the ports would be
observed, which would overshadow the electromagnetic crosstalk effects [8]. On 10- -cm substrates, the inductor proximity
effects were small enough not to restrict the RF circuit layout
in most cases. If inductors are used in LNA’s, however, where
power levels can be extremely low, cross talk can become a
serious issue, and adequate spacing of the LNA to the other
circuitry and special isolation structures become necessary.
Another layout issue results from the poor definition of the
substrate bias if the substrate resistivity is high. The substrate
bias can only be defined by using a substrate contact outside
of the spiral coil, which would be different in the regions
underneath the coil as a result of the high substrate resistivity.
In the model, the substrate contact can be represented by a
, as shown in Fig. 2. The effect of the contact on
resistor
the electrical characteristics of the one- and two-port inductor
configurations has been investigated, and the results were
presented elsewhere [9]. In that work, the Q-factor in the
one-port configuration (one terminal at ground) was found to
if a string
increase by 40% at the expense of a reduced
of substrate contacts enclosing the spiral coil (halo substrate
and
contact [9]) was applied. This tradeoff between Q
applies to silicon substrate contacts as well as to metal ground
shield structures underneath the spiral coil [5]. The effect of
is significantly
a substrate contact is diminished, and Q
reduced, if the silicon resistivity is low [9]. The effect of the
substrate contact on the inductor characteristics is one example
of the effect of the circuit layout on the device models in
2032
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
(a)
(a)
(b)
Fig. 10. (a) Schematics and (b) insertion loss of a coupled-resonator bandpass filter with use of either Al or micromachined Cu inductors. The 3-dB
bandwidth relative to the center frequency (the Q of the filter) was set to
5.4 by the capacitance ratio.
monolithic RF systems, indicating that the traditional concept
of discrete device models may not be sufficient for RF circuit
design on silicon.
III. EFFECT OF INDUCTOR-Q
ON
=
RF CIRCUIT PERFORMANCE
The effect of the inductor-Q is very obvious in a bandpass
filter (BPF) if high-Q metal-insulator-metal capacitors are
used [Fig. 10(a)]. A first version of the BPF was built using
Al inductors with a Q of 7.6. For the selected filter-Q of
5.5, based on the ratio of the capacitance value in the
inductance–capacitance resonator and of the capacitance that
couples the resonators, an insertion loss of 10 dB was
measured [Fig. 10(b)]. The same BPF fabricated on a p p
substrate had 15-dB insertion loss due to a reduced inductorQ of 4.6 [not shown in Fig. 10(b)]. With micromachined Cu
), the insertion loss improved to 3.5 dB.
inductors (Q
Extrapolating from this result, we estimated that for this best
case inductor implementation, a filter-Q of ten can be achieved
with an insertion loss of 5 dB. Those values may still not be
sufficient in some RF designs, indicating that the integration
of RF filters is one of the major challenges in the integration
of monolithic RF transceivers.
As a second RF circuit, a 5.8-GHz LNA was fabricated by
using a 0.5- m SiGe-BiCMOS process1 and was investigated
by simulation [Fig. 11(a)]. In this circuit, a high inductor-Q
allows one to design either for a reduced power consumption
or a maximum figure of merit (FoM) [10], i.e., FoM
S21/(NF
) with the gain S21, the noise figure NF, and
. At
mW and 2-V
the power consumption
1 See
(b)
Fig. 11. (a) Schematic and (b) simulated and measured noise figure and
insertion loss versus frequency of a 5.8-GHz LNA using inductors with Q
8 or 40.
IBM’s SiGe technology home page at http://www.chips.ibm.com/
sige/technology.html.
(a)
(b)
Fig. 12. (a) Schematic and (b) power versus frequency of a 5.0-GHz VCO
using an inductor with Q = 8 or 40.
BURGHARTZ et al.: RF CIRCUIT DESIGN ASPECTS
supply voltage, the FoM was found by simulation to improve
from 0.75 to 1.2 mW if an inductor-Q of 40 was used in
[Fig. 11(b)]. For the fabricated LNA with an
place of Q
mW
and NF
dB
inductor-Q of ten, FoM
were calculated and measured because the emitter inductor in
the circuit was 0.23 nH instead of the desired 0.37 nH. With
mW is expected.
the correct value, FoM
Like the LNA, VCO’s suffer especially from low-Q onchip inductors. A 5.5-GHz SiGe VCO, based on a Colpitts
oscillator [11], was investigated by simulation, assuming a 3-V
supply voltage and a varactor-Q of 30 [Fig. 12(a)]. DC power
reduction was identified as a key benefit of a high inductorQ due to reduced gain requirements from the active circuitry.
At 10-MHz offset, the phase noise was 130 dBc/Hz and the
power was 17.9 mW for an inductor-Q of eight, and 137
, showing that a
dBc/Hz and 5.1 mW were found for Q
5 increase in inductor-Q translates into a 3.5 power savings
and 7-dB better phase noise [Fig. 12(b)].
IV. CONCLUSIONS
In summary, integrated spiral inductors with inductances
ranging from about 0.5 to 100 nH and Q’s up to 40 can be
provided for RF circuit design on silicon by using Al or Cu
interconnect technologies. A low inductance value typically
combines with a comparably high Q at a high . A proper
choice of conductor line width and, in some cases, utilization
of the inductor coil’s inner space for placement of circuitry
can be instrumental to conserve chip area. In most cases,
electromagnetic coupling between inductors is not an issue
that affects the circuit layout. Important RF system building
blocks, such as bandpass filters, LNA’s, and VCO’s, were
found to benefit substantially from an improved inductor-Q.
REFERENCES
[1] N. M. Nguyen and R. G. Meyer, “Si IC-compatible inductors and
LC passive filters,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp.
1028–1031, 1990.
[2] J. R. Long and M. A. Copeland, “Modeling, characterization and design
of monolithic inductors for silicon RF IC’s,” in Proc. Custom Integrated
Circuits Conf. (CICC), 1996, pp. 185–188.
[3] J. N. Burghartz, M. Soyuer, and K. A. Jenkins, “Integrated RF and
microwave components in BiCMOS technology,” IEEE Trans. Electron
Devices, vol. 43, no. 9, pp. 1559–1570, 1996.
[4] J. N. Burghartz et al., “Monolithic spiral inductors fabricated using a
VLSI Cu-Damascene interconnect technology and low-loss substrates,”
in Tech. Dig. Int. Electron Devices Meeting (IEDM), 1996, pp. 99–102.
[5] J. N. Burghartz, “Progress in RF inductors on silicon—Understanding
substrate losses,” in Tech. Dig. Int. Electron Devices Meeting (IEDM),
to be published.
[6] R. G. Meyer et al., “A 2.5 GHz BiCMOS transceiver for wireless
LAN’s,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2097–2104,
1997.
[7] J. Burghartz, K. Jenkins, and M. Soyuer, “Multi-level spiral inductors
using VLSI interconnect technology,” IEEE Electron Device Lett., vol.
17, no. 9, pp. 428–430, 1996.
[8] A. Pun, T. Yeung, J. Lau, F. J. R. Clement, and D. Su, “Experimental
results and simulation of substrate noise coupling via planar spiral
inductor in RF IC’s,” in Tech. Dig. Intern. Electron Devices Meeting
(IEDM), 1997, pp. 325–328.
[9] J. N. Burghartz, A. E. Ruehli, K. A. Jenkins, M. Soyuer, and D. NguyenNgoc, “Novel substrate contact structure for high-Q silicon-integrated
spiral inductors,” in Tech. Dig. Int. Electron Devices Meeting (IEDM),
1997, pp. 55–58.
2033
[10] H. Ainspan et al., “A 6.25-GHz low DC power low-noise amplifier
in SiGe,” in Proc. Custom Integrated Circuits Conf. (CICC), 1997, pp.
177–180.
[11] M. Soyuer et al., “A 2.4-GHz silicon bipolar oscillator with integrated
resonator,” IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 268–270,
1996.
Joachim N. Burghartz (M’90–SM’92) received the
Dipl.Ing. degree from the Technische Hochschule
Aachen, Germany, in 1982 and the Ph.D. degree
from the University of Stuttgart, Germany, in 1987,
both in electrical engineering.
During 1982–1987, he was with the University
of Stuttgart, where he developed sensors with integrated signal conversion with a special focus on
magnetic-field sensors. Since 1987, he has been with
the IBM T. J. Watson Research Center, Yorktown
Heights, NY. His earlier research work at IBM
included device applications of selective epitaxial growth of silicon, Si and
SiGe high-speed transistor design and integration processes, and 0.15-m
CMOS technology. For the past few years, he has been engaged in the
development of circuit building blocks for SiGe RF front ends, with a special
interest in the integration of high-quality passive components on silicon. He
has served at technical conferences such as IEDM, ESSDERC, and BCTM.
He is the author or coauthor of more than 80 technical publications. He has
received five U.S. patents.
D. C. Edelstein received the B.S., M.S., and Ph.D.
degrees in applied physics from Cornell University,
Ithaca, NY, in 1982, 1986, and 1990, respectively.
His thesis work involved ultrafast quantum electronics studies in III–V semiconductors and the
development of new femtosecond lasers and measurement techniques, most notably, the femtosecond
optical parametric oscillator. He currently is a Research Staff Member in IBM’s Research Division
at the T. J. Watson Research Center, Yorktown
Heights, NY. Since 1989, he has worked at IBM
on advanced interconnect technology for VLSI/ULSI applications. This work
has included process integration, advanced materials development, reliability,
electrical performance modeling, interconnect scaling, dielectric, and highspeed measurements. In general, this work was all applied to research of
copper on-chip interconnects. For the past five years, he has played a
leadership role in the development and qualification of copper interconnects
for IBM’s ULSI CMOS programs.
Mehmet Soyuer (S’79–M’88–SM’96) received the
B.S. and M.S. degrees in electrical engineering
from the Middle East Technical University, Ankara,
Turkey, in 1976 and 1978, respectively, and the
Ph.D. degree in electrical engineering from the
University of California, Berkeley, in 1988.
He was a Teaching Associate and Research Assistant at the Middle East Technical University and
at the University of California, Berkeley. He joined
IBM’s T. J. Watson Research Center, Yorktown
Heights, NY, as a Research Staff Member in 1988.
His research work involved high-frequency mixed-signal IC designs, in
particular monolithic phase-locked-loop designs for clock and data recovery,
clock multiplication, and frequency synthesis using silicon technologies.
During 1995–1997, he was a Project Leader for Si and SiGe RF and
microwave IC designs covering frequency bands of 1–20 GHz. In 1997, he
became Manager of the Mixed-Signal Communications IC Design Group.
He is the author of numerous articles in the areas of analog, mixed-signal,
RF, microwave, and nonlinear electronic circuit design. He has received six
U.S. patents. His research interests include high-speed integrated circuits,
technologies, and systems for data communications.
Dr. Soyuer was a NATO Science Scholar from 1979 to 1982. He has
received several IBM Research Division Awards.
2034
H. A. Ainspan received the B.S. and M.S. degrees in electrical engineering
from Columbia University, NY, in 1989 and 1991, respectively.
In 1989, he joined the IBM T. J. Watson Research Center, Yorktown
Heights, NY, where he has been involved in the design of mixed-signal and
RF IC’s for high-speed data links using Si and GaAs technologies. He is the
coauthor of 22 external publications. He has received one patent.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
Keith A. Jenkins (M’98) received the Ph.D. degree
in physics from Columbia University, NY, for work
done in experimental high energy physics.
He was with The Rockefeller University until
1983, when he joined the IBM Research Division
at the T. J. Watson Research Center, Yorktown
Heights, NY, where he first worked in Josephson
technology. He later joined the Silicon Technology
Department, where he worked in a variety of device
and circuit subjects, including high-frequency measurement techniques, electron-beam circuit testing,
radiation-device interactions, and low-temperature electronics. He presently
is a Senior Engineer in the VLSI Systems Department. His current activities
include evaluation of the performance of VLSI circuits, phase-locked loops
and integrated silicon RF circuits, and research into the transient behavior of
silicon-on-insulator FET’s.