Low Power VLSI

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

Day to day VLSI circuit is becoming more complex in regard of architecture and analysis point of view. A high computation design with less power consumption and miniaturization in the area is implicit to the current semiconductor industry. In these, a methodology for error-control parity generator and checker is fundamental of data communication and widely used in error control application. In this paper is the synthesis of the parity generator and checker, which has the unique architecture in terms of architecture complexity. Efficiency in terms of the VLSI performance attributes such as delay, power, and area. Then with the use of GDI technique a new architecture of parity generator and checker is introduced, we achieved a design with low supply voltage operation. The 3-bit parity generator and checker based on GDI technique is successful, simulated and tested at 0.5V, 1V, 1.5V, 2V supply voltage and consumed power at these voltages are 5µw, 2.5µw, 3.3µw and 0.2ns, 0.3ns, and 0.8ns worst condition of delay respectively.

En este trabajo se desarrolla los conceptos de un sistema VLSI, los cuales representan a la mayoría de los microchips de hoy en día. Pasaremos por la historia de los chips de computadoras viendo su evolución en el tiempo y el pronóstico para el futuro. Se mostrarán los distintos componentes que componente un chip y como estos son implementados en la fabricación a VLSI.

In today’s VLSI field the exponentially increasing factor of integration takes the techniques of chip designing to be more cared about both switch level (eg. device, logic gate design, etc.) and chip level (eg. pad design, floorplanning, routing, etc.) as size of chip is continually decreasing and power consumption challenge is getting tougher. To design a complete & successful functional chip, pad frame design and floorplanning are also challenging. This study is an attempt to present a VLSI design of pad frame with less power consuming I/O architecture with an efficient way of floorplanning which includes block placement, global routing, detail routing. MAGIC is used as layout designing CAD tool to design the pad frame as it is the easiest and worldwide CAD tool for VLSI layout design, and for simulation purpose PSpice is used. This study presents details of the key research work, results, techniques and efficient way of pad frame design as well as floorplanning.

VLSI IEEE Projects 2017 | IEEE 2018 VLSI Project Titles
IEEE 2017-18 VLSI Project Titles
LOW POWER
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption
Resource-Efficient SRAM-based Ternary Content Addressable Memory
Write-Amount-Aware Management Policies for STT-RAM Caches
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
Efficient Designs of Multi-ported Memory on FPGA
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission
Scalable Device Array for Statistical Characterization of BTI-Related Parameters
AREA EFFICIENT/ TIMING & DELAY REDUCTION
VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
Efficient Soft Cancelation Decoder Architectures for Polar Codes
Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields
Antiwear Leveling Design for SSDs With Hybrid ECC Capability
Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems
Audio, Image and Video Processing
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
An FPGA-Based Hardware Accelerator for Traffic Sign Detection
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
Time-Encoded Values for Highly Efficient Stochastic Circuits
Design of Power and Area Efficient Approximate Multipliers
VERIFICATION
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
NETWORKING
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um)
Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
Delay Analysis for Current Mode Threshold Logic Gate Designs
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz
A 65-nm CMOS Constant Current Source with Reduced PVT Variation
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy
Preweighted Linearized VCO Analog-to-Digital Converter
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression
Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
On Micro-architectural Mechanisms for Cache Wear out Reduction
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing
A 0.45 V 147–375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an optimized and dedicated hardware. The real time implementation places several constraints such as area occupied, power consumption , etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression sequence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

Power consumption has emerged as a principle theme in today’s widely and frequently used portable electronics. The datapath consumes roughly 30% of the total power of a modern day high performance microprocessor. Adders are key components used in datapaths and, therefore, careful design and analysis is required for these units to obtain optimum performance So the full adder designs with low power characteristics are becoming more popular these days. This paper presents a novel low power, energy efficient full adder circuit implementation for ultra deep submicron design. With rapid technology scaling, the main focus in low power design is targeted to reduce the static power while trading other vital requirements such as driving capability, delay, total power and noise immunity. Based on the fact that transmission logic has good driving capability and full signal swing than pass transistor logic, a new full adder cell is proposed to reduce delay and power-delay product (PDP).The simul...

Device density in VLSI today enforces the process of chip designing much more complex; whereas MAGIC CAD tools made the IC design in this work, comparatively easier. Study on various amplifiers for sensor applications showed that their powers ranged from a few milliamperes to a few hundred milliamperes at the submicron fabrication processes by MOSIS, but within the affordable cost. Objectives of lowering the power at least by 1000 times in those fabrication processes engaged this research towards completing a new design, called the mirror-amplifier. This design is verified for precise functional behavior for the sensor and total power consumption, using MAGIC extractor and PSPICE electrical simulation tools. A compact model chip layout made silicon area more efficient for MOSIS tiny-chip fabrication in 0.6µm processes. To make even more economical, a multi-die placement technique was applied to the chip layout for this tiny-chip in silicon area of 1500µmX1500µm. MOSIS design rules for multi-die fabrication was verified for process scribe-lines and die packaging. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

In this paper an ultra-low power NAND based multiplexer and flip flop is proposed. The modified design is compared to conventional 4*1 multiplexer and shows dynamic and static power reduction up to 32.077% and 45.055% respectively while for JK flip flop, dynamic and static power reduction up to 84.25% and 92.47%respectively. Simulations have been done on 270C temperature and 50MHz frequency. With every selection line input dynamic power consumption is calculated, static power consumption, delay and power delay product. The simulations have been carried out on Tanner EDA.

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high-speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixed-mode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.. KEYWORDS Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very Large Scale Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge full adder.

In this paper, GDI technique implementation of modified Carry Select Adder is presented for the low power applications. The proposed Carry Select Adder can be used RCA using GDI and same size of BEC (binary to excess-1) and Multiplexer. Simulation is performed in T-SPICE using 45nm technology parameters. The results have been compared with 16-bit Regular SQRT-CSA BK using BEC and proposed 16-bit CSA using GDI technique. The performance of the designs is compared in terms of area, power and delay. Comparative analysis shows that the proposed CSA using GDI technique has reduced area and consumes less power.

In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage V DD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for cost-effective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption. The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.

Gate-all-around (GAA) is a promising MOSFET structure to continue scaling down the size of CMOS devices beyond 7 nm technology node. This paper gives an overview of different types of GAAFETs including lateral and vertical channel orientations, and nanowire (NW) and nanosheet (NSH) channel structures. The advantages and disadvantages of these structures are discussed. Besides, key parameters such as gate length, transfer characteristics, drain-induced barrier lowering (DIBL), subthreshold slop (SS), and threshold voltage are used to compare the electrical performance of different structures. The review summarizes the advantages of four structures: first, the lateral nanowire tends to have the lowest simulated DIBL (45mV/V) and SS (68mV/dec) due to the circular shape of the channel structure. Second, the lateral nanosheet has a higher driving current or on-state current (Ion = 85μA) than nanowire due to large effective width, Weff. Third, the vertical cylindrical is relaxed on the gate length and contacted gate pitch and has the potential to reduce short channel effects (SCEs) by reducing the diameter of the nanowire. Last, the cylindrical junctionless structure has the lowest Ioff and threshold voltage roll-off which is suitable for low power electronics, and it is easier for fabrication.

In this research work the environmental conditions of Piper Betle cultivation are considered to be studied carefully and improve using advanced electro-agriculture technology. A mixed-signal precision mirror-amplifier, designed in our previous research work for sensing all crucial parameters of natural environment is taken for farther improvement by designing a complete integrated chip for extensive application, which comprises separate controlling segments for different sensing parameters with necessary drivers. This paper represents the designing of the sensor circuit and the complete chip with packaging according to MOSIS’s specifications with the help of MAGIC CAD tool along with MAGIC extraction tool and PSPICE. Also this paper presents the applications in all sizes of betel fields for optimal controlling on environment such as soil moisture and sun shading towards improving the growth i.e. larger betel leaves. Furthermore, additional applications are added in the system those are very crucial to prevent damaging effects from hail and windy weather to save these plants. The entire system is based on off-grid solar power system with 3V and 12V of voltage levels. Results from PSPICE confirmed the proper performance of the chip and proved to be very applicable in this electro-agricultural controlling system. In this paper the methods and results are presented towards the improvement of betel leaf growth.

Soil and land degradation is considered for slope land such as riverbank or streambank and lands of high forced water runoff and rainfall causes severe soil erosion is the concern of this work. The major cause of runaway unprotected soil particles due to the natural reasons, thus making uneven soil plain surface scan be remedied by tree plantation or vegetation. A precision mirror-amplifier is designed for primarily sensing soil moisture and pH level to provide eventual environmental conditions needed for irrigation and fertilization for plants to grow healthy, which in turn reduces the soil erosion. Another special sensor designed and employed here that can monitor the degradation due to erosion and the system can determine the soil’s critical limits. To design the system in an IC form, VLSI design MAGIC CAD tool is used to complete. Results from PSPICE has confirmed the proper performance of the IC and proved to be very applicable in the environment controlling systems. In this paper, design methods and results are presented for a sustainable cultivation technology to prevent soil erosion at slope land.