NBTI

As of date many NBTI models have been published which aim to successfully capture the essential physics. As such, these models have mostly focused on the stress phase. The relaxation phase, on the other hand, has not received as much attention, possibly because of the contradictory results published so far. Particularly noteworthy are the very long relaxation tails of almost logarithmic nature, which cannot be successfully described by the reaction-diffusion model. The authors argue that understanding the nature of the relaxation phase could hold the key to unraveling the underlying NBTI mechanism. In particular, the authors stipulate that the relaxation phase follows a universal relaxation law, demonstrate the valuable consequences resulting therefrom, and use this universality to classify presently available NBTI models.

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

Modern caches are designed to hold 64-bits wide data, however a proportion of data in the caches continues to be narrow width. In this paper, we propose a new cache architecture which increases the effective cache capacity up to 2X for the systems with narrow-width values, while also improving its power efficiency, bandwidth, and reliability. The proposed double capacity cache (DCC) architecture uses a fast and efficient peripheral circuitry to store two narrow-width values in a single wordline. In order to minimize the latency overhead in workloads without narrow-width data, the flag bits are added to tag store. The proposed DCC architecture decreases cache miss-rate by 50%, which results in 27% performance improvement and 30% higher dynamic energy efficiency. To improve reliability, DCC modifies the data distribution on individual bits, which results in 20% and 25% average static-noise margin (SNM) improvement in L1 and L2 caches respectively.

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

The overall performance of a system depends on the performance of the multipliers, thus digital multipliers are among the most critical arithmetic functional units; but their performance is affected by negative bias temperature instability effect and positive bias temperature instability effect. The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs =−Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both these effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore this paper proposes an aging-aware multiplier design with a new adaptive hold logic (AHL) circuit. To mitigate performance degradation due to the aging effect, this architecture can be applied to a column- bypassing multiplier or row-bypassing multiplier.

Keywords- Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.