Neuromorphic VLSi

Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called " XOR (3T) " is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP). .

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-m CMOS process and occupies an area of 2 x 2 mm^2 .

The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity-dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real-world applications. In this paper, we describe analog very large-scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g., based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g., calcium-dependent models). We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature , and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real-world applications.

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix-2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC. KEYWORDS Radix-2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for cost-effective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption. The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

A significant portion of the total power consumption in high performance digital circuits in deep sub-micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high-speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixed-mode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.. KEYWORDS Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very Large Scale Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge full adder.

In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage V DD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.

This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.

In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.

This paper gives the innovative idea of designing a router using multicrossbar switch in Network on Chip(NoC). In Network-on-Chip architectures the input buffer can consume a large portion of the total power. Eliminating all input buffer would result in increased power consumption at high load, while reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar router design using elastic buffer by combining the advantage of both buffered and buffer less network. In the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router.

Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

D stacking is a promising technology (low latency/power/area, high bandwidth); its main shortcoming is increased power density. Simultaneously, motivated by energy constraints, architectures are evolving towards greater customization, with tasks delegated to ac- celerators. Due to the widespread use of machine-learning algo- rithms and the re-emergence of neural networks (NNs) as the pre- ferred such algorithms, NN accelerators are receiving increased at- tention. They turn out to be well matched to 3D stacking: inherently 3D structures with a low power density and high across-layer band- width requirements. We present what is, to the best of our knowl- edge, the first 3D stacked NN accelerator

Fault diagnosis in processing digital system application has raised various limiting problems. While basic objective of fault tolerant systems is to minimize the fault occurring in the device, the processing error is an additional error to be considered. Past approaches were observed to be focusing much on internal fault in digital device, the error due to processing and communication is to be developed. In this paper a self correcting approach to memory design based on memory interface is proposed. The error approach observed in case of forwarding binary data to encode, store and retrieve with error free coding is proposed. The Process of memory error free coding results in higher reliability in case of bit and block coding.

—This work proposes a low power digital block for spatial localization of sensors within the limited area/power budget of sensor nodes. We show a novel digital architecture for a Linear Program (LP) solver based on a recurrent (non-linear feedback) Neural Network (RNN). Training data is not needed in our approach. We solve the primal and dual optimization problems for spatial localization with a single multi-functional data path which does not require matrix inversions. FPGA and ASIC implementations are presented which target a sensor (microrobot) localization problem in 2D using angle-of-arrival (AOA) measurements. The results show that the estimated locations (2D coordinates) are very close to the ground truth values in all tested scenarios. The proposed RNN has input and output layers, and a hidden layer with four neurons. FPGA implementation of the localizer in 180 nm process dissipates 180 mW of power at 1.5V and 31.25 MHz. When scaled to 128 neurons the performance is 13 Mop/sec/W for the same FPGA technology. The design has been also simulated in an ASIC 45 nm (PDK45 1V VDD) standard cell technology. With 128 neurons in the hidden layer the ASIC consumes 196.9 mW power at 516 MHz, which is equivalent to 677.165 Mop/sec/W. The proposed design significantly improves computing efficiency over the recently published results for similar implementations.

The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an optimized and dedicated hardware. The real time implementation places several constraints such as area occupied, power consumption , etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression sequence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

A novel mechanism is proposed for pulse-based logarithmic computation that is scalable across multi-core neuromorphic processors. At the core of the proposed method is an integrate-and-fire margin-propagation (IFMP) unit that facilitates spike-based computation in the logarithmic domain. We first show that a network of three IF neurons implement threshold and rectification operations to compute nonlinear functions. The functions used in the computational algorithms are mapped into log-sum-exp function and
approximated using margin propagation algorithm. Then, we show that a generic pulse neural network is implemented by pipelining and cascading multiple IFMP units. Because all computations are performed in log-domain, multiplication of the pre-synaptic pulse-train by synaptic weights is translated into a simple addition between the two input spike-trains. We demonstrate the scalability of the proposed approach by designing an IFMP-based support vector machine (SVM) for a separable and non separable classification tasks.

Neuromorphic circuits try to replicate aspects of the information processing in neural tissue. Historically, this has often meant some kind of long-term learning function which slowly adjusts the weight of a synapse to achieve a certain target network function. Recently, short-term dynamics at the synapse have also gained significant attention due to their role in dynamic and temporal information processing. However, only very few neuromorphic circuits have incorporated short term dynamics, with still fewer of these implementations being biologically realistic. We derive a circuit for biologically relevant short term dynamics, showing its accuracy with respect to biological measurements. Since this circuit significantly increases the overall complexity of the synapse, a direct integration in the synapse would be prohibitive. Thus, in addition to the short term dynamics, we also present a novel configurable topology for the neurons and synapses on chip which achieves a compact and flexible overall design while still augmenting all synapses with the new short term dynamics.

The computational function of neural networks is thought to depend primarily on the learning/plasticity function carried out at the synapse. Neuromorphic circuit realizations have taken this into account by implementing a variety of synaptical processing functions, with most recent synapse circuits replicating some form of Spike Time Dependent Plasticity (STDP). However, STDP is being challenged by older rate-dependent learning rules as well as by biological experiments exhibiting more complex timing rules (e.g. spike triplets) as well as simultaneous rate- and timing dependent plasticity. In this paper, we present a circuit realization of a plasticity rule based on the postsynaptic neuron potential as well as the transmission profile of the presynaptic spike. To the best of our knowledge, this is the first circuit realization of synaptical behaviour which moves significantly beyond STDP, replicating the triplet experiments of Froemke and Dan, the combined timing and rate experiments of Sjoestroem et al., as well as conventional BCM behaviour.

Selective attention is a biological mechanism to process salient subregions of the sensory input space, while suppressing non-salient inputs. We present a hardware selective attention system, implemented using a neuromorphic VLSI chip interfaced to a workstation, via a custom PCI board and based on an address event (spike based) representation of signals. The chip selects salient inputs and sequentially shifts from one salient input to the other. The PCI board acts as an interface between the chip and an algorithm that generates saliency maps. We present experimental data showing the system's response to saliency maps generated from natural scenes.

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.