80386

OVERVIEW:
Intel 386

Intel 80386 DX rated at 16 MHz
Produced From 1985 to September 2007
Common
manufacturer(s)
Intel
AMD
IBM
Max. CPU clock rate 12 MHz to 40 MHz
Min. feature size 1.5m to 1m
Instruction set x86 (IA-32)
Predecessor Intel 80286
Successor Intel 80486
Transistors 275,000
Price $299
Pins 132
Package(s)
132-pin PGA, 132-pin
PQFP; SX variant: 88-
pin PGA, 100-pin
PQFP

HISTORY:
The 80386 ("eighty-three-eighty-six"), family of
microprocessors of Intel Corporation is the first 32 bit
version of the 8086 family-a switch from 16 bit to 32 bit
having 5 MIPS.
Chief architect in the development of the 80386 was John
H. Crawford
80386 has upward compatibility with 8086,8088,80286 etc
The 80386 was launched in October 1985, but full-function
chips were first delivered in the third quarter of 1986
Although it had long been obsolete as a personal
computer CPU, Intel and others had continued making the
chip for embedded systems.
A 33 MHz 80386 was reportedly measured to operate at
about 11.4 MIPS.
The first personal computer to make use of the 80386 was
designed and manufactured by Compaq.
May 2006, Intel announced that 80386 production would
stop at the end of September 2007
In 1988, Intel introduced the i386SX.
Used in aerospace technology, some mobile phones also
used the 80386 processor, such as BlackBerry 950
[8]
and
Nokia 9000 Communicator.
AMD introduced its compatible Am386 processor in March
1991.
The AMD Am386SX and Am386DX were almost exact
clones of the 80386SX and 80386DX having 40MHz.
Chips and Technologies Super386 38600SX and 38600DX
were developed using reverse engineering. They sold
poorly, due to some technical errors and incompatibilities,
Cyrix Cx486SLC/Cx486DLC could be (simplistically)
described as a kind of 386/486 hybrid chip that included a
small amount of on-chip cache.
IBM 386SLC and 486SLC/DLC were variants of Intel's
design which contained a large amount of on-chip cache (8
kB, and later 16 kB).
VERSIONS OF 80386:
80386DX the full version
The first member in 80386 family
this CPU could work with 16-bit and 32-bit external buses.
Comprises of both 32-bit internal registers and 32-bit
external bus.
80386SX the reduced bus version
low cost version of the 80386.
This processor had 16 bit external data bus,32-bit internal
registers and 24-bit external address bus.
80386SL
low-power microprocessor with power management
features, with 16-bit external data bus and 24-bit external
address bus.
The processor included ISA bus controller, memory
controller and cache controller.
Embedded 80376 and 80386EX processors.- Still in use today.

ARCHITECTURE:
To enhance performance 80386 has 6 functional units,
processing in parallel:
The bus unit:
is the interface to the external devices.
The prefetch unit:
unit performs a mechanism known as
an instruction stream queue.
The decode unit:
accesses the output end of the prefetch
units instruction queue.
The execution unit:
involves the arithmetic/logic unit-ALU,
registers, special multiply, divide, and
shift hardware, and a control ROM.
The page unit &
The segment unit:
provide the memory management and
protection services for the 80386.
OPERATING MODES:
*real mode, protected mode and virtual mode.

80486
Intel 486

The exposed die of an Intel 80486DX2 microprocessor
Produced From 1989 to 2007
Common
manufacturer(s)
Intel, IBM, AMD, Texas
Instruments, Harris
Semiconductor, UMC, SGS
Thomson
Max. CPU clock rate 16 MHz to 100 MHz
FSB speeds 16 MHz to 50 MHz
Min. feature size 1m to 0.6m
Instruction set x86 including x87 (except for "SX" models)
Predecessor Intel 80386
Successor Pentium (P5)
Package(s)
PGA (socket 1, 2, 3), 196-pin PQFP,
208-pin SQFP

Only few differences between the 80486 and 80386, but
these differences created a significant performance
improvement.
32 bit microprocessor and same register set as 80386.
Few additional instructions were added to its instruction
set.
4 gigabyte addressing space .
HISTORY:
The first tightly pipelined x86 design as well as the first x86
chip to use more than a million transistors.
A 50 MHz executed around 40 MIPS on average and was
able to reach 50 MIPS peak performance.
80486 was announced at Spring Comdex in April 1989,
Intel stated that samples would be available in the third
quarter of 1989 and production quantities would ship in
the fourth quarter of 1989.

IMPROVEMENTS MADE IN 80486 OVER 80386:
80486 was powered with a 8KB cache memory.
This improved the speed of 80486 processor to great
extent.
Some new 80486 instructions are included to maintain the
cache.
It uses four way set associative cache.
80486 also uses a co-processor similar to 80387 used with
80386.
But this co-processor is integrated on the chip allows it to
execute instructions 3 times faster as 386/387
combination.
The new design of 80486 allows the instruction to execute
with fewer clock cycles.
486 is packed with 168 pin grid array package instead of
the 132 pin used for 386 processor.
This additional pins made room for the additional signals.
This new design of 80486 allows the instruction to execute
with fewer clock cycles.
These small differences made 80486 more powerful
processor.
VERSIONS:
AMD produced several clones of the 486 using a 40 MHz
bus (486DX-40, 486DX/2-80, and 486DX/4-120) which had
no equivalent available from Intel, as well as a part
specified for 90 MHz, using a 30 MHz external clock, that
was sold only to OEMs.
The fastest running 486 CPU, the Am5x86, ran at 133 MHz
and was released by AMD in 1995. 150 MHz and 160 MHz
parts were planned but never officially released.
Cyrix's early offerings included the 486DLC and 486SLC.,
two hybrid chips which plugged into 386DX or SX sockets
respectively, and offered 1 KB of cache (versus 8 KB for the
then-current Intel/AMD parts).
The Motorola 68040 (best known for its use in the
Macintosh Quadra series), while not compatible with the
486, was often positioned as the 486's equivalent in
features and performance.
One of the earliest complete systems to use the 80486
chip was the Apricot VX FT, produced by United Kingdom
hardware manufacturer Apricot Computers.













Model
Specified max
clock
Voltage
L1-
Cache
Introduced Notes


i486DX (P4)
20, 25 MHz
33 MHz
50 MHz
5V
8 KB
WT
April 1989
May 1990
June 1991
The original chip (without any clock doubling)

i486SL 20, 25, 33 MHz
5V or
3.3V
8 KB
WT
November
1992
Low power version of the i486DX, reduced VCore,
SMM (System Management Mode), stop clock, and
power saving features mainly for use in portable
computers

i486SX (P23)
16, 20, 25 MHz
33 MHz
5V
8 KB
WT
September
1991
September
1992
An i486DX with the FPU part disabled or missing.
Early variants were parts with disabled (defective)
FPUs.
[5]
Later versions had the FPU removed from the
die to reduce area and hence cost.

i486DX2
(P24)
40/20,
50/25 MHz
66/33 MHz
5V
8 KB
WT
March 1992
August 1992
The internal processor clock runs at twice the clock
rate of the external bus clock

i486DX-S
(P4S)
33 MHz;
50 MHz
5V or
3.3V
8 KB
WT
June 1993 SL Enhanced 486DX

i486DX2-S
(P24S)
40/20,
50/25 MHz
(66/33 MHz)
5V or
3.3V
8 KB
WT
June 1993


i486SX-S
(P23S)
25, 33 MHz
5V or
3.3V
8 KB
WT
June 1993 SL Enhanced 486SX

i486SX2
50/25,
66/33 MHz
5V
8 KB
WT
March 1994 i486DX2 with the FPU disabled

IntelDX4
(P24C)
75/25,
100/33 MHz
3.3V
16 KB
WT
March 1994
Designed to run at triple clock rate (not quadruple as
often believed; the DX3, which was meant to run at
2.5x the clock speed, was never released). DX4
models that featured write-back cache were
identified by an "&EW" laser etched into their top
surface, while the write-through models were
identified by "&E".

IntelDX4WB 100/33 MHz 3.3V
16 KB
WB
October 1994


i486DX2WB
(P24D)
50/25,
66/33 MHz
5V
8 KB
WB
October 1994


i486DX2
(P24LM)
90/30 MHz;
100/33 MHz
2.5
2.9V
8 KB
WT
1994


i486GX up to 33 MHz 3.3V
8 KB
WT
Embedded Ultra-Low power CPU with all features of
the i486SX and 16 Bit external data bus. This CPU is
for embedded battery-operated and hand-held
applications.


PENTIUM
OVERVIEW:
Pentium

2009present logo
Produced From March 22, 1993 to present
Common manufacturer(s)
Intel
Max. CPU clock rate 60 MHz to 3.8 GHz
FSB speeds 60 MHz to 1333 MT/s
Min. feature size 0.8 m to 22 nm
Instruction set x86, x86-64
Microarchitecture P5
Cores 12
Predecessor Intel 80486
Socket(s)
Socket 4.5.7
L1 Cache 16-32KiB

HISTORY:
Intel wanted to prevent their competitors from
branding their processors with similar names, as AMD
had done with their Am486.
The name Pentium is originally derived from
the Greek word pente meaning 'five' as the series was
Intel's 5th generation microarchitecture suffix -ium
was chosen as it could connote a fundamental
ingredient of a computer, like a chemical element.
Intel rates as "two stars" meaning that it is above the
low-end Atom and Celeron products but below the
faster Core i3, i5 and i7 lines as well as the high-end
Xeon processors.
are typically used with a lower clock frequency, a
partially disabled L3 cache and some of the advanced
features such as hyper-threading and virtualization
disabled.
Marketing firm Lexicon Branding was hired to coin a
name for the new processor.
P5 Pentium competitors included the Motorola 68060
and the PowerPC 601 as well as the SPARC, MIPS, and
Alpha microprocessor families, most of which also
used a superscalar in-order dual instruction pipeline
configuration at some time
Designed by the same Santa Clara team which
designed the 386 and 486. Design work started in
1989; the team decided to use a superscalar
architecture, with on-chip cache, floating-point, and
branch prediction.
John H. Crawford, chief architect of the original 386,
co-managed the design of the P5, along with Donald
Alpert, who managed the architectural team. Dror
Avnon managed the design of the FPU. Vinod K.
Dham was general manager of the P5 group.

List of Intel Pentium Microprocessors:
Core Process Frequency L1
Cache
FSB Socket Release
date
P5 0.8 m 6066 MHz 16 KB 60
66 MHz
Socket
4
March
1993
P54C 0.6 m 75
120 MHz
16 KB 50
66 MHz
Socket
5
October
1994
P54CS 0.35 m 133
200 MHz
16 KB 60
66 MHz
Socket
7
June
1995
P55C 0.35 m 120
233 MHz
32 KB 60
66 MHz
Socket
7
January
1997
[12]

Tillamook 0.25 m 166
300 MHz
32 KB 66 MHz Socket
7
August
1997
Major improvements over i486 microarchitecture[edit]
Performance:
o Superscalar architecture The Pentium has two
datapaths (pipelines) that allow it to complete
two instructions per clock cycle in many cases.
The main pipe (U) can handle any instruction,
while the other (V) can handle the most common
simple instructions.
o 64-bit external databus doubles the amount of
information possible to read or write on each
memory access and therefore allows the
Pentium to load its code cache faster than the
80486; it also allows faster access and storage of
64-bit and 80-bit x87 FPU data.
o Separation of code and data caches lessens the
fetch and operand read/write conflicts
compared to the 486.
o Much faster floating point unit.
o Four-input address-adders enables the Pentium
to further reduce the address calculation latency
compared to the 80486.
o The microcode can employ both pipelines to
enable auto-repeating instructions
o A faster, fully hardware-based multiplier makes
instructions such as MUL and IMUL several times
as fast (and more predictable) than in the 80486;
the execution time is reduced from 13~42 clock
cycles down to 10~11 for 32-bit operands.
o Virtualized interrupt to speed up virtual 8086
mode.
Other features:
o Enhanced debug features with the introduction
of the Processor-based debug port.
o Enhanced self test features like the L1 cache
parity check.