L4972A

L4972AD

2A SWITCHING REGULATOR

..
..
..
..
.
.
..
..

2A OUTPUT CURRENT
5.1V TO 40V OUTPUT VOLTAGE RANGE
0 TO 90% DUTY CYCLE RANGE
INTERNAL FEED-FORWARD LINE REG.
INTERNAL CURRENT LIMITING
PRECISE 5.1V 2% ON CHIP REFERENCE
RESET AND POWER FAIL FUNCTIONS
INPUT/OUTPUT SYNC PIN
UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON
PWM LATCH FOR SINGLE PULSE PER PERIOD
VERY HIGH EFFICIENCY
SWITCHING FREQUENCY UP TO 200KHz
THERMAL SHUTDOWN
CONTINUOUS MODE OPERATION

DESCRIPTION
The L4972Aisa stepdownmonolithicpower switching regulatordelivering 2A at a voltagevariable from
5.1 to 40V.
Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
efficiency and very fast switching times. Features of

MULTIPOWER BCD TECHNOLOGY

POW ERDIP
(16 + 2 + 2)

SO20

ORDERING NUMBERS : L4972A (Powerdip)

L4972AD (SO20)

the L4972A include reset and power fail for microprocessors, feed forward line regulation, soft start,
limiting current and thermal protection. The device
is mountedin a Powerdip16 + 2 + 2 and SO20large
plastic packages and requires few external components. Efficient operation at switching frequencies
up to 200KHz allows reduction in the size and cost
of external filter component.

BLOCK DIAGRAM

June 2000

1/23

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

L4972A-L4972AD
ABSOLUTE MAXIMUM RATINGS
Symbo l

Parameter

Valu e

Unit
V

V11

Input Voltage

55

V11

Input Operating Voltage

50

V20

Output DC Voltage
Output Peak Voltage at t = 0.1s f = 200khz

-1
-5

V
V

I20

Maximum Output Current

VI

Boostrap Voltage
Boostrap Operating Voltage

V4 , V 8

Internally Limited
65
V11 + 15

V
V

Input Voltage at Pins 4, 12

12

V3

Reset Output Voltage

50

I3

Reset Output Sink Current

50

mA

Input Voltage at Pin 2, 7, 9, 10

I2

Reset Delay Sink Current

30

mA

I7

Error Amplifier Output Sink Current

I8

Soft Start Sink Current

V2, V 7, V 9, V10

Ptot
TJ, Tstg

30

mA

Total Power Dissipation at TPINS 90C

at T amb = 70C (No copper area on PCB)

5 / 3.75(*)
1.3/1 (*)

W
W

Junction and Storage Temperature

-40 to 150

(*) SO-20

PIN CONNECTION (top view)

THERMAL DATA
Symb ol
Rth j-pins
Rth j-amb

2/23

Parameter
Thermal Resistance Junction-Pins
Thermal Resistance Junction-ambient

max
max

Po werdip

SO- 20

12C/W
60C/W

16C/W
80C/W

L4972A-L4972AD
PIN FUNCTIONS
No

Name

F unctio n

BOOTSTRAP

A Cboot capacitor connected between this terminal and the output allows to drive
properly the internal D-MOS transistor.

RESET DELAY

A Cd capacitor connected between this terminal and ground determines the reset
signal delay time.

RESET OUT

Open Collector Reset/power Fail Signal Output. This output is high when the supply
and the output voltages are safe.

RESET INPUT

Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider
to the input for power fail function. It mustbe connected to the pin 14 an external 30K
resistor when power fail signal not required.

GROUND

Common Ground Terminal

FREQUENCY
COMPENSATION

A series RC network connected between this terminal and ground determines the
regulation loop gain characteristics.

SOFT START

Soft Start Time Constant. A capacitor is connected between thi sterminal and ground
to define the soft start time constant.

FEEDBACK INPUT

The Feedback Terminal of the Regulation Loop. The output is connected directly to
this terminal for 5.1V operation; It is connected via a divider for higher voltages.

10

SYNC INPUT

Multiple L4972As are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

11

5, 6
15, 16

SUPPLY VOLTAGE

Unregulated Input Voltage.

12, 19

N.C.

Not Connected.

13

Vref

5.1V Vref Device Reference Voltage.

14

Vstart

Internal Start-up Circuit to Drive the Power Stage.

17

OSCILLATOR

Rosc. External resistor connected to ground determines the constant charging current
of C osc.

18

OSCILLATOR

Cosc. External capacitor connected to ground determines (with Rosc) the switching
frequency.

20

OUTPUT

Regulator Output.

3/23

L4972A-L4972AD
CIRCUIT OPERATION
The L4972A is a 2A monolithic stepdown switching
regulatorworking in continuousmode realized inthe
new BCD Technology. This technology allows the
integration of isolatedvertical DMOS power transistors plus mixed CMOS/Bipolar transistors.
The device can deliver 2A at an output voltage adjustable from 5.1V to 40V and contains diagnostic
and control functions that make it particularly suitable for microprocessor based systems.
BLOCK DIAGRAM
The block diagram shows the DMOS power transistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V
2%,soft start, undervoltagelockout, oscillator with
feedforward control, pulse by pulse current limit,
thermal shutdown and finally the reset and power
fail circuit. The reset and power fail circuit provides
an output signal for a microprocessor indicating the
status of the system.
Device turn on is around 11V with a typical 1V hysterysis, this threshold porvides a correct voltage for
the driving stage of the DMOS gate and the hysterysis prevents instabilities.
An externalbootstrapcapacitorchargeto 12V by an
internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of
around 0.5A to the gate of the DMOS transistor. A
typical switching time of the current in the DMOS
transistor is 50ns. Due to the fast commutation
switching frequencies up to 200kHz are possible.
The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is producedby comparing
theoutputvoltagewiththeprecise5.1V 2% onchip
reference. This error signal is then compared with
the sawtooth oscillator in order to generate frixed
frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate
multiple pulsing within a period even in noisy environments.
The gain and stabilityof the loop can be adjustedby

4/23

an external RC network connected to the output of

the error amplifier. A voltage feedforward control
has been added to the oscillator, this maintains superior line regulation over a wide input voltage
range. Closing the loop directly gives an outputvoltage of 5.1V, higher voltages areobtained by inserting a voltage divider.
At turn on, outputovercurrents are preventedby the
soft start function (fig. 2). The error amplifier is initially clamped by an externalcapacitor,Css, and allowed to rise linearly under the charge of an internal
constant current source.
Output overload protection is provided by a current
limit circuit. The load current is sensedby a internal
metalresistor connectedto a comparator.When the
load current exceeds a preset threshold, the output
of the comparator sets a flip flop which turns off the
power DMOS. The next clock pulse, from an internal
40kHz oscillator, will reset the flip flopand the power
DMOS will again conduct. This current protection
method,ensuresa constantcurrent outputwhenthe
systemis overloadedor shortcircuited and limitsthe
switching frequency, in this condition,to 40kHz. The
Reset and Power fail circuit (fig. 4), generates an
output signal when the supply voltage exceeds a
threshold programmed by an external voltage divider. The reset signal, is generated with a delay
time programmedby a externalcapacitor on the delay pin. When the supply voltage falls below the
threshold or the output voltage goes below 5V, the
resetoutput goes low immediately. The reset output
is an open drain.
Fig. 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage is
not yet 5V.
Fig. 4B shows the case when the output is 5.1V, but
the supply voltage is not yet higher than the fixed
threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150C and has a hysterysis to prevent unstable
conditions.

L4972A-L4972AD
Figure 1 : Feedforward Waveform.

Figure 2 : Soft Start Function.

Figure 3 : Limiting Current Function.

5/23

L4972A-L4972AD
Figure 4 : Reset and Power Fail Functions.
A

6/23

L4972A-L4972AD
ELECTRICAL CHARACTERISTICS (refer to the test circuit, TJ = 25C, V i = 35V, R4 = 30K,
C9 = 2.7nF, fSW = 100KHztyp, unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbo l

Parameter

Vi

Input Volt. Range (pin 11)

Vo = Vref to 40V
Io = 2A (**)

15

Vo

Output Voltage

Vi =15V to 50V
Io = 1A; Vo = Vref

Vo

Line Regulation

Vi = 15V to 50V
Io = 0.5A; Vo = Vref

Vo

Load Regulation

Vo = Vref Io = 0.5A to 2A

Vd

Dropout Voltage between

Pin 11 and 20

Io = 2A

I20L

Max Limiting Current

Vi = 15V to 50V
Vo = Vref to 40V

Efficiency (*)

Io = 2A, f = 100KHz
Vo = Vref
Vo = 12V

SVR

T est Co nd itions

Vi = 2VRMS; Io = 1A
f = 100Hz; Vo = Vref

Supply Voltage Ripple

Rejection

Switching Frequency

f/Vi

Voltage
Stability
Switching
Frequency
Temperature Stability of
Switching Frequency

Tj = 0 to 125C

fmax

Maximum Operating
Switching Frequency

Vo = Vref R4 = 15K
Io = 2A C9 = 2.2nF

T yp.

Max.

Unit

Fig .

50

5.1

5.2

12

30

mV

20

mV

0.25

0.4

2.5

2.8

3.5

75

85
90

%
%

56

60

dB

90

100

110

KHz

KHz

Fig .

of Vi = 15V to 45V

f/Tj

(*) Only for DIP version

Min.

1
200

(**) Pulse testing with a low duty cycle

Vref SECTION (pin 13)

Symbo l
V13

Parameter

T est Cond ition

Reference Voltage

Min.

T yp.

Max.

Unit

5.1

5.2

V13

Line Regulation

Vi = 15V to 50V

10

25

mV

V13

Load Regulation

I13 = 0 to 1mA

20

40

mV

Tj = 0C to 125C

0.4

mV/C

V13 = 0

70

mA

V13
T
I13 short

Average Temperature
Coefficient Reference
Voltage
Short Circuit Current Limit

VSTART SECTION (pin 15)

Symbo l

Parameter

T est Cond ition

Max.

Unit

Fig .

12

12.6

Line Regulation

Vi = 15 to 50V

0.6

1.4

V14

Load Regulation

I14 = 0 to 1mA

50

200

mV

Short Circuit Current Limit

V15 = 0V

80

mA

I14 short

11.4

T yp.

V14

V14

Reference Voltage

Min.

7/23

L4972A-L4972AD
ELECTRICAL CHARACTERISTICS (continued)
DC CHARACTERISTICS
Symbo l

Parameter

V11on

Turn-on Threshold

V11 Hyst

Turn-off Hysteresys

T est Cond ition

Min.

Typ.

Max.

Unit

10

11

12

7A

7A

F ig.

I11Q

Quiescent Current

V8 = 0; S1 = D

13

19

mA

7A

I11OQ

Operating Supply Current

V8 = 0; S1 = B; S2 = B

16

23

mA

7A

Out Leak Current

Vi = 55V; S3 = A; V8 = 0

mA

7A

I20L

SOFT START (pin 8)

Symbo l

Parameter

I8

Soft Start Source Current

V8 = 3V; V9 = 0V

T est Cond ition

V8

Output Saturation Voltage

I8 = 20mA; V11 = 10V

I8 = 200A; V11 = 10V

Min.

Typ.

Max.

Unit

F ig.

80

115

150

7B

1
0.7

V
V

7B
7B

Max.

Unit

F ig.

7C

7C
7C

ERROR AMPLIFIER
Symbo l

Parameter

T est Cond ition

Min.

Typ.

V7H

High Level Out Voltage

I7 = 100A; S1 = C
V9 = 4.7V

V7L

Low Level Out Voltage

I7 = 100A; S1 = C
V9 = 5.3V;

I7H

Source Output Current

V7 = 1V; V 7 = 4.7V

100

150

-I7L

Sink Output Current

V7 = 6V; V 9 = 5.3V

100

150

7C

I9

Input Bias Current

S1 = B; RS = 10K

GV

DC Open Loop Gain

S1 = A; RS = 10

60

A
dB

7C

SVR

Supply Voltage Rejection

15 < Vi < 50V

60

dB

7C

V OS

Input Offset Voltage

R S = 50 S1 = A

6
1.2

0.4

80

7C

10

mV

7C

Typ.

Max.

Unit

F ig.

RAMP GENERATOR (pin 18)

Symbo l

Parameter

T est Cond ition

V18

Ramp Valley

S1 = B; S2 = B

V18

Ramp Peak

S1 = B
S2 = B

I18

Min. Ramp Current

S1 = A; I17 = 100A

I18

Max. Ramp Current

S1 = A; I17 = 1mA

Min.
1.2

V i = 15V
Vi = 45V

1.5

7A

2.5
5.5

V
V

7A
7A

270
2.4

2.7

Min.

Typ.

300

7A

mA

7A

SYNC FUNCTION (pin 10)

Symbo l

8/23

Max.

Unit

F ig.

V10

Low Input Voltage

Parameter

Vi = 15V to 50V; V 8 = 0;
S1 = B; S2 = B; S4 = B

T est Cond ition

0.3

0.9

7A

V10

High Input voltage

V8 = 0;
S1 = B; S2 = B; S4 = B

2.5

5.5

7A

I10L

Sync Input Current with Low V10 = V18 = 0.9V; S4 = B;

Input Voltage
S1 = B; S2 = B

0.4

mA

7A

I10H

Input Current with High V10 = 2.5V

Input Voltage

1.5

mA

7A

V10

Output Amplitude

tW

Output Pulse Width

Vthr = 2.5V

0.3

0.5

0.8

L4972A-L4972AD
ELECTRICAL CHARACTERISTICS (continued)
RESET AND POWER FAIL FUNCTIONS
Symbo l

Parameter

T est Co nd itions

Min.

T yp.

Max.

Unit

Fig .

V9R

Rising Thereshold Voltage

(pin 9)

Vi = 15 to 50V
V4 = 5.3V

Vref
-130

Vref
-100

Vref
-80

V
mV

7D

V9F

Falling Thereshold Voltage

(pin 9)

Vi = 15 to 50V
V4 = 5.3V

4.77

Vref
-200

Vref
-160

V
mV

7D

V2H

Delay High Threshold Volt.

Vi = 15 to 50V
V4 = 5.3V V9 = V13

4.95

5.1

5.25

7D

V2L

Delay Low Threshold Volt.

Vi = 15 to 50V
V4 = 4.7V V9 = V13

1.1

1.2

7D

I2SO

Delay Source Current

V4 = 5.3V;

30

60

80

I2SI

Delay Source Sink Current

V4 = 4.7V; V2 = 3V

V 3S

Output Saturation Voltage

I3 = 15mA; S1 = B V4 = 4.7V

0.4

7D

Output Leak Current

V3 = 50V; S1 = A

100

V4R

Rising Threshold Voltage

V9 = V13

V4H

Hysteresis

I3

I4

V2 = 3V

Input Bias Current

10

7D

mA

7D

7D

4.95

5.1

5.25

7D

0.4

0.5

0.6

7D

7D

TYPICAL PERFORMANCES (using evaluation board) :

n = 83% (Vi = 35V ; Vo = VREF ; Io = 2A ; fsw = 100KHz)
Vo RIPPLE = 30mV (at 1A)
Line regulation = 12mV (Vi = 15 to 50V)
Load regulation = 7mV (Io = 0.5 to 2A)
for component values Refer to the fig. 5 (Part list).

9/23

L4972A-L4972AD
Figure 6a : Component Layout of fig.5 (1 : 1 scale). Evaluation Board Available (only for DIP version)

PART LIST
R 1 = 30K
R 2 = 10K
R 3 = 15K
R 4 = 30K
R 5 = 22
R 6 = 4.7K
R 7 = see table A
R 8 = OPTION
R 9 = 4.7K
* C1 = C2 = 1000F 63V EYF (ROE)
C3 = C4 = C5 = C6 = 2,2F 50V
C7 = 390pF Film
C8 = 22nF MKT 1837 (ERO)
C9 = 2.7nF KP 1830 (ERO)
C10 = 0.33F Film
C11 = 1nF
** C12 = C 13 = C14 = 100F 40V EKR (ROE)
C15 = 1F Film
D1 = SB 560 (OR EQUIVALENT)
L1 = 150H
core 58310 MAGNETICS
45 TURNS 0.91mm (AWG 19)
COGEMA 949181
* 2 capacitors in parallel to increase input RMS current capability.
* * 3 capacitors in parallel to reduce total output ESR.

10/23

Table A
V0

R9

R7

12V
15V
18V
24V

4.7k
4.7k
4.7k
4.7k

6.2kW
9.1k
12
18

Note:
In the Test and Application Circuit for L4972D are not
mounted C2, C14 and R8.

Table B
SUGGESTED BOOSTRAP CAPACITORS
Operatin g F requency

Boo strap Cap.c10

f = 20KHz

680nF

f = 50KHz

470nF

f = 100KHz

330nF

f = 200KHz

220nF

f = 500KHz

100nF

L4972A-L4972AD
Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)

Figure 7 : DC Test Circuits.

11/23

L4972A-L4972AD
Figure 7A.

Figure 7B.

Figure 7C.

12/23

L4972A-L4972AD
Figure 7D.

Figure 8 : Quiescent Drain Current vs. Supply

Voltage (0% duty cycle - see fig. 7A).

Figure 9 : QuiescentDrain Current vs. Junction

Temperature (0% duty cycle).

13/23

L4972A-L4972AD
Figure 10 : Quiescent Drain Current vs. Duty Cycle.

Figure 11 : Reference Voltage (pin 13) vs. Vi

(see fig. 7).

Figure 12 : Reference Voltage (pin 13) vs. Junction Temperature (see fig. 7).

Figure 13 : ReferenceVoltage (pin 14) vs. Vi

(see fig. 7).

Figure 14 : Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7).

Figure 15 : Reference Voltage 5.1V (pin 13) Supply Voltage Ripple Rejection vs. FreSVR
(dB)

14/23

L4972A-L4972AD
Figure 16 : Switching Frequency vs. Input Voltage
(see fig. 5).

Figure 17 : Switching Frequency vs. Junction

Temperature (see fig. 5).

Figure 18 : Switching Frequency vs. R4

(see fig.5).

Figure 19 : Maximum Duty Cycle vs. Frequency.

Figure 20 : Supply Voltage Ripple Rejection vs.

Frequency (see fig. 5).

Figure 21 : Efficiency vs. Output Voltage.

15/23

L4972A-L4972AD
Figure 22 : Line Transient Response (see fig. 5).

Figure 23 : Load Transient Response (see fig. 5).

Figure 24 : Dropout Voltage between Pin 11 and

Pin 20 vs. Current at Pin 20.

Figure 25 : .Dropout Voltage between Pin 11 and

Pin 20 vs. Junction Temperature.

Figure 26 : Power Dissipation (device only) vs.

Input Voltage.

Figure 27 : Power Dissipation (device only) vs.

Input Voltage.

16/23

L4972A-L4972AD
Figure 28 : Power Dissipation (device only) vs.
Output Voltage.

Figure 29 : Power Dissipation (device only) vs.

OutputVoltage.

Figure 30 : Power Dissipation (device only) vs.

Output Current.

Figure 31 : Power Dissipation (device only) vs.

Output Current.

Figure 32 : Efficiency vs. Output Current.

Figure 33 : Test PCB Thermal Characteristic.

17/23

L4972A-L4972AD
Figure 34 : Junctionto AmbientThermal Resistance
vs. Area onBoard Heatsink (DIP 16+2+2)

Figure 35: Junction to Ambient Thermal Resistance

vs. Area on Board Heatsink (SO20)

Figure 36: Maximum Allowable Power Dissipation vs. Ambient Temperature (Powerdip)

Figure 37: Maximum Allowable Power Dissipation vs. Ambient Temperature

(SO20)

Figure 38: Open Loop Frequency and Phase of Error Amplifier (see fig. 7C).

18/23

L4972A-L4972AD
Figure 39 : 2A 5.1V Low Cost Application Circuit.

Figure 40 : A 5.1V/12VMultiple Supply. Note the Synchronization between the L4972A and L4970A.

19/23

L4972A-L4972AD
Figure 41 : L4972As Sync. Example.

Figure 42: 1A/24V Multiple Supply. Note the synchronization between the L4972A and L4962

20/23

L4972A-L4972AD

mm

DIM.
MIN.
a1

0.51

0.85

b
b1

TYP.

inch
MAX.

MIN.

TYP.

MAX.

0.020
1.40

0.033

0.50
0.38

0.055
0.020

0.50

0.015

0.020

24.80

0.976

8.80

0.346

2.54

0.100

e3

22.86

0.900

7.10

0.280

5.10

0.201

L
Z

OUTLINE AND
MECHANICAL DATA

3.30

0.130
1.27

Powerdip 20
0.050

21/23

L4972A-L4972AD

mm

DIM.
MIN.

TYP.

inch
MAX.

MIN.

TYP.

MAX.

2.35

2.65

0.093

0.104

A1

0.1

0.3

0.004

0.012

0.33

0.51

0.013

0.020

0.23

0.32

0.009

0.013

12.6

13

0.496

0.512

7.4

7.6

0.291

0.299

1.27

OUTLINE AND
MECHANICAL DATA

0.050

10

10.65

0.394

0.419

0.25

0.75

0.010

0.030

0.4

1.27

0.016

0.050

SO20
K

0 (min.)8 (max.)

h x 45

A
B

A1

K
H

20

11
E

1
0
SO20MEC

22/23

L4972A-L4972AD

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