VIPer50/SP

 VIPer50A/ASP

SMPS PRIMARY I.C.

T YPE V DSS In R DS(on)
VIPer50/SP 620V 1.5 A 5Ω
VIPer50A/ASP 700V 1.5 A 5.7 Ω
10

1
PENTAWATT HV PENTAWATT HV
FEATURE (022Y)
PowerSO-10
■ ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
■ CURRENT MODE CONTROL DESCRIPTION
■ SOFT START AND SHUT DOWN CONTROL VIPer50/50A make using VIPower M0
■ AUTOMATIC BURST MODE OPERATION IN Technology combines on the same silicon chip a
STAND-BY CONDITION ABLE TO MEET state-of-the-art PWM circuit together with an
”BLUE ANGEL” NORM (<1W TOTAL POWER optimized high voltage avalanche rugged Vertical
CONSUMPTION) Power MOSFET (620V or 700V / 1.5A).
■ INTERNALLY TRIMMED ZENER Typical applications cover off line power supplies
REFERENCE with a secondary power capability of 25W in wide
■ UNDERVOLTAGE LOCK-OUT WITH range condition and 50W in single range or with
HYSTERESIS doubler configuration. It is compatible from both
■ INTEGRATED START-UP SUPPLY primary or secondary regulation loop despite
■ AVALANCHE RUGGED using around 50% less components when
■ OVERTEMPERATURE PROTECTION compared with a discrete solution. Burst mode
■ LOW STAND-BY CURRENT operation is an additional feature of this device,
■ ADJUSTABLE CURRENT LIMITATION offering the possibility to operate in stand-by
mode without extra components.
BLOCK DIAGRAM

OSC DRAIN

ON/OFF
OSCILLATOR

SECURITY PWM
LATCH LATCH

UVLO FF S
VDD
LOGIC R/S Q R1 FF Q
S R2 R3

OVERTEMP.
DETECTOR

0.5V
_
0.5 V + 1.7 µ s + + 2 V/A
250 ns
_ DELAY BLANKING _
CURRENT
ERROR AMPLIFIER
_ AMPLIFIER

13 V +
4.5 V
FC00291

COMP SOURCE

May 1999 1/20

VIPer50/SP - VIPer50A/ASP

ABSOLUTE MAXIMUM RATING

Symb ol Parameter Value Unit
V DS Continuous Drain-Source Voltage (Tj = 25 to 125o C)
for VIPer50/SP -0.3 to 620 V
for VIPer50A/ASP -0.3 to 700 V
ID Maximum Current Internally Limited A
VDD Supply Voltage 0 to 15 V
V OSC Voltage Range Input 0 to V DD V
V COMP Voltage Range Input 0 to 5 V
I COMP Maximum Continuous Current ±2 mA
V esd Electrostatic discharge (R = 1.5 KΩ C = 100pF) 4000 V
I D(AR) Avalanche Drain-Source Current, Repetitive or Not-Repetitive
(T C = 100 oC, Pulse Width Limited by T J max, δ <1%)
for VIPer50/SP 1.5 A
for VIPer50A/ASP 1 A
o
P tot Power Dissipation at T c = 25 C 60 W
o
Tj Junction Operating Temperature Internally Limited C
o
T s tg Storage Temperature -65 to 150 C

THERMAL DATA
PENT AW ATT-HV Po werSO-10(*)
o
R t hj-ca se Thermal Resistance Junction-case Max 1.9 1.9 C/W
o
R th j-a mb. Thermal Resistance Ambient-case Max 60 50 C/W
(*) When mounted using the minimum recommended pad size on FR-4 board.

CONNECTION DIAGRAMS (Top View)

PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10

CURRENT AND VOLTAGE CONVENTIONS

IDD ID

VDD DRAIN
IOSC -
OSC
13V +
VDD COMP SOURCE
VDS
ICOMP

VOSC

VCOMP

FC00020

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 VIPer50/SP - VIPer50A/ASP

ORDERING NUMBERS
PENT AW ATT HV PENTAW AT T HV (022Y) Pow erSO-10
VIP er50 VIPer50 (022Y) VIPer50SP
VIPer50A VIPer50A (022Y) VIPer50ASP

PINS FUNCTIONAL DESCRIPTION constant current source, and can easily be

connected to the output of an optocoupler.
DRAIN PIN: Note that any overvoltage due to regulation
Integrated power MOSFET drain pin. It provides loop failure is still detected by the error
internal bias current during start-up via an amplifier through the VDD voltage, which
integrated high voltage current source which is cannot overpass 13V. The output voltage will
switched off during normal operation. The device be somewhat higher than the nominal one, but
is able to handle an unclamped current during its still under control.
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and COMP PIN :
allowing a snubberless operation for low output This pin provides two functions :
power. - It is the output of the error transconductance
SOURCE PIN: amplifier, and allows for the connection of a
compensation network to provide the desired
Power MOSFET source pin. Primary side circuit
transfer function of the regulation loop. Its
common ground connection.
bandwidth can be easily adjusted to the
VDD PIN : needed value with usual components value. As
This pin provides two functions : stated above, secondary regulation
configurations are also implemented through
- It corresponds to the low voltage supply of the the COMP pin.
control part of the circuit. If VDD goes below 8V,
the start-up current source is activated and the - When the COMP voltage is going below 0.5V,
output power MOSFET is switched off until the the shut-down of the circuit occurs, with a zero
VDD voltage reaches 11V. During this phase, duty cycle for the power MOSFET. This feature
the internal current consumption is reduced, can be used to switch off the converter, and is
the VDD pin is sourcing a current of about 2mA automatically activated by the regulation loop
and the COMP pin is shorted to ground. After (whatever is the configuration) to provide a
that, the current source is shut down, and the burst mode operation in case of negligible
device tries to start up by switching again. output power or open load condition.

- This pin is also connected to the error OSC PIN :

amplifier, in order to allow primary as well as An RT-CT network must be connected on that pin
secondary regulation configurations. In case of to define the switching frequency. Note that
primary regulation, an internal 13V trimmed despite the connection of RT to VDD, no
reference voltage is used to maintain VDD at significant frequency change occurs for VDD
13V. For secondary regulation, a voltage varying from 8V to 15V. It provides also a
between 8.5V and 12.5V will be put on VDD pin synchronisation capability, when connected to an
by transformer design, in order to stuck the external frequency source.
output of the transconductance amplifier to the
high state. The COMP pin behaves as a

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VIPer50/SP - VIPer50A/ASP

AVALANCHE CHARACTERISTICS
Symb ol Parameter Max Valu e Unit
I D(a r) Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max, δ < 1%)
for VIPer50/SP 1.5 A
for VIPer50A/ASP (see fig. 12) 1.0 A
E (ar) Single Pulse Avalanche Energy 30 mJ
(starting Tj = 25 oC, ID = I D( ar)) (see fig. 12)

ELECTRICAL CHARACTERISTICS (TJ = 25 oC, VDD = 13 V, unless otherwise specified)

POWER SECTION
Symb ol Parameter T est Con ditio ns Min. Typ . Max. Un it
BV DSS Drain-Source Voltage I D = 1 mA V COMP = 0 V
for VIPer50/SP 620 V
for VIPer50A/ASP (see fig. 5) 700 V
o
I DSS Off-State Drain Current V COMP = 0 V TJ = 125 C
V DS = 620 V for VIPer50/SP 1 mA
V DS = 700 V for VIPer50A/ASP 1 mA
R DS( on) Static Drain Source on ID = 1 A
Resistance for VIPer50/SP 4.0 5.0 Ω
for VIPer50A/ASP 4.6 5.7 Ω
o
ID = 1 A TJ= 100 C
for VIPer50/SP 9.0 Ω
for VIPer50A/ASP 10.3 Ω
tf Fall T ime ID = 0.2 A Vin = 300 V (1) 100 ns
(see fig. 3)
tr Rise Time ID = 1 A V i n = 300 V (1) 50 ns
(see fig. 3)
C OSS Output Capacitance V DS = 25 V 120 pF
(1) On Inductive Load, Clamped.

SUPPLY SECTION
Symb ol Parameter T est Con ditio ns Min. Typ . Max. Un it
I DDch Start-up Charging V DD = 5 V VDS = 70 V -2 mA
Current (see fig. 2 and fig.15)
I DD0 Operating Supply Current V DD = 12 V, F SW = 0 KHz 12 16 mA
(see fig. 2)
I DD1 Operating Supply Current V DD = 12 V, F SW = 100 KHz 14 mA
I DD2 Operating Supply Current V DD = 12 V, F SW = 200 KHz 16 mA
V DDo ff Undervoltage Shutdown (see fig. 2) 8 V
V DDo n Undervoltage Reset (see fig. 2) 11 12 V
VDDhyst Hysteresis St art-up (see fig. 2) 2.4 3 V

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 VIPer50/SP - VIPer50A/ASP

ELECTRICAL CHARACTERISTICS (continued)

OSCILLATOR SECTION
Symb ol Parameter T est Con ditio ns Min. Typ . Max. Un it
F SW Oscillator F requency R T = 8.2 KΩ C T =2.4 nF 90 100 110 KHz
Total Variation V DD = 9 to15 V
with R T ± 1% CT ± 5%
(see fig.6 and fig.9)
V OSCih Oscillator Peak Voltage 7.1 V
V OSCi l Oscillator Valley Voltage 3.7 V

ERROR AMPLIFIER SECTION

Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
V DDreg VDD Regulation Point I COMP = 0 mA (see fig.1) 12.6 13 13.4 V
o
∆V DDreg Total Variation T J = 0 to 100 C 2 %
GBW Unity Gain Bandwidth From Input = V DD to O utput = V COMP 150 KHz
CO MP pin is open (see fig. 10)
A VOL Open Loop Voltage CO MP pin is open (see fig. 10) 45 52 dB
Gain
Gm DC T ransconductance V COMP = 2.5 V (see fig. 1) 1.1 1.5 1.9 mA/V
V COMPL O Output Low Level I COMP = -400 µA VDD = 14 V 0.2 V
V COMPHI Output High Level I COMP = 400 µA V DD = 12 V 4.5 V
I COMPLO Output Low Current V COMP = 2.5 V V DD = 14 V -600 µA
Capability
I COMPHI Output High Current V COMP = 2.5 V V DD = 12 V 600 µA
Capability

PWM COMPARATOR SECTION

Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
H ID ∆V COMP /∆IDpea k V COMP = 1 to 3 V 1.4 2 2.6 V/A
V COMPof f V COMP offset I Dp eak = 10 mA 0.5 V
I Dpeak Peak Current Limitation V DD = 12 V COMP pin open 1.5 2 2.7 A
td Current Sense Delay I D = 0.5 A 250 ns
to turn-off
tb Blanking Time 250 360 ns
t on( mi n) Minimum on T ime 350 ns

SHUTDOWN AND OVERTEMPERATURE SECTION

Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it
V COMPth Restart threshold (see fig. 4) 0.5 V
t DI Ssu Disable Set Up Time (see fig. 4) 1.7 5 µs
o
T t sd Thermal Shutdown (see fig. 8) 140 170 C
Temperature
o
T hyst Thermal Shutdown (see fig. 8) 40 C
Hysteresis

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VIPer50/SP - VIPer50A/ASP

Figure 1: VDD Regulation Point Figure 2: Undervoltage Lockout

ICOMP Slope =
IDD
ICOMPHI Gm in mA/V
IDD0
VDD VDS = 70 V
VDDhyst
0 Fsw = 0

VDDoff VDDon VDD

ICOMPLO
IDDch
VDDreg
FC00150 FC00170

Figure 3: Transition Time Figure 4: Shut Down Action

VOSC

ID
t

VCOMP
tDISsu
10% Ipeak
t

VDS VCOMPth t
90% VD
ID

10% VD
t
t
tf tr
FC00160 ENABLE ENABLE
DISABLE
FC00060

Figure 5: Breakdown Voltage vs Temperature Figure 6: Typical Frequency Variation

FC00180 FC00190
1.15 1
BVDSS (%)
(Normalized) 0
1.1
-1

1.05 -2

-3
1
-4

0.95 -5
0 20 40 60 80 100 120 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

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 VIPer50/SP - VIPer50A/ASP

Figure 7: Start-up Waveforms

Figure 8: Overtemperature Protection

Tj
Ttsd

Ttsd-Thyst

Vdd

Vddon
Vddoff

Id

Vcomp

SC10191

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VIPer50/SP - VIPer50A/ASP

Figure 9: Oscillator

VDD For RT > 1.2 KΩ:

Rt
OSC 2.3
FSW = D
RT CT MAX
CLK 550
DMAX = 1 −
RT − 150
~360Ω

Ct
Recommended DMAX values:
100KHz: > 80%
200KHz: > 70%

FC00050

Maximum duty cycle vs Rt

FC00040
1

0.9

0.8
Dmax

0.7

0.6

0.5
1 2 3 5 10 20 30 50
Rt (kΩ)
Oscillator frequency vs Rt and Ct
FC00030
1,000
Ct = 1.5 nF

500
Ct = 2.7 nF

300
Frequency (kHz)

Ct = 4.7 nF
200

Ct = 10 nF
100

50

30
1 2 3 5 10 20 30 50
Rt (kΩ)

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 VIPer50/SP - VIPer50A/ASP

Figure 10: Error Amplifier Frequency Response

FC00200
60
RCOMP = +∞

RCOMP = 270k
40
Voltage Gain (dB)

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k
20

(20)
0.001 0.01 0.1 1 10 100 1,000
Frequency (kHz)

Figure 11: Error Amplifier Phase Response

FC00210

200
RCOMP = +∞

150 RCOMP = 270k

RCOMP = 82k

RCOMP = 27k
Phase (°)

100 RCOMP = 12k

50

(50)
0.001 0.01 0.1 1 10 100 1,000
Frequency (kHz)

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VIPer50/SP - VIPer50A/ASP

Figure 12: Avalance Test Circuit

L1
1mH

2 3
VD D DRAIN
Q1
- 2 x STHV102FIin parallel
1 R1
OSC
13V + BT1
0 to 20V
COMP SOURCE 47 GENERATOR INPUT
5 4 500us PULSE
C1 U1
BT2 47uF VIPer100
12V 16V
R2 R3
1k 100

FC00195

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 VIPer50/SP - VIPer50A/ASP

Figure 13: Off Line Power Supply With Auxliary Supply Feedback

F1

TR2 BR1
C1 TR1
AC IN D2 L2
+Vcc
D1
R9
C2
C7 C9
R1

C3 GND
D3
C10
R7
C4

R2
VDD DRAIN
-
OSC
VIPer50
13V +
COMP SOURCE
C5

C6
C11
R3
FC00301

Figure 14: Off Line Power Supply With Optocoupler Feedback

F1

TR2 BR1
C1 TR1
AC IN D2 L2
+Vcc
D1
R9
C2
C7 C9
R1

C3 GND
D3
C10
R7
C4

R2
VDD DRAIN
-
OSC VIPer50
13V +
COMP SOURCE
C5

C6
C11 R6
ISO1
R3

R4
C8
U2

R5

FC00311

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VIPer50/SP - VIPer50A/ASP

OPERATION DESCRIPTION : Where:

LP is the primary inductance of the transformer.
CURRENT MODE TOPOLOGY:
FSW is the normal switching frequency.
The current mode control method, like the one
ISTBY is the minimum controllable current,
integrated in the VIPer50/50A uses two control
corresponding to the minimum on time that the
loops - an inner current control loop and an outer
loop for voltage control. When the Power device is able to provide in normal operation. This
current can be computed as :
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is (tb + td) VIN
ISTBY =
monitored with a SenseFET technique and LP
converted into a voltage VS proportional to this tb + td is the sum of the blanking time and of the
current. When VS reaches VCOMP (the amplified propagation time of the internal current sense
output voltage error) the power switch is switched and comparator, and represents roughly the
off. Thus, the outer voltage control loop defines minimum on time of the device. Note that PSTBY
the level at which the inner loop regulates peak may be affected by the efficiency of the converter
current through the power switch and the primary at low load, and must include the power drawn on
winding of the transformer. the primary auxiliary voltage.
Excellent open loop D.C. and dynamic line As soon as the power goes below this limit, the
regulation is ensured due to the inherent input auxiliary secondary voltage starts to increase
voltage feedforward characteristic of the current above the 13V regulation level forcing the output
mode control. This results in an improved line voltage of the transconductance amplifier to low
regulation, instantaneous correction to line state (VCOMP < VCOMPth). This situation leads to
changes and better stability for the voltage the shutdown mode where the power switch is
regulation loop. maintained in the off state, resulting in missing
Current mode topology also ensures good cycles and zero duty cycle. As soon as VDD gets
limitation in the case of short circuit. During a first back to the regulation level and the VCOMPth
phase the output current increases slowly threshold is reached, the device operates again.
following the dynamic of the regulation loop. Then The above cycle repeats indefinitely, providing a
it reaches the maximum limitation current burst mode of which the effective duty cycle is
internally set and finally stops because the power much lower than the minimum one when in
supply on VDD is no longer correct. For specific normal operation. The equivalent switching
applications the maximum peak current internally frequency is also lower than the normal one,
set can be overridden by externally limiting the leading to a reduced consumption on the input
voltage excursion on the COMP pin. An mains lines. This mode of operation allows the
integrated blanking filter inhibits the PWM VIPer50/50A to meet the new German ”Blue
comparator output for a short time after the Angel” Norm with less than 1W total power
integrated Power MOSFET is switched on. This consumption for the system when working in
function prevents anomalous or premature stand-by. The output voltage remains regulated
termination of the switching pulse in the case of around the normal level, with a low frequency
current spikes caused by primary side ripple corresponding to the burst mode. The
capacitance or secondary side rectifier reverse amplitude of this ripple is low, because of the
recovery time. output capacitors and of the low output current
drawn in such conditions.The normal operation
STAND-BY MODE
resumes automatically when the power get back
Stand-by operation in nearly open load condition to higher levels than PSTBY.
automatically leads to a burst mode operation
allowing voltage regulation on the secondary HIGH VOLTAGE START-UP CURRENT
side. The transition from normal operation to SOURCE
burst mode operation happens for a power PSTBY An integrated high voltage current source
given by : provides a bias current from the DRAIN pin
1 2 during the start-up phase. This current is partially
PSTBY = LP ISTBY FSW
2 absorbed by internal control circuits which are

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 VIPer50/SP - VIPer50A/ASP

placed into a standby mode with reduced short circuit.

consumption and also provided to the external The external capacitor CVDD on the VDD pin must
capacitor connected to the VDD pin. As soon as be sized according to the time needed by the
the voltage on this pin reaches the high voltage converter to start up, when the device starts
threshold VDDon of the UVLO logic, the device switching. This time tSS depends on many
turns into active mode and starts switching. The parameters, among which transformer design,
start up current generator is switched off, and the output capacitors, soft start feature and
converter should normally provide the needed compensation network implemented on the
current on the VDD pin through the auxiliary COMP pin. The following formula can be used for
winding of the transformer, as shown on figure defining the minimum capacitor needed:
15. IDD tSS
In case of abnormal condition where the auxiliary CVDD >
VDDhyst
winding is unable to provide the low voltage
where:
supply current to the VDD pin (i.e. short circuit on
the output of the converter), the external IDD is the consumption current on the VDD pin
capacitor discharges itself down to the low when switching. Refer to specified IDD1 and IDD2
threshold voltage VDDoff of the UVLO logic, and values.
the device get back to the inactive state where tSS is the start up time of the converter when the
the internal circuits are in standby mode and the device begins to switch. Worst case is generally
start up current source is activated. The converter at full load.
enters a endless start up cycle, with a start-up VDDhyst is the voltage hysteresis of the UVLO
duty cycle defined by the ratio of charging current logic. Refer to the minimum specified value.
towards discharging when the VIPer50/50A tries Soft start feature can be implemented on the
to start. This ratio is fixed by design to 2 to 15, COMP pin through a simple capacitor which will
which gives a 12% start up duty cycle while the be also used as the compensation network. In
power dissipation at start up is approximately 0.6 this case, the regulation loop bandwidth is rather
W, for a 230 Vrms input voltage. This low value of low, because of the large value of this capacitor.
start-up duty cycle prevents the stress of the In case a large regulation loop bandwidth is
output rectifiers and of the transformer when in mandatory, the schematics of figure 16 can be

Figure 15: Behaviour of the high voltage current source at start-up

VDD 2 mA 3 mA DRAIN
VDD
VDDon
15 mA 1 mA 15 mA
VDDoff

CVDD

Ref.

t UNDERVOLTAGE
Auxiliary primary LOCK OUT LOGIC
winding
VIPer50 SOURCE

Start up duty cycle ~ 12% FC0032 0

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VIPer50/SP - VIPer50A/ASP

used. It mixes a high performance compensation and therefore AVOL are subject to large
network together with a separate high value soft tolerances. An impedance Z can be connected
start capacitor. Both soft start time and regulation between the COMP pin and ground in order to
loop bandwidth can be adjusted separately. define more accurately the transfer function F of
If the device is intentionally shut down by putting the error amplifier, according to the following
the COMP pin to ground, the device is also equation, very similar to the one above:
performing start-up cycles, and the VDD voltage is F(S) = Gm x Z(S)
oscillating between VDDon and VDDoff. This voltage The error amplifier frequency response is
can be used for supplying external functions, reported in figure 10 for different values of a
provided that their consumption doesn’t exceed simple resistance connected on the COMP pin.
0.5mA. Figure 17 shows a typical application of The unloaded transconductance error amplifier
this function, with a latched shut down. Once the shows an internal ZCOMP of about 330 KΩ. More
”Shutdown” signal has been activated, the device complex impedance can be connected on the
remains in the off state until the input voltage is COMP pin to achieve different compensation
removed. laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
TRANSCONDUCTANCE ERROR AMPLIFIER a resistance in series leads to a flat gain at higher
The VIPer50/50A includes a transconductance frequency, insuring a correct phase margin. This
error amplifier. Transconductance Gm is the configuration is illustrated on figure 18.
change in output current (ICOMP) versus change As shown in figure 18 an additional noise filtering
in input voltage (VDD). Thus: capacitor of 2.2 nF is generally needed to avoid
∂ ICOMP any high frequency interference.
Gm =
∂ VDD It can be also interesting to implement a slope
The output impedance ZCOMP at the output of this compensation when working in continuous mode
amplifier (COMP pin) can be defined as: with duty cycle higher than 50%. Figure 19 shows
∂ VCOMP 1 ∂ VCOMP such a configuration. Note that R1 and C2 build
ZCOMP = = x
∂ ICOMP Gm ∂ VDD the classical compensation network, and Q1 is
This last equation shows that the open loop gain injecting the slope compensation with the correct
AVOL can be related to Gm and Z COMP: polarity from the oscillator sawtooth.
AVOL = Gm x ZCOMP EXTERNAL CLOCK SYNCHRONIZATION:
where Gm value for VIPer50/50A is 1.5 mA/V The OSC pin provides a synchronisation
typically. capability, when connected to an external
Gm is well defined by specification, but ZCOMP frequency source. Figure 20 shows one possible

Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down

D2

D3
VIPer50
R1 VIPer50
VDD DRAIN
- VDD DRAIN
OSC
R3 Q2 -
13V + OSC
COMP SOURCE 13V +
D1 COMP SOURCE
AUXILIARY
WINDI NG R3 R2
C4 R1
R2 R4
+ C3 C1 + C2 Shutdown Q1 D1

FC00331 FC00340

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 VIPer50/SP - VIPer50A/ASP

schematic to be adapted depending the specific where:

needs. If the proposed schematic is used, the R1 + R2
pulse duration must be kept at a low value (500ns VCOMP = 0.6 x
R2
is sufficient) for minimizing consumption. The
The suggested value for R1+R2 is in the range of
optocoupler must be able to provide 20mA
220KΩ.
through the optotransistor.
OVER-TEMPERATURE PROTECTION:
PRIMARY PEAK CURRENT LIMITATION
Over-temperature protection is based on chip
The primary IDPEAK current and, as resulting
temperature sensing. The minimum junction
effect, the output power can be limited using the
temperature at which over-temperature cut-out
simple circuit shown in figure 21. The circuit
occurs is 140oC while the typical value is 160oC.
based on Q1, R1 and R2 clamps the voltage on
The device is automatically restarted when the
the COMP pin in order to limit the primary peak
junction temperature decreases to the restart
current of the device to a value:
temperature threshold that is typically 40oC below
VCOMP − 0.5 the shutdown value (see figure 8).
IDPEAK =
HID

Figure 18: Typical Compensation Network Figure 19: Slope Compensation

VIPer50
R2 R1
VDD DRAIN
- VIPer50
OSC VDD DRAIN
13V + -
COMP SOURCE OSC
13V +
COMP SOURCE

C2 R1 C2

C1 Q1 C3

C1 R3

FC00351
FC00361

Figure 20:External Clock Synchronization Figure 21:Current Limitation Circuit Example

VIPer50
VDD DRAIN
-
OSC
13V +
VIPer50
COMP SOURCE
VDD DRAIN
-
OSC
13V +
COMP SOURCE R1
10 kΩ
Q1

R2

FC00370

FC00380

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VIPer50/SP - VIPer50A/ASP

Figure 22: Recommended layout

T1
D1

To sec ondary
C7
D2 filtering and load

R1 2 3
VDD DRAIN

C1 -
1 OSC C5
13V +
From input
COMP SOURCE
diodes bridge
5 4
U1
VIPerXX0

R2 C6

C2
C3

ISO1 C4

FC00500

LAYOUT CONSIDERATIONS power ones. The interferences due to a mixing

Some simple rules insure a correct running of of signal and power may result in instabilities
switching power supplies. They may be classified and/or anomalous behaviour of the device in
into two categories: case of violent power surge (Input
overvoltages, output short circuits...).
- To minimise power loops: the way the switched
power current must be carefully analysed and In case of VIPer, these rules apply as shown on
the corresponding paths must present the figure 22. The loops C1-T1-U1, C5-D2-T1,
smallest inner loop area as possible. This C7-D1-T1 must be minimised. C6 must be as
avoids radiated EMC noises, conducted EMC close as possible from T1. The signal
noises by magnetic coupling, and provides a components C2, ISO1, C3 and C4 are using a
better efficiency by eliminating parasitic dedicated track to be connected directly to the
inductances, especially on secondary side. source of the device.
- To use different tracks for low level signals and

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 VIPer50/SP - VIPer50A/ASP

PENTAWATT HV (VERTICAL) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.60 17.30 0.653 0.681
L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 7.56 8.16 0.298 0.321
R 0.50 0.020
V4 90o 90
Diam. 3.70 3.90 0.146 0.154

E L1

M1
A
M

R D C
leads
between
Resin

L6

L7
V4
G2

G1

H1
H3

H2
F

L2
Diam

L3 L5
P023H3

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VIPer50/SP - VIPer50A/ASP

PENTAWATT HV 022Y(VERTICAL HIGH PITCH) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 5.00 5.70 0.197 0.224
R 0.50 0.020
o
V4 90 90o
Diam. 3.70 3.90 0.146 0.154

L1
E

M1 A
M

R D C
leads
between
Resin

L6

L7
V4
G2

G1

H1
H3

H2
F

Diam

L3 L5
P023H2

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 VIPer50/SP - VIPer50A/ASP

PowerSO-10 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
C 0.35 0.55 0.013 0.022
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
e 1.27 0.050
E 9.30 9.50 0.366 0.374
E1 7.20 7.40 0.283 0.291
E2 7.20 7.60 0.283 0.300
E3 6.10 6.35 0.240 0.250
E4 5.90 6.10 0.232 0.240
F 1.25 1.35 0.049 0.053
h 0.50 0.002
H 13.80 14.40 0.543 0.567
L 1.20 1.80 0.047 0.071
q 1.70 0.067
α 0o 8o

0.10 A B
10 6
=

=
=

H E E2 E3 E1 E4
=
=

=
=
=

1 5
SEATING
PLANE

e B DETAIL ”A” A

0.25 M C
Q
D
h = D1 =
= =
SEATING
PLANE
A
F
A1 A1

L
DETAIL ”A”

α
0068039-C

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VIPer50/SP - VIPer50A/ASP

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