VIPer50/SP

® - VIPer50A/ASP

SMPS PRIMARY I.C.

TYPE VDSS In RDS(on)
VIPer50/SP 620V 1.5 A 5Ω
VIPer50A/ASP 700V 1.5 A 5.7 Ω

10
■ ADJUSTABLE SWITCHING FREQUENCY UP PENTAWATT HV PENTAWATT HV
TO 200 kHz 1
(022Y)
■ CURRENT MODE CONTROL PowerSO-10™
■ SOFT START AND SHUT DOWN CONTROL

■ AUTOMATIC BURST MODE OPERATION IN DESCRIPTION

STAND-BY CONDITION ABLE TO MEET VIPer50™/50A, made using VIPower M0
“BLUE ANGEL” NORM (<1W TOTAL POWER Technology, combines on the same silicon chip a
CONSUMPTION) state-of-the-art PWM circuit together with an
■ INTERNALLY TRIMMED ZENER REFERENCE optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 1.5A).
■ UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS Typical applications cover off line power supplies
with a secondary power capability of 25W in wide
■ INTEGRATED START-UP SUPPLY range condition and 50W in single range or with
■ AVALANCHE RUGGED doubler configuration. It is compatible from both
■ OVERTEMPERATURE PROTECTION
primary or secondary regulation loop despite
using around 50% less components when
■ LOW STAND-BY CURRENT compared with a discrete solution. Burst mode
■ ADJUSTABLE CURRENT LIMITATION operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
BLOCK DIAGRAM

OSC DRAIN

ON/OFF
OSCILLATOR

SECURITY PWM
LATCH LATCH

UVLO FF S
VDD R/S Q R1 FF Q
LOGIC
S R2 R3

OVERTEMP.
DETECTOR

0.5V
_
0.5 V + 1.7 µ s + + 2 V/A
250 ns
_ DELAY BLANKING _

ERROR CURRENT
AMPLIFIER
_ AMPLIFIER

13 V +
4.5 V
FC00291

COMP SOURCE

May 2003 1/23

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 VIPer50/SP - VIPer50A/ASP

ABSOLUTE MAXIMUM RATING

Symbol Parameter Value Unit
Continuous Drain-Source Voltage (Tj=25 to 125°C)
VDS for VIPer50/SP -0.3 to 620 V
for VIPer50A/ASP -0.3 to 700 V
ID Maximum Current Internally limited A
VDD Supply Voltage 0 to 15 V
VOSC Voltage Range Input 0 to VDD V
VCOMP Voltage Range Input 0 to 5 V
ICOMP Maximum Continuous Current ±2 mA
Vesd Electrostatic Discharge (R =1.5kΩ; C=100pF) 4000 V
Avalanche Drain-Source Current, Repetitive or Not Repetitive
(TC=100°C; Pulse width limited by Tj max; δ < 1%)
ID(AR) 1.5 A
for VIPer50/SP
for VIPer50A/ASP 1 A
Ptot Power Dissipation at Tc=25ºC 60 W
Tj Junction Operating Temperature Internally limited °C
Tstg Storage Temperature -65 to 150 °C

THERMAL DATA
Symbol Parameter PENTAWATT HV PowerSO-10™ (*) Unit
Rthj-case Thermal Resistance Junction-case Max 1.9 1.9 °C/W
Rthj-amb. Thermal Resistance Ambient-case Max 60 50 °C/W

(*) When mounted using the minimum recommended pad size on FR-4 board.
CONNECTION DIAGRAMS (Top View)

PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10™

CURRENT AND VOLTAGE CONVENTIONS

IDD ID

VDD DRAIN
IOSC -
OSC
13V +
VDD COMP SOURCE
VDS
ICOMP

VOSC

VCOMP

FC00020

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ORDERING NUMBERS
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10™
VIPer50 VIPer50 (022Y) VIPer50SP
VIPer50A VIPer50A (022Y) VIPer50ASP

PINS FUNCTIONAL DESCRIPTION

DRAIN PIN:
Integrated Power MOSFET drain pin. It provides source, and can easily be connected to the
internal bias current during start-up via an output of an optocoupler. Note that any
integrated high voltage current source which is overvoltage due to regulation loop failure is still
switched off during normal operation. The device detected by the error amplifier through the VDD
is able to handle an unclamped current during its voltage, which cannot overpass 13V. The
normal operation, assuring self protection against output voltage will be somewhat higher than the
voltage surges, PCB stray inductance, and nominal one, but still under control.
allowing a snubberless operation for low output
power.
COMP PIN:
This pin provides two functions:
SOURCE Pin:
Power MOSFET source pin. Primary side circuit - It is the output of the error transconductance
common ground connection. amplifier, and allows for the connection of a
compensation network to provide the desired
VDD Pin: transfer function of the regulation loop. Its
This pin provides two functions: bandwidth can easily be adjusted to the
needed value with usual components value. As
stated above, secondary regulation
- It corresponds to the low voltage supply of the configurations are also implemented through
control part of the circuit. If VDD goes below 8V, the COMP pin.
the start-up current source is activated and the
output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase, - When the COMP voltage goes below 0.5V, the
the internal current consumption is reduced, shut-down of the circuit occurs, with a zero
the VDD pin sources a current of about 2mA duty cycle for the power MOSFET. This feature
and the COMP pin is shorted to ground. After can be used to switch off the converter, and is
that, the current source is shut down, and the automatically activated by the regulation loop
device tries to start up by switching again. (whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary OSC PIN:
regulation, an internal 13V trimmed reference An Rt-Ct network must be connected on that pin to
voltage is used to maintain VDD at 13V. For define the switching frequency. Note that despite
secondary regulation, a voltage between 8.5V the connection of Rt to VDD, no significant
and 12.5V will be put on VDD pin by transformer frequency change occurs for VDD varying from 8V
design, in order to stick the output of the to 15V. It also provides a synchronization
transconductance amplifier to the high state. capability, when connected to an external
The COMP pin behaves as a constant current frequency source.

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AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
Avalanche Current, Repetitive or Not Repetitive
(pulse widht limited by Tj max; δ < 1%)
ID(AR) 1.5 A
for VIPer50/SP
for VIPer50A/ASP (see fig.12) 1.0 A
Single Pulse Avalanche Energy
E(ar) 30 mJ
(starting Tj =25ºC, I D=ID(ar)) (see fig.12)

ELECTRICAL CHARACTERISTICS (Tj=25°C; VDD=13V, unless otherwise specified)

POWER SECTION
Symbol Parameter Test Conditions Min Typ Max Unit
ID=1mA; VCOMP=0V
BVDSS Drain-Source Voltage for VIPer50/SP 620 V
for VIPer50A/ASP (see fig.5) 700 V
VCOMP=0V; Tj=125°C
IDSS Off-State Drain Current VDS=620V for VIPer50/SP 1 mA
VDS=700V for VIPer50A/ASP 1 mA

ID=1A
for VIPer50/SP 4.0 5.0 Ω
Static Drain-Source for VIPer50A/ASP 4.6 5.7 Ω
RDS(on)
On Resistance ID=1A; Tj=100°C
for VIPer50/SP 9.0 Ω
for VIPer50A/ASP
10.3 Ω
ID=0.2A; VIN=300V (1) 100 ns
tf Fall Time
(See fig. 3)
ID=1A; VIN=300V (1) 50 ns
tr Rise Time
(See fig. 3)
Coss Output Capacitance VDS=25V 120 pF

(1) On Inductive Load, Clamped.

SUPPLY SECTION
Symbol Parameter Test Conditions Min Typ Max Unit
Start-Up Charging VDD=5V; VDS=35V -2 mA
IDDch
Current (see fig. 2 and fig. 15)
Operating Supply Current VDD=12V; FSW=0kHz 12 16 mA
IDD0
(see fig. 2)
IDD1 Operating Supply Current VDD=12V; Fsw=100kHz 14 mA
IDD2 Operating Supply Current VDD=12V; Fsw=200kHz 16 mA
VDDoff Undervoltage Shutdown (See fig. 2) 7.5 8 9 V
VDDon Undervoltage Reset (See fig. 2) 11 12 V
VDDhyst Hysteresis Start-up (See fig. 2) 2.4 3 V

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VIPer50/SP - VIPer50A/ASP

ELECTRICAL CHARACTERISTICS (continued)

OSCILLATOR SECTION
Symbol Parameter Test Conditions Min Typ Max Unit
Rt=8.2KΩ; Ct=2.4nF 90 100 110 kHz
Oscillator Frequency VDD=9 to 15V;
FSW
Total Variation with Rt± 1%; Ct± 5%
(see fig. 6 and fig. 9)
VOSCih Oscillator Peak Voltage 7.1 V
VOSCil Oscillator Valley Voltage 3.7 V

ERROR AMPLIFIER SECTION

Symbol Parameter Test Conditions Min Typ Max Unit
VDDreg VDD Regulation Point ICOMP=0mA (see fig. 1) 12.6 13 13.4 V
∆VDDreg Total Variation Tj=0 to 100°C 2 %
From Input =VDD to Output = VCOMP 150 kHz
GBW Unity Gain Bandwidth
COMP pin is open (see fig. 10)
AVOL Open Loop Voltage Gain COMP pin is open (see fig. 10) 45 52 dB
Gm DC Transconductance VCOMP=2.5V (see fig. 1) 1.1 1.5 1.9 mA/V
VCOMPLO Output Low Level ICOMP= -400µA; VDD=14V 0.2 V
VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V
Output Low Current
ICOMPLO VCOMP=2.5V; VDD=14V -600 µA
Capability
Output High Current
ICOMPHI VCOMP=2.5V; VDD=12V 600 µA
Capability

PWM COMPARATOR SECTION

Symbol Parameter Test Conditions Min Typ Max Unit
HID ∆VCOMP / ∆IDPEAK VCOMP=1 to 3 V 1.4 2 2.6 V/A
VCOMPoff VCOMP Offset IDPEAK=10mA 0.5 V
IDpeak Peak Current Limitation VDD=12V; COMP pin open 1.5 2 2.7 A
Current Sense Delay to
td ID=0.5A 250 ns
Turn-Off
tb Blanking Time 250 360 ns
ton(min) Minimum On Time 350 1200 ns

SHUTDOWN AND OVERTEMPERATURE SECTION

Symbol Parameter Test Conditions Min Typ Max Unit
VCOMPth Restart Threshold (see fig. 4) 0.5 V
tDISsu Disable Set Up Time (see fig. 4) 1.7 5 µs
Thermal Shutdown
Ttsd (See fig. 8) 140 170 °C
Temperature
Thermal Shutdown
Thyst (See fig. 8) 40 °C
Hysteresis

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 VIPer50/SP - VIPer50A/ASP

Figure 1: VDD Regulation Point Figure 2: Undervoltage Lockout

ICOMP Slope =
IDD
ICOMPHI Gm in mA/V
IDD0
VDD VDS= 35 V
0 VDDhyst
Fsw = 0

ICOMPLO VDDoff VDDon VDD

IDDch
VDDreg
FC00150 FC00170

Figure 3: Transition Time Figure 4: Shut Down Action

VOSC

ID
t

VCOMP
10% Ipeak tDISsu
t

VDS VCOMPth t
90% VD
ID

10% VD
t t
tf tr
FC00160 ENABLE ENABLE
DISABLE
FC00060

Figure 5: Breakdown Voltage Vs. Temperature Figure 6: Typical Frequency Variation

FC00180 FC00190
1.15 1
BVDSS (%)
(Normalized) 0
1.1
-1

1.05 -2

-3
1
-4

0.95 -5
0 20 40 60 80 100 120 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

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VIPer50/SP - VIPer50A/ASP

Figure 7: Start-Up Waveforms

Figure 8: Overtemperature Protection

TJ
Ttsc
Ttsd-Thyst

t
Vdd
Vddon
Vddoff

t
Id

t
Vcomp

t
SC10191

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 VIPer50/SP - VIPer50A/ASP

Figure 9: Oscillator

VDD
For Rt >1.2KΩ
Rt and
OSC
Ct ≥ 15nF if FSW ≤ 40KHz

F SW = ------------ ⋅  1 – ----------------------
2.3 550
CLK
R t Ct  Rt – 150
~360Ω

Ct

FC00050

Ct

Forbidden area

880
Ct(nF) =
Fsw(kHz)
22nF

15nF

Forbidden area

40kHz
Fsw

Oscillator frequency vs Rt and Ct

FC00030
1,000
Ct = 1.5 nF

500
Ct = 2.7 nF

300
Frequency (kHz)

Ct = 4.7 nF
200

Ct = 10 nF
100

50

30
1 2 3 5 10 20 30 50
Rt (kΩ)

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Figure 10: Error Amplifier Frequency Response

FC00200
60
RCOMP = +∞

RCOMP = 270k
40
Voltage Gain (dB)

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k
20

(20)
0.001 0.01 0.1 1 10 100 1,000
Frequency (kHz)

Figure 11: Error Amplifier Phase Response

FC00210
200
RCOMP = +∞

150 RCOMP = 270k

RCOMP = 82k

RCOMP = 27k
Phase (°)

100 RCOMP = 12k

50

(50)
0.001 0.01 0.1 1 10 100 1,000
Frequency (kHz)

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Figure 12: Avalanche Test Circuit

L1
1mH

2 3
VDD DRAIN
Q1
2 x STHV102FI in parallel
1
- R1
OSC
13V + BT1
0 to 20V
COMP SOURCE 47 GENERATOR INPUT
5 4 500us PULSE
C1 U1
BT2 47uF VIPer100
12V 16V
R2 R3
1k 100

FC00195

10/23

1
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Figure 13: Off Line Power Supply With Auxiliary Supply Feedback

F1

TR2 BR1
C1 TR1
AC IN D2 L2
+Vcc
D1
R9
C2
C7 C9
R1

C3 GND
D3
C10
R7
C4

R2
VDD DRAIN
-
OSC
VIPer50
13V +
COMP SOURCE
C5

C6
C11
R3
FC00301

Figure 14: Off Line Power Supply With Optocoupler Feedback

F1

TR2 BR1
C1 TR 1
AC IN D2 L2
+V cc
D1
R9
C2
C7 C9
R1

C3 GND
D3
C1 0
R7
C4

R2
V DD DR AIN
-
O SC V IP er50
13V +
COMP S O UR C E
C5

C6
C 11 R6
IS O 1
R3

R4
C8
U2

R5

F C 0 0311

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OPERATION DESCRIPTION: FSW is the normal switching frequency.

ISTBY is the minimum controllable current,
CURRENT MODE TOPOLOGY corresponding to the minimum on time that the
device is able to provide in normal operation. This
The current mode control method, like the one current can be computed as:
integrated in the VIPer50/50A uses two control
loops - an inner current control loop and an outer ( t b + td )V IN
loop for voltage control. When the Power I STBY = --------------------------------
L
MOSFET output transistor is on, the inductor P
current (primary side of the transformer) is tb + td is the sum of the blanking time and of the
monitored with a SenseFET technique and propagation time of the internal current sense and
converted into a voltage VS proportional to this comparator, and roughly represents the minimum
current. When VS reaches VCOMP (the amplified on time of the device. Note that PSTBY may be
output voltage error) the power switch is switched affected by the efficiency of the converter at low
off. Thus, the outer voltage control loop defines load, and must include the power drawn on the
the level at which the inner loop regulates peak primary auxiliary voltage.
current through the power switch and the primary
winding of the transformer. As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
Excellent D.C. open loop and dynamic line above the 13V regulation level forcing the output
regulation is ensured due to the inherent input voltage of the transconductance amplifier to low
voltage feedforward characteristic of the current state (VCOMP < VCOMPth). This situation leads to
mode control. This results in an improved line the shutdown mode where the power switch is
regulation, instantaneous correction to line maintained in the off state, resulting in missing
changes and better stability for the voltage cycles and zero duty cycle. As soon as VDD gets
regulation loop. back to the regulation level and the VCOMPth
Current mode topology also ensures good threshold is reached, the device operates again.
limitation in the case of short circuit. During the The above cycle repeats itself indefinitely,
first phase the output current increases slowly providing a burst mode of which the effective duty
following the dynamic of the regulation loop. Then cycle is much lower than the minimum one when in
it reaches the maximum limitation current normal operation. The equivalent switching
internally set and finally stops because the power frequency is also lower than the normal one,
supply on VDD is no longer correct. For specific leading to a reduced consumption on the input
applications the maximum peak current internally mains lines. This mode of operation allows the
set can be overridden by limiting the voltage VIPer50/50A to meet the new German "Blue
excursion externally on the COMP pin. An Angel" Norm with less than 1W total power
integrated blanking filter inhibits the PWM consumption for the system when working in
comparator output for a short time after the stand-by. The output voltage remains regulated
integrated Power MOSFET is switched on. This around the normal level, with a low frequency
function prevents anomalous or premature ripple corresponding to the burst mode. The
termination of the switching pulse in the case of amplitude of this ripple is low, because of the
current spikes caused by primary side capacitance output capacitors and because of the low output
or secondary side rectifier reverse recovery time. current drawn in such conditions. The normal
operation resumes automatically when the power
gets back levels which are higher than PSTBY.
STAND-BY MODE
Stand-by operation in nearly open load condition
HIGH VOLTAGE START-UP CURRENT
automatically leads to a burst mode operation
SOURCE
allowing voltage regulation on the secondary side.
The transition from normal operation to burst An integrated high voltage current source provides
mode operation happens for a power PSTBY given a bias current from the DRAIN pin during the start-
by: up phase. This current is partially absorbed by
internal control circuits which are placed into a
1 2 standby mode with reduced consumption and are
P STBY = --- L I STBY F
2 P SW also provided to the external capacitor connected
Where: to the VDD pin. As soon as the voltage on this pin
reaches the high voltage threshold VDDon of the
LP is the primary inductance of the transformer.

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 VIPer50/SP - VIPer50A/ASP

UVLO logic, the device turns into active mode and where:
starts switching. IDD is the consumption current on the VDD pin
The start up current generator is switched off, and when switching. Refer to specified IDD1 and IDD2
the converter should normally provide the needed values.
current on the VDD pin through the auxiliary tSS is the start up time of the converter when the
winding of the transformer, as shown on figure 15. device begins to switch. Worst case is generally at
In case of abnormal condition where the auxiliary full load.
winding is unable to provide the low voltage supply VDDhyst is the voltage hysteresis of the UVLO
current to the VDD pin (i.e. short circuit on the logic. Refer to the minimum specified value.
output of the converter), the external capacitor
discharges itself down to the low threshold voltage Soft start feature can be implemented on the
VDDoff of the UVLO logic, and the device gets back COMP pin through a simple capacitor which will
to the inactive state where the internal circuits are also be used as the compensation network. In this
in standby mode and the start up current source is case, the regulation loop bandwidth is rather low,
activated. The converter enters an endless start because of the large value of this capacitor. In
up cycle, with a start-up duty cycle defined by the case of a large regulation loop bandwidth is
ratio of charging current towards discharging when mandatory, the schematics in figure 16 can be
the VIPer50/50A tries to start. This ratio is fixed by used. It mixes a high performance compensation
design from 2 to 15, which gives a 12% start up network together with a separate high value soft
duty cycle while the power dissipation at start up is start capacitor. Both soft start time and regulation
approximately 0.6 W, for a 230 Vrms input voltage. loop bandwidth can be adjusted separately.
This low value of start-up duty cycle prevents the If the device is intentionally shut down by putting
stress of the output rectifiers and of the the COMP pin to ground, the device is also
transformer when in short circuit. performing start-up cycles, and the VDD voltage is
The external capacitor CVDD on the VDD pin must oscillating between VDDon and VDDoff.
be sized according to the time needed by the This voltage can be used for supplying external
converter to start up, when the device starts functions, provided that their consumption doesn’t
switching. This time tSS depends on many exceed 0.5mA. Figure 17 shows a typical
parameters, among which transformer design, application of this function, with a latched shut
output capacitors, soft start feature and down. Once the "Shutdown" signal has been
compensation network implemented on the COMP activated, the device remains in the off state until
pin. The following formula can be used for defining the input voltage is removed.
the minimum capacitor needed:
I DD tSS
CVDD > --------------------------
V DDhyst

Figure 15: Behavior of the high voltage current source at start-up

VDD 2 mA 3 mA DRAIN
VDD
VDDon
15 mA 1 mA 15 mA
VDDoff

CVDD
Ref.

t UNDERVOLTAGE
Auxiliary primary LOCK OUT LOGIC
winding
VIPer50 SOURCE

Start up duty cycle ~ 12% FC00320

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 VIPer50/SP - VIPer50A/ASP

TRANSCONDUCTANCE ERROR AMPLIFIER achieve different compensation laws. A capacitor

The VIPer50/50A includes a transconductance will provide an integrator function, thus eliminating
error amplifier. Transconductance Gm is the the DC static error, and a resistance in series
change in output current (ICOMP) versus change in leads to a flat gain at higher frequency, insuring a
input voltage (VDD). Thus: correct phase margin. This configuration is
illustrated in figure 18.
∂I COMP
G = ------------------------
m ∂V DD As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
The output impedance ZCOMP at the output of this any high frequency interference.
amplifier (COMP pin) can be defined as:
It can also be interesting to implement a slope
∂V COMP 1 ∂V COMP compensation when working in continuous mode
Z COMP = --------------------------- = --------- × --------------------------- with duty cycle higher than 50%. Figure 19 shows
∂I COMP G ∂V DD such a configuration. Note that R1 and C2 build
m
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
This last equation shows that the open loop gain polarity from the oscillator sawtooth.
AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
EXTERNAL CLOCK SYNCHRONIZATION
where Gm value for VIPer50/50A is 1.5 mA/V
typically. The OSC pin provides a synchronisation
capability, when connected to an external
Gmis well defined by specification, but ZCOMP and frequency source. Figure 20 shows one possible
therefore AVOL are subject to large tolerances. An schematic to be adapted depending on the
impedance Z can be connected between the specific needs. If the proposed schematic is used,
COMP pin and ground in order to define more the pulse duration must be kept at a low value
accurately the transfer function F of the error (500ns is sufficient) for minimizing consumption.
amplifier, according to the following equation, very The optocoupler must be able to provide 20mA
similar to the one above: through the optotransistor.
F(S) = Gm x Z(S)
The error amplifier frequency response is reported PRIMARY PEAK CURRENT LIMITATION
in figure 10 for different values of a simple
resistance connected on the COMP pin. The The primary IDPEAK current and, as resulting
unloaded transconductance error amplifier shows effect, the output power can be limited using the
an internal ZCOMP of about 330 KΩ. More complex simple circuit shown in figure 21. The circuit based
impedance can be connected on the COMP pin to on Q1, R1 and R2 clamps the voltage on the

Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down

D2

D3
VIPer50
R1 VIPer50
VDD DRAIN
- VDD DRAIN
OSC
R3 Q2 -
13V + OSC
COMP SOURCE 13V +
D1 COMP SOURCE
AUXILIARY
WINDING R3 R2
C4 R1
R2 R4
+ C3 C1 + C2 Shutdown Q1 D1

FC00331 FC00340

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 VIPer50/SP - VIPer50A/ASP

COMP pin in order to limit the primary peak current OVER-TEMPERATURE PROTECTION:
of the device to a value: Over-temperature protection is based on chip
V – 0.5 temperature sensing. The minimum junction
COMP
IDPEAK = ------------------------------------- temperature at which over-temperature cut-out
H ID occurs is 140ºC while the typical value is 170ºC.
The device is automatically restarted when the
where: junction temperature decreases to the restart
R1 + R2 temperature threshold that is typically 40ºC below
V COMP = 0.6 × ---------------------- the shutdown value (see figure 8).
R2

The suggested value for R1+R2 is in the range of

220KΩ.

Figure 18: Typical Compensation Network Figure 19: Slope Compensation

VIPer50
VDD DRAIN R2 R1
- V IP er50
OSC
VD D DRAIN
13V +
COMP SOURCE -
O SC
13V +
COM P SO U RCE

C2 R1 C2

C1 Q1 C3

C1 R3

FC00351
FC 00361

Figure 20: External Clock Synchronization Figure 21: Current Limitation Circuit Example

VIPer50
VDD DRAIN
-
OSC
13V +
VIPer50
COMP SOURCE
VDD DRAIN
-
OSC
13V +
COMP SOURCE R1
10 kΩ
Q1

R2

FC00370

FC00380

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 VIPer50/SP - VIPer50A/ASP

Figure 22: Input Voltage Surges Protection

R1 D1

(Optional)
R2
39R
Auxilliary winding

VDD DRAIN
C2
C1 -
OSC
Bulk capacitor 22nF 13V +
VIPerXX0 COMP SOURCE

ELECTRICAL OVER STRESS RUGGEDNESS

The VIPer may be submitted to electrical over can overpass the VDD pin absolute maximum
stress caused by violent input voltage surges or rating voltage value. Such events may trigger the
lightning. Following the enclosed Layout VDD internal protection circuitry which could be
Considerations chapter rules is the most of the damaged by the strong discharge current of the
time sufficient to prevent catastrophic damages, VDD bulk capacitor. The simple RC filter shown in
however in some cases the voltage surges figure 22 can be implemented to improve the
coupled through the transformer auxiliary winding application immunity to such surges.

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 VIPer50/SP - VIPer50A/ASP

Figure 23: Recommended Layout

T1
D1

7RVHFRQGDU\
C7
D2 ILOWHULQJDQGORDG

R1 2 3
VDD DRAIN

C1 -
1 OSC C5
13V +
)URPLQSXW
COMP SOURCE
GLRGHVEULGJH
5 4
U1
VIPerXX0

R2 C6

C2
C3

ISO1
C4

FC00500

LAYOUT CONSIDERATIONS - To use different tracks for low level signals and
Some simple rules insure a correct running of power ones. The interferences due to a mixing
switching power supplies. They may be classified of signal and power may result in instabilities
into two categories: and/or anomalous behavior of the device in
- To minimize power loops: the way the switched case of violent power surge (Input overvoltages,
power current must be carefully analyzed and output short circuits...).
the corresponding paths must present the In case of VIPer, these rules apply as shown in
smallest possible inner loop area. This avoids figure 23. The loops C1-T1-U1, C5-D2-T1, C7-D1-
radiated EMC noises, conducted EMC noises T1 must be minimized. C6 must be as close as
by magnetic coupling, and provides a better possible to T1. The signal components C2, ISO1,
efficiency by eliminating parasitic inductances, C3 and C4 use a dedicated track to be connected
especially on secondary side. directly to the source of the device.

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 VIPer50/SP - VIPer50A/ASP

PowerSO-10™ MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A (*) 3.4 3.6 0.134 0.142
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
B (*) 0.37 0.53 0.014 0.021
C 0.35 0.55 0.013 0.022
C (*) 0.23 0.32 0.009 0.0126
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
E 9.30 9.50 0.366 0.374
E2 7.20 7.60 0.283 300
E2 (*) 7.30 7.50 0.287 0.295
E4 5.90 6.10 0.232 0.240
E4 (*) 5.90 6.30 0.232 0.248
e 1.27 0.050
F 1.25 1.35 0.049 0.053
F (*) 1.20 1.40 0.047 0.055
H 13.80 14.40 0.543 0.567
H (*) 13.85 14.35 0.545 0.565
h 0.50 0.002
L 1.20 1.80 0.047 0.070
L (*) 0.80 1.10 0.031 0.043
α 0º 8º 0º 8º
α (*) 2º 8º 2º 8º
(*) Muar only POA P013P

0.10 A B
10

H E E2 E4

1
SEATING
PLANE

e B DETAIL "A" A

0.25 C

D
h = D1 =
= =
SEATING
PLANE
A
F
A1 A1

L
DETAIL "A"
P095A
α

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 VIPer50/SP - VIPer50A/ASP

PENTAWATT HV MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.11
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 15.60 17.30 6.14 0.681
L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 4.50 5.60 0.177 0.220
R 0.50 0.02
V4 90° (typ)
Diam 3.65 3.85 0.144 0.152

P023H3

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1
 VIPer50/SP - VIPer50A/ASP

PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 5.00 5.70 0.197 0.224
R 0.50 0.020
V4 90° 90°
Diam. 3.70 3.90 0.146 0.154
L
L1
E
M1

A
M

C
R
leads
Resin between

L6

L7
V4
G2

G1

H1
H3

H2
F

DIA
L3

L5

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1
 VIPer50/SP - VIPer50A/ASP

PowerSO-10™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix)

14.6 - 14.9
B CASABLANCA MUAR
10.8- 11
C
6.30

A C
A

0.67 - 0.73
B
1 10 0.54 - 0.6
2 9
9.5 3 8 All dimensions are in mm.
4 7 1.27
5 6 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8

TAPE AND REEL SHIPMENT (suffix “13TR”)

REEL DIMENSIONS
Base Q.ty 600
Bulk Q.ty 600
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4

All dimensions are in mm.

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

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1
VIPer50/SP - VIPer50A/ASP

PENTAWATT HV TUBE SHIPMENT (no suffix)

Base Q.ty 50
Bulk Q.ty 1000
B Tube length (± 0.5) 532
A 18
B 33.1
C (± 0.1) 1
C
All dimensions are in mm.

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1
VIPer50/SP - VIPer50A/ASP

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of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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