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Biasing PDF

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LTSPICE

2/5/2018 1
LTSPICE
 Biasing Schemes

2/5/2018 2
Recap
 Common Source(CS) Configuration
 Transfer Characterstics in Common Source(CS)
Configuration

2/5/2018 3
I-V Characterstics of common Source
amplifer

iD

C
B

Load Line
Q
vGS= vIQ
Slope of
Load Line ?
A

2/5/2018 vDS = vo
Transfer Characterstics of common Source amplifer

XA :Cut off AB: Saturation

iD

VDD

BC:Triode
VDD =VDSQ Region

VOB

VOC
BIASING in MOS Amplifier Circuits

• An operating point appropriate dc or bias point is


characterized by a stable and predictable dc current
ID and by a dc drain to source voltage VDS that ensures
operation in the saturation region for all expected
input signal levels

2/5/2018 6
Biasing in MOS Amplifier Circuits

•The first step for an amplifier design  Biasing Design


•For a MOSFET  keep it in saturation region

Bias Methodologies:

1. Fixing VGS;
2. Fixing VG and a degenerated resistor;
3. Using a Drain-to-Gate feedback Resistor;
4. Using a constant current source.
BIASING by Fixing VGS

• Fix VGS to the value required to provide desired


I D.
• Can be achieved by using an voltage divider.

Voltage Q
divider

2/5/2018 8
BIASING by Fixing VGS

• Threshold voltage , oxide capacitance and transistor


aspect ratio vary widely among devices of the same
size and type in case of discrete devices.

2/5/2018 9
Temperature Effects

2/5/2018 10
BIASING by Fixing VGS

Fixing V is not a good technique.


GS

2/5/2018 11
I-V curves with only fixing bias

•Assumed that device #1 and


device #2 are with different I-V
characteristics due to process
variation.
BIASING by Fixing VG and connecting
a resistance in the source

• A better bias methodology

Connecting a resistance in the source ,RS


2/5/2018 13
BIASING by Fixing VG and connecting
a resistance in the source

VG is constant

I D VGS

ID
2/5/2018 14
BIASING by Fixing VG and connecting
a resistance in the source

• The action of Resistance ,RS is to keep the


value of bias I as constant current as possible
D

• Resistance ,R - Source degeneration Resistor


S

• Resistance ,R provides a S

negative feedback which


acts to stabilize the value
of bias current ID .

2/5/2018 15
Biasing
Chapter 4
by Fixing V and Connecting
MOS field-Effect Transistors (MOSFETs)
GS
Figure 4.30
Resistance in the source

FIGURE 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a)
basic arrangement; (b) reduced variability in ID
Coupling of a Signal Source to
the gate using a capacitor CC1

Gain conversion! Coupling cap.

Signal to be
amplified (ac input)
Practical implementation using single and
two supplies

FIGURE 4.30 (c) practical implementation using a single supply (e) practical implementation using two
supplies.
Biasing MOSFET using large drain to gate
feedback resistor RG

•Resistor RG is of high value

•RG ensures the MOSFET in


saturation (VGS = VDS)

•A single power supply is needed.


Biasing using a Drain-to-Gate Feedback Resistor

•Negative feedback
mechanism
Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.

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