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Application Note: September 19, 2016 - Rev. 2 1 AN004E/D
Application Note: September 19, 2016 - Rev. 2 1 AN004E/D
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APPLICATION NOTE
Specifications subject to change without notice. • • 2016 Littelfuse, Inc. 1 Publication Order Number:
September 19, 2016 - Rev. 2 AN004E/D
AN004E/D
di/dt
As the gate region of the SCR is driven on, its area of
Figure 2.
conduction takes a finite amount of time to grow, starting
as a very small region and gradually spreading. Since the
anode current flows through this turned–on gate region,
very high current densities can occur in the gate region if
high anode currents appear quickly (di/dt). This can result
in immediate destruction of the SCR or gradual
degradation of its forward blocking voltage capabilities –
depending on the severity of the occasion.
–
VIN VOUT
+
DC
OV
Power COUT Sense
Supply
Figure 4.
Specifications subject to change without notice. 2016 Littelfuse, Inc. Publication Order Number:
2
September 19, 2016 - Rev. 2 AN004E/D
AN004E/D
VCC
Isource
4
Current Source
2
Vsense1 – +
+ –
VREF
2.6 V 8
+
Output
–
Figure 8.
The first comparator is designed to initiate a stable time The minimum value of the gate current limiting resistor,
delay and the second one activates both a crowbar firing RG, is given in Figure 11. Using this value of RG the SCR
current and a low level indication signal. Q1 will receive the greatest gate current possible without
damaging the MC3423. If lower output currents are
The Basic Circuit required, RG can be increased in value.
The basic circuit configuration of the OVP is shown in
Figure 9. In this circuit, the voltage sensing inputs of both THE PROGRAMMATION
the internal amplifiers are tied together for sensing the
overvoltage condition. The shortest possible propagation Low Voltage < 36 V
delay is thus obtained. In many instances, the MC3423 will be used in a noise
The threshold on trip voltage at which the MC3423 will environment. To prevent false tripping of the OVP circuit
trigger and supply gate drive to the crowbar SCR, Q1, is by noise which would not normally harm the load, the
determined by the selection of R1 and R2. Their values can MC3423 has a programmable delay feature. To implement
be determined by the equation (1): this feature, the circuit configuration of Figure 12 is used.
R1 R1 In this configuration, a capacitor is connected from pin 3 to
Vtrip VREF 1 2.6 V 1 (1)
R2 R2 VEE. The value of this capacitor determines the minimum
duration of the overvoltage condition which is necessary to
R2 ≤ kΩ for minimum drift.
trip the OVP. The value of C can be found from Figure 13.
Figure 10 shows (with R2 = 2.7 kΩ) the value (min, typ,
The circuit operates in the following manner: when VCC
max) of R1 versus trip voltage.
rises above the trip point set by R1 and R2, an internal
The switch S1, shown in Figure 9, may be used to reset
current source (pin 4) begins charging the capacitor, C,
the SCR crowbar. Otherwise, the power supply, across
connected to pin 3. If the overvoltage condition disappears
which the SCR is connected, must be shut down to reset the
before this occurs, the capacitor is discharged at a rate 10
crowbar. If a non–current–limited supply is used, a fuse or
times faster than the charging rate, resetting the timing
circuit breaker, F1, should be used to protect the SCR
feature until the next overvoltage condition occurs.
and/or the load.
+ 35
F1 (+ Sense
Lead) RG(min) = 0
30
VCC, Supply Voltage (V)
R1 1 Q1 if VCC < 11 V
Power 2 8
Supply 3 MC3423 To
25
RG
R2 Load
4 7 5
20
S1
(– Sense Lead) 15
–
10
Figure 9. 0 10 20 30 40 50 60 70 80
RG, Gate Current Limiting Resistor (Ω)
30
Max
Figure 11.
R2 = 2.7 k Typ
+VCC
R1, Resistance (kΩ)
20
R3
Min R1 V10
1 6
Indication
2N6504 or
10
Power 2 MC3423 8 Out
Supply equivalent
RG
4 3 5 7
R2 VO
0 VC C Vtrip
0 5.0 10 15 20 25 30 R3 ≥
10 mA
VT, Trip Voltage (V)
Figure 10.
Figure 12.
1.0 +
(+ Sense
RS Lead)
0.1
R1
Capacitance (μF)
1 Q1
8
0.01 2 To
Power Load
MC3423 3
Supply
4 VS
0.001 7 5 R2
1N4740 (– Sense
+ 10 μF
10 V Lead)
15 V
0.0001 –
0.001 0.01 0.1 1.0 10
td, Delay Time (ms) Figure 14.
Figure 13.
VCC
Occasionally, it is desired that immediate crowbarring of Vtrip
the supply occurs when a high overvoltage condition
occurs, while retaining the false tripping immunity of 0
Figure 12.
VC
VREF
High Voltage 36 V < V < 800 V
Figure 14 is a typical application for voltage protection
0
over 36 V, using a Zener diode 1N4740 (10 V) and a 10 μF
(15 V) capacitor at the positive sense lead. VO
The value of RS can be calculated with the following
formula (2):
0
(VS 10) td
RS k (2)
25 VIO
The V trip is given by the formula (1).
Following the choice of the SCR (Q1), the protection can
be done up to 800 V: Figure 15.
VS ≤ 50 V: 2N6504 or equivalent
VS ≤ 100 V: 2N6505 or equivalent Using Figure 13 (C value) and Figure 15, td is equal to:
VS ≤ 200 V: 2N6506 or equivalent VREF
td C (12.103) C (3)
VS ≤ 400 V: 2N6507 or equivalent Isource
VS ≤ 600 V: 2N6508 or equivalent
VS ≤ 800 V: 2N6509 or equivalent Remote Activation Input
On this configuration (Figure 14) the typical propagation Another feature of the MC3423 is its remote activation
delay is 1.0 μs. If faster operation is desired, pin 3 may be input, pin 5. If the voltage on this CMOS/TTL compatible
connected to pin 2 with pin 4 left floating. This will result in input is held below 0.8 V, the MC3423 operates normally.
decreasing the propagation delay to approximately 0.5 μs at However, if it is raised to a voltage above 2.0 V, the OVP
the expense of a slightly increased TC for the trip voltage output is activated independent of whether or not an
value. overvoltage condition is present. It should be noted that pin
5 has an internal pull–up current source. This feature can
THE ADDITIONAL FEATURES be used to accomplish an orderly and sequenced shut–down
Activation Indication Output of system power supplies during a system fault condition.
An additional output for use as an indication of OVP In addition, the activation indication output of one
activation is provided by the MC3423. This output is an MC3423 can be used to activate another MC3423 if a single
open collector transistor which saturates when the OVP is transistor inverter is used to interface the former’s
activated. It will remain in a saturated state until the SCR indication output to the latter’s remote activation input, as
crowbar pulls the supply voltage, VCC, below 4.5 V as in shown in Figure 16. In this circuit, the indication output
Figures 12 and 15. This output can be used to clock an edge (pin 6) of the MC3423 on power supply 1 is used to activate
triggered flip–flop whose output inhibits or shuts down the the MC3423 associated with power supply 2. Q1 is any
power supply when the OVP trips. This reduces or eliminates small PNP with adequate voltage rating.
the heat–sinking requirements for the crowbar SCR.
VEE
+
+ + +
CHANNEL
ONE – – –
+ –
– + DRIVE 1
0.9 VREF
INDICATION
OUT 1
1.4 V
ENABLE –
+
+
1.4 V + – +
VREF 2.5 V
–
+ +
CHANNEL
TWO +
– –
DRIVE 2
INDICATION
OUT 2
REMOTE REMOTE
DELAY 1 DELAY 2 VEE
ACTIVATION 1 ACTIVATION 2
VCC
+ +
OVER
VOLTAGE +
SENSE +
–
DRIVE
2.5 V +
+
UNDER
INDICATION
VOLTAGE –
OUT
SENSE
A look at Figure 17 (MC3424) shows two channels of Figure 18 (MC3425) shows a low cost OUVP version: 8
uncommitted differential inputs with a common mode pins dual in line instead of 14 pins for the MC3424.
range from ground (VEE) to VCC+, for maximum A typical application is shown in Figure 19. Following
flexibility. This circuit has an externally programmable the trip voltage required, the value of resistors RS and RB
hysteresis. However, the output is very stable (TC < will be selected following the formula [see formula (1)]:
0.01%/°C), due mainly to its band gap reference voltage RS RS
circuit: 2.5 V at 10 mA. Vtrip VREF 1 2.6 V 1
RB RB
The two independent drive outputs are capable of
To prevent a minimum drift of the circuit, RB value
sourcing 300 mA at a slew rate of 200 to 400 mA/μs.
should be around 10 kα and
The two indicators are capable of sinking 300 mA.
The enable input (CMOS, TTL, DTL compatible) RE T
VS
control of either channel 2 or both channels depending on CELn VS VE
channel 1 input conditions. 200 A Td
Is Td
Each channel can be operated closed loop with gain or CD
VREF 2.5 V
unity gain, stabilized at the delay pin.
VS
+
F1
RS1 RS2 R
VCC
R1
Q1 Q2
Power OVER
Supply DRIVE To
Crowbar Indicate
UNDER RG Load
Over Under
RR1 RR2 ENABLE Voltage Voltage
IND.
C1 VEE DELAY
CD
–
Figure 19.
Littelfuse products are not designed for, and shall not be used for, any purpose (including, without limitation, automotive, military,
aerospace, medical, life-saving, life-sustaining, nuclear facility applications, devices intended for surgical implant into the body, or any
other application in which the failure or lack of desired operation of the product may result in personal injury, death, or property
damage) other than those expressly set forth in applicable Littelfuse product documentation. Warranties granted by Littelfuse shall be
deemed void for products used for any purpose not expressly set forth in applicable Littelfuse documentation. Littelfuse shall not be
liable for any claims or damages arising out of products used in applications not expressly intended by Littelfuse as set forth in
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unless otherwise agreed by Littelfuse.