FET Amplifier

Course-Section : ECE20L-2 / E06

Name : DE LEMOS, NICHOLAS LOUIS N.

Signature :

Date : JULY 28, 2022

Course Instructor : LEONARDO VALIENTE

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 VGG

EECE VDD

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Figure 1.1. Circuit Board of JFET Device.

Part 1: Characteristics of Junction Field Effect Transistor (JFET) Device

Schematic Diagram:

1.1 Draw in LTSPICE the schematic diagram of JFET circuit shown in Figure 1.1. The terminals
of JFET (Q1) are drain (D), gate (G), and source (S). Use the following components in the
circuit: VGG (dc voltage source at gate circuit), R1 (gate resistor), Q1, R2 (source resistor),
R3 (drain resistor), and VDD (dc voltage source at drain circuit). Do not connect in the circuit
the CR1 (crystal rectifier) and GEN (signal generator). The student or group should use
different their own component values for the dc voltage sources (VGG, VDD), resistors (R1,
R2, R3), and JFET (Q1).

Here is a link about ‘Getting Started with LTSPICE’:

https://learn.sparkfun.com/tutorials/getting-started-with-ltspice/all

1.2 Take the photo of your circuit diagram drawn in LTSPICE tool, and place it as Figure 1.2.

One way to capture the screen in LTSPICE is: View > Paste Bitmap.

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 Figure 1.2. Schematic Diagram of JFET circuit using LTSPICE Tool.

ID-VGS Characteristic Curve:

1.3 Set the VDD to a certain value. Sweep the value of VGG. Run a DC simulation in LTSPICE,
and plot the gate-to-source voltage (VGS) of JFET Q1 in x-axis and the drain current (ID) of
JFET Q1 in y-axis. Take a snapshot of the simulation results, and place it as Figure 1.3.

Figure 1.3. ID-VGS Characteristics of JFET.

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1.4 Record the details of simulation.

Part number of JFET =J111

VDD = 12V
VDS = 10V (Drain-to-source voltage)
VGG(minimum) = 0V
VGG(maximum) = 10V
VGS(minimum) = 0V
VGS(maximum) = 10V
ID(minimum) = 371.23667µA
ID(maximum) = 1.1356534mA

1.5 Based on the ID-VGS graph in Figure 1.3, briefly describe the effect of input gate-to-source
voltage (VGS) on the output drain current (ID), or the transfer characteristics, of JEFT device.
I was able to notice that in a reverse bias that is applied to the diode will decrease the both sides of the PN junction that

extends to the JFET channel, a region that allows current to flow between the source and the drain . Depending on the

input value of the voltage, the current that will flow is limited because the value of VGS is zero then the amount of current

flow is restricted.

ID-VDS Characteristic Curve:

1.6 Set the VGG to a certain value. Sweep the value of VDD. Run a DC simulation in LTSPICE,
and plot the drain-to-source voltage (VDS) of JFET Q1 in x-axis and the drain current (ID) of
JFET Q1 in y-axis. Take a snapshot of the simulation results, and place it as Figure 1.4.

Figure 1.4. ID-VDS Characteristics of JFET.

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1.7 Record the details of simulation.

Part number of JFET = J111

VGG = 12V
VGS = 10V
VDD(minimum) = 0V
VDD(maximum) = 10V
VDS(minimum) = 0V
VDS(maximum) = 10V
ID(minimum) = 15.480736pA
ID(maximum) = 27.068934pA

1.8 Based on the ID-VDS graph in Figure 1.4, briefly describe the output characteristics of JEFT
device.
The ID meet its maximum value and does not retain the same value as shown in the figure 1.4. The drain

current saturates while the VDS increases and does not change in Thh ID.

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 VDD

EECE
of
Figure 2.1. Circuit Board of JFET Amplifier.

Part 2: JFET Amplifier

Schematic Diagram:

2.1 Draw in LTSPICE the schematic diagram of JFET Amplifier shown in Figure 2.1. The student
or group should use different their own component values for input sine wave generator GEN,
gate resistor R1, source resistor R2, drain resistor R3, input coupling capacitor C1, bypass
capacitor C2, transistor Q1, and dc supply VDD.

Here is a link about ‘LTSPICE: Simple Steps for Simulating Transformers’:

https://www.analog.com/en/technical-articles/ltspice-basic-steps-for-simulating-transformers.html

2.2 Take the photo of your circuit diagram drawn in LTSPICE tool, and place it as Figure 2.2.

One way to capture the screen in LTSPICE is: View > Paste Bitmap.

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 Figure 2.2. Schematic Diagram of JFET Amplifier using LTSPICE Tool.

DC Operating Condition:

2.3 Run a .OP simulation in LTSPICE, and determine the terminal voltages of transistors at dc
supply VDD voltage.

Terminal Voltages of Transistor Q1: Note: The given JFET is n-channel type.
VG = 24.288µV The drain and source regions
VD = 24.100V are both n-type layer, while
VS = 167.844mV the gate region is p-type layer.

2.4 Based on the measured terminal voltages, identify the bias condition of gate-source junction
of transistor Q1. Briefly explain you answer.
As VG<VS, the gate-source junction of transistor Q1 is in reverse bias, indicating that VGS<0.0. The depletion area
functions as if the negative-biased VGS effect is applied, as if VGS = 0V, but the VDS values are lowered.

2.5 Based on the measured terminal voltages, identify the bias condition of gate-drain junction of
transistor Q1. Briefly explain you answer.
Since VG<VD, the gate-drain junction of transistor Q1 has a reverse bias, allowing VGD<0.0. This now creates a
greater region of depletion sufficient to compensate for the rise in VDS, keeping ID constant at some stage.

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2.6 Based on the measured terminal voltages, identify the operating condition of transistor Q1.
Briefly explain you answer.
Based on the experiment, the operating condition for transistor Q1 is a very small amount of voltage from G to be
able to operate to have the predicted results where having VDD would provide for the output.

2.7 Take a snapshot of DC simulation waveforms, and place it in Figure 2.3.

Figure 2.3. DC Simulation of JFET Amplifier using LTSPICE Tool.

AC Operation:

2.8 Run transient simulations in LTSPICE. Adjust the amplitude of input sine wave generator
voltage and rerun the transient simulation until the voltage at the drain of Q1 becomes
undistorted. Determine the maximum amplitude of its input voltage that will result to an
undistorted output voltage.

Vin =-988.182mV
Vo(undistorted) = 23.162V

2.9 Based on the measured input and output voltages, calculate the amplification in terms of
voltage gain.

Av = -23.4397

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2.10 Take a snapshot of Transient simulation waveforms, and place it in Figure 2.4.

Figure 2.4. Transient Simulation of JFET Amplifier using LTSPICE Tool.

2.11 Based on the simulation results, explain the operation of JFET Amplifier.
A JFET amplifier is an amplifier that utilizes a junction field effect transistor to put out a high input impedance.
With the given results obtained by the group, a JFET amplifier operates as a unipolar transistor that can be
applied to control noise, buffer currents, and as a chopper.

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