Mamba: HI-6138: General Description

MAMBATM: HI-6138
3.3V BC / MT / RT MIL-STD-1553 / MIL-STD-1760

August, 2021 Compact Multi-Terminal Device with SPI Host Interface
GENERAL DESCRIPTION • 64-Word Interrupt Log Buffer queues the most

recent 32 interrupts. Hardware-assisted interrupt
The 3.3V CMOS HI-6138 device is a member of decoding quickly identifies interrupt sources.
Holt’s MIL-STD-1553 MAMBATM family and provides • Built-in self-test for protocol logic, digital signal
a complete single or multi-function interface between paths and internal RAM.
a host processor and MIL-STD-1553B bus. Each IC
• Optional self-initialization at reset uses external
contains a Bus Controller (BC), a Bus Monitor Terminal
serial EEPROM.
(MT) and a Remote Terminal (RT). Any combination of the
contained 1553 functions can be enabed for concurrent • ±8kV ESD Protection (HBM, all pins).
o o
operation. The enabled terminals communicate with the • Two temperature ranges: -40 C to +85 C, or
o o
MIL-STD-1553 buses through a shared on-chip dual -55 C to +125 C with optional burn-in.
bus transceiver and external transformers. The user • RoHS compliant and Tin / Lead options available.
allocates 16K bytes of on-chip static RAM between
devices to suit application requirements. PIN CONFIGURATION (TOP)
The HI-6138 communicates with the host via a 40 MHz
4-wire serial peripheral interface (SPI). Programmable
39 - MTSTOFF
48 - BCTRIG
37 - RTMC8
interrupts provide terminal status to the host processor.
47 - BENDI
41 - VCCP
44 - VCCP
40 - BUSB
42 - BUSB
43 - BUSA
45 - BUSA
38 - EE2K
46 - TEST
Circular data buffers in RAM have interrupts for rollover
and programmable “level attained”.
The HI-6138 can be configured for automatic self- MODE - 1 36 - TTCLK

IRQ - 2 35 - ESCLK
initialization after reset. A dedicated SPI port reads ACKIRQ - 3 34 - EECOPY
data from an external serial EEPROM to fully configure MODE1760 - 4 33 - ECS
READY - 5 HI-6138PCIF 32 - MOSI
registers and RAM and optionally start execution for any VCC - 6 HI-6138PCTF 31 - VCC
subset of one to three terminal devices. GND - 7 30 - GND
ACTIVE - 8 HI-6138PCMF 29 - MISO
RTSSF - 9 28 - MTTCLK
AUTOEN - 10 27 - LOCK
FEATURES TXINHA - 11 26 - RTA4
25 - RTA3
TXINHB - 12
• Concurrent multi-terminal operation for one to
three MIL-STD-1553B functions: BC, MT and/or
RTAP - 13
RTA0 - 14
CE - 15
VCC - 16
SCK - 17
SO - 18
SI - 19
GND - 20
MCLK - 21
RTA1 - 22
MR - 23
RTA2 - 24
RT.
• 8K x 17-bit words internal static RAM with parity
• Autonomous terminal operation requires minimal 48 - Pin Plastic 6mm x 6mm
host intervention. Chip-Scale Package (QFN)
• 40 MHz SPI Host Interface.
• MIL-STD-1760 option sets Busy bit in Status See Section 26.1 on page 256 for 48-Pin PQFP Configuration
Word response during initialization.
• World’s smallest MIL-STD-1553 terminal, QFN
package measures just 6mm x 6mm.
• Fully programmable Bus Controller with 28 op
code instruction set.
• Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
• Independent 16-bit time tag counters and clock
sources for all modes. The Bus Controller and
Monitor also have 32- and 48-bit time count
options, respectively.
HOLT INTEGRATED CIRCUITS
DS6138 Rev. Q www.holtic.com 08/21
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NOTES:

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Table of Contents
1. BLOCK DIAGRAM........................................................................................... 14
2. FEATURE OVERVIEW ................................................................................... 15
2.1. Bus Controller Operation........................................................................................... 15
2.2. Remote Terminal Operation....................................................................................... 15
2.3. Monitor Terminal Operation........................................................................................ 15
2.4. Interrupts.................................................................................................................... 15
2.5. Reset and Initialization............................................................................................... 15
3. PIN DESCRIPTIONS...................................................................................... 16
4. MEMORY MAP................................................................................................ 19
5. RAM STRUCTURES ...................................................................................... 20
5.1. Interrupt Log Data Buffer........................................................................................... 20
5.2. Bus Controller (BC) Instruction List............................................................................ 20
5.3. Bus Controller (BC) Msg Control / Status Stack........................................................ 20
5.4. Bus Controller (BC) Call Stack................................................................................... 20
5.5. Bus Controller (BC) General Purpose Queue............................................................ 20
5.6. Monitor Terminal Temporary Buffers A & B................................................................ 20
5.7. Monitor Terminal (MT) Address List........................................................................... 20
5.8. Monitor Terminal (MT) Message Filter Table.............................................................. 21
5.9. Monitor Terminal (MT) Data Buffers........................................................................... 21
5.10. RT Command Illegalization Table.............................................................................. 21
5.11. RT Descriptor Table................................................................................................... 21
5.12. RT Temporary Receive Buffer.................................................................................... 21
5.13. RT Message Data Buffers.......................................................................................... 21
5.14. RT Storage for Mode Code Commands..................................................................... 21
6. HARDWARE FEATURES ............................................................................... 22

6.1. Remote Terminal Address Inputs............................................................................... 22
6.2. Dual Transceivers for MIL-STD-1553 Bus................................................................. 22
6.3. Encoder and Decoders.............................................................................................. 22
6.4. Auto-Initialization Serial EEPROM Interface.............................................................. 22
6.5. Transmit Time-out Fail-Safe Counter......................................................................... 22

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6.6. MIL-STD-1760 Mode................................................................................................. 22
7. REGISTER & MEMORY ADDRESSING........................................................ 23

8. REGISTER DEFINITIONS.............................................................................. 23
9. REGISTERS USED BY ALL DEVICE FUNCTIONS..................................... 28
9.1. Master Configuration Register 1 (0x0000)................................................................. 28
9.2. Master Configuration Register 2 (0x004E) ................................................................ 31
9.3. Master Status and Reset Register (0x0001) ............................................................. 33
9.4. Overview of Interrupts................................................................................................ 35
9.5. Hardware Interrupt Behavior...................................................................................... 36
9.6. Interrupt Count & Log Address Register (0x000A) .................................................... 37
9.7. Interrupt Log Buffer.................................................................................................... 37
9.8. Hardware Interrupt Registers..................................................................................... 41
9.8.1. Hardware Interrupt Enable Register (0x000F) ....................................................... 41
9.8.2. Hardware Pending Interrupt Register (0x0006) ..................................................... 41
9.8.3. Hardware Interrupt Output Enable Register (0x0013) ........................................... 41
9.9. Extended Configuration Register (0x004D)............................................................... 44
9.10. Time Tag Counter Configuration................................................................................ 47
9.11. Time Tag Counter Configuration Register (0x0039)................................................... 48
9.12. Memory Address Pointer Registers........................................................................... 52
10. BUS CONTROLLER − CONFIGURATION AND OPERATION.................... 54

10.1. Bus Controller Condition Codes................................................................................. 55
10.2. Bus Controller Instruction Op Codes......................................................................... 58
10.3. Bus Controller General Purpose Queue.................................................................... 67
10.4. Bus Controller Message Control / Status Blocks....................................................... 67
10.4.1. BC Control Word.................................................................................................... 68
10.4.2. Time to Next Message Word.................................................................................. 73
10.4.3. Data Block Pointer.................................................................................................. 73
10.4.4. BC Block Status Word............................................................................................ 74
11. BUS CONTROLLER REGISTER DESCRIPTION ....................................... 78

11.1. BC (Bus Controller) Configuration Register (0x0032)................................................ 78
11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033).................. 87
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)................................................ 87
11.4. Bus Controller (BC) Last Message Block Address (0x004F)..................................... 87

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11.5. Bus Controller (BC) Frame Time Remaining Register (0x0035)................................ 88

11.6. Bus Controller (BC) Time To Next Message Register (0x0036)................................. 88
11.7. Bus Controller (BC) Condition Code Register (Read 0x0037)................................... 88
11.8. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)......................... 91
11.9. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038).................. 91
11.10. Bus Controller (BC) Time Tag Counter (0x0043)....................................................... 92
11.11. Bus Controller (BC) Time Tag Counter High (0x0044)............................................... 92
11.12. Bus Controller (BC) Time Tag Utility Register (0x0045) ............................................ 93
11.13. Bus Controller (BC) Time Tag Utility High Register (0x0046) ................................... 93
11.14. Bus Controller (BC) Time Tag Match Register (0x0047) ........................................... 93
11.15. Bus Controller (BC) Time Tag Match High Register (0x0048) .................................. 93
11.16. Bus Controller Interrupt Registers and Their Use...................................................... 94
11.16.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ....................................... 95
11.16.2. Bus Controller (BC) Pending Interrupt Register (0x0007) ..................................... 95
11.16.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) ........................... 95
12. SIMPLE MONITOR TERMINAL (SMT).......................................................... 98

12.1. Overview.................................................................................................................... 98
12.2. SMT Block Status Word (BSW) Description............................................................ 103
12.3. SMT Message Filter Table....................................................................................... 106
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION......... 108

13.1. SMT Configuration Register (0x0029)..................................................................... 108
13.2. SMT Bus Monitor Address List Start Address Register (0x002F).............................111
13.3. SMT Next Message Command Buffer Address (0x0030).........................................111
13.4. SMT Last Message Command Buffer Address (0x0031)......................................... 112
13.5. SMT Bus Monitor Time Tag Count Register (0x003A)............................................. 112
13.6. SMT Bus Monitor Time Tag Count Mid Register (0x003B)...................................... 112
13.7. SMT Bus Monitor Time Tag Count High Register (0x003C)..................................... 112
13.8. SMT Bus Monitor Time Tag Utility Register (0x003D).............................................. 113
13.9. SMT Bus Monitor Time Tag Utility Mid Register (0x003E)....................................... 113
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F)...................................... 113
13.11. SMT Bus Monitor Time Tag Match Register (0x0040)............................................. 114
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041) ...................................... 114
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042) .................................... 114
13.14. SMT Bus Monitor Interrupt Registers and Their Use............................................... 115

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13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011).......................................... 116

13.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008)........................................ 116
13.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015).............................. 116
14. REMOTE TERMINAL − OVERVIEW ............................................................118

15. REMOTE TERMINAL REGISTERS..............................................................119
15.1. Remote Terminal Configuration Register (0x0017) ................................................. 119
15.2. Remote Terminal Operational Status Register (0x0018) ........................................ 125
15.3. Remote Terminal Current Command Register (0x0002).......................................... 127
15.4. Remote Terminal Current Control Word Address Register (0x0003) ...................... 127
15.5. Remote Terminal Descriptor Table Base Address Register (0x0019)...................... 127
15.6. Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A).................... 128
15.7. Remote Terminal Current Message Information Word Register (0x001B)............... 129
15.8. Remote Terminal Bus A Select Register (0x001C).................................................. 130
15.9. Remote Terminal Bus B Select Register (0x001D).................................................. 130
15.10. Remote Terminal Built-In Test (BIT) Word Register (0x001E).................................. 131
15.11. Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)................... 132
15.12. Remote Terminal Time Tag Counter Register (0x0049)........................................... 132
15.13. Remote Terminal Time Tag Utility Register (0x004A)............................................... 133
15.13.1. RT Time Tag Counter Loading ............................................................................. 133
15.13.2. RT Time Tag Count Match Interrupts ................................................................... 133
15.14. Remote Terminal Interrupt Registers and Their Use................................................ 134
15.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012).................................. 135
15.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009)................................ 135
15.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016)...................... 135
16. REMOTE TERMINAL CONFIGURATION AND OPERATION.................... 138

16.1. Command Responses............................................................................................. 138
16.1.1. RT to RT Commands. .......................................................................................... 140
16.2. Command Illegalization Table.................................................................................. 140
16.3. Temporary Receive Data Buffer............................................................................... 145
16.4. Descriptor Table....................................................................................................... 145
16.4.1. Receive Subaddress Control Word...................................................................... 148
16.4.2. Transmit Subaddress Control Word..................................................................... 151
16.4.3. Data Buffer Options for Mode Code Commands.................................................. 154
16.4.4. Receive Mode Control Word................................................................................ 155

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HI-6138
16.4.5. Transmit Mode Control Word................................................................................ 158
17. REMOTE TERMINAL MESSAGE DATA BUFFERS................................... 161

17.1. Subaddress Message Information Words ............................................................... 162
17.1.1. Receive Subaddress Command .......................................................................... 162
17.1.2. Transmit Subaddress Command ......................................................................... 164
17.2. Mode Command Message Information Words........................................................ 166
17.2.1. Receive Mode Command .................................................................................... 166
17.2.2. Transmit Mode Command ................................................................................... 168
17.3. Ping-Pong Data Buffering........................................................................................ 170
17.3.1. Double Buffered (Ping-Pong) Mode..................................................................... 170
17.3.2. Ping-Pong Enable / Disable Handshake.............................................................. 171
17.3.3. Broadcast Message Handling in Ping-Pong Mode............................................... 173
17.4. Indexed Data Buffer Mode....................................................................................... 175
17.4.1. Single Message Mode.......................................................................................... 175
17.4.2. Broadcast Message Handling in Index Mode....................................................... 175
17.5. Circular Buffer Mode 1............................................................................................. 179
17.6. Circular Buffer Mode 2............................................................................................. 183
18. REMOTE TERMINAL MODE COMMAND PROCESSING......................... 188

18.1. General Considerations........................................................................................... 188
18.2. Mode Command Interrupts...................................................................................... 188
18.3. Mode Command Data Words.................................................................................. 189
18.4. Standard Mode Command Processing.................................................................... 191
18.5. Simplified Mode Command Processing................................................................... 191
19. SERIAL EEPROM PROGRAMMING UTILITY............................................ 193

19.1. Writing the Auto-Initialization EEPROM................................................................... 193
19.2. Overall 8K Word Checksum Used by Auto-Initialization.......................................... 196
19.3. Fast Initialization Option using EE2K Pin................................................................. 197
20. RESET AND INITIALIZATION...................................................................... 198

20.1. Hardware Master Reset and Optional Auto-Initialization......................................... 198
20.2. Initialization using EE2K Pin.................................................................................... 201
20.3. Memory Test Fail Address Register (0x0024)........................................................ 201
20.4. Software Reset........................................................................................................ 202
20.4.1. Remote Terminal ................................................................................................. 202
20.4.2. Bus Monitor SMT.................................................................................................. 203

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20.5. MIL-STD-1760: Busy Status Assertion After Power-Up........................................... 204
21. SELF-TEST.................................................................................................... 205

21.1. Optional RAM Self-Test after Hardware Master Reset............................................ 205
21.2. Host-Directed Self-Test............................................................................................ 205
21.2.1. Self-Test Control Register (0x0028) .................................................................. 205
21.2.2. Loopback Test Transmit Data Register (0x001F)............................................... 209
21.2.3. Loopback Test Receive Data Register (0x0002)................................................ 209
21.2.4. RAM Self-Test Fail Address Register (0x001B).................................................. 209
21.2.5. Host-Directed RAM Self-Test................................................................................ 210
21.2.6. Host-Directed RT-Mode Loopback Testing (On-Line Analog or Off-Line Digital) .210
21.2.7. Programmed BC-Mode Digital Loopback Testing (Off-Line) ............................... 211
21.2.8. Continuous BC-Mode Analog Loopback Testing (On-Line) ................................. 211
22. HOST SERIAL PERIPHERAL INTERFACE (SPI)....................................... 212

22.1. Serial Peripheral Interface (SPI) Basics .................................................................. 212
22.2. SPI Commands........................................................................................................ 213
22.3. Fast-Access Commands for Registers 0-15 ........................................................... 213
22.4. Fast-Access Write Commands for Registers 0-63 .................................................. 213
22.5. Indirect Addressing of RAM and Registers ............................................................. 213
22.6. Data Prefetch for SPI Read Cycles ......................................................................... 216
22.7. Special Purpose Commands .................................................................................. 216
22.8. RT Descriptor Table Prefetch Exceptions ............................................................... 219
23. APPENDIX: RT MESSAGES RESPONSES, OPTIONS &

EXCEPTIONS ............................................................................................... 223
24. ELECTRICAL CHARACTERISTICS............................................................ 251
24.1. Absolute Maximum Ratings..................................................................................... 251
24.2. Recommended Operating Conditions...................................................................... 251
24.3. DC Electrical Characteristics................................................................................... 251
24.4. AC Electrical Characteristics ― Host Bus Interface (SPI) Timing............................ 253
24.5. AC Electrical Characteristics ― Master Reset......................................................... 254
25. MIL-STD-1553 BUS INTERFACE................................................................. 255

26. ADDITIONAL PIN / PACKAGE CONFIGURATIONS.................................. 256
26.1. HI-6138PQx (48-pin PQFP)..................................................................................... 256

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HI-6138
27. ORDERING INFORMATION......................................................................... 257

28. REVISION HISTORY.................................................................................... 258
29. PACKAGE DIMENSIONS............................................................................. 262

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List of Figures
Figure 1. Block Diagram............................................................................................................... 14
Figure 2. Address Mapping for Registers and RAM..................................................................... 19
Figure 3. Fixed Address Mapping for Interrupt Log Buffer............................................................ 40
Figure 4. Bus Controller Message Sequence Structures............................................................. 55
Figure 5. Bus Controller Flag Operation....................................................................................... 66
Figure 6. Structure of Bus Controller Message Control / Status Blocks in RAM.......................... 68
Figure 7. Simple Monitor Terminal (SMT) Data Storage............................................................. 102
Figure 8. Deriving the Monitor Filter Table Address from the Received Command Word.......... 106
Figure 9. MIL-STD-1553 Command Word Structure.................................................................. 138
Figure 10. Deriving the Illegalization Table Address From the Received Command Word........ 142
Figure 11. Address Mapping for Illegalization Table .................................................................. 143
Figure 12. Summary of RT Illegalization Table Addresses for Mode Code Commands ............ 144
Figure 13. Address Mapping for RT Descriptor Table ................................................................ 147
Figure 14. Deriving a Descriptor Table Control Word Address From Command Word .............. 148
Figure 15. Illustration of Ping-Pong Buffer Mode ....................................................................... 172
Figure 16. Ping-Pong Buffer Mode Example for a Receive Subaddress ................................... 174
Figure 17. Illustration of Indexed Buffer Mode ........................................................................... 177
Figure 18. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled) ..... 178
Figure 19. Illustration of Circular Buffer Mode 1......................................................................... 181
Figure 20. Circular Buffer Mode 1 Example for a Receive Subaddress .................................... 182
Figure 21. Illustration of Circular Buffer Mode 2......................................................................... 186
Figure 22. Circular Buffer Mode 2 Example for a Receive Subaddress .................................... 187
Figure 23. Generalized Single-Byte Transfer Using SPI Protocol.

SCK is Shown for SPI Modes 0 and 3 ...................................................................... 212
Figure 24. Single-Word (2-Byte) Read From RAM or a Register............................................... 214
Figure 25. Single-Word (2-Byte) Write To RAM or a Register ................................................... 215

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HI-6138
Figure 26. Host Bus Interface Timing Diagram........................................................................... 253
Figure 27. Master Reset Timing Diagram................................................................................... 254
Figure 28. Bus Connection Example using HI-6138................................................................... 255
Figure 29. MIL-STD-1553 Direct Coupled Test Circuits.............................................................. 255
Figure 30. MIL-STD-1553 Transformer Coupled Test Circuits.................................................... 255

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List of Tables
Table 1. Pin Descriptions.............................................................................................................. 16
Table 2. Host Interface Pins.......................................................................................................... 18
Table 3. Register Summary.......................................................................................................... 24
Table 4. Format of IIW and IAW in Interrupt Log Buffer................................................................ 38
Table 5. Bus Controller Condition Code Table.............................................................................. 56
Table 6. Bus Controller Instruction Op Codes.............................................................................. 59
Table 7. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition...... 87
Table 8. Message Block in Circular Command Buffer for SMT Monitor using 16-bit Time Tag.... 98
Table 9. Message Block in Circular Command Buffer for SMT Monitor using 48-bit Time Tag.... 99
Table 10. Monitor Address List for SMT...................................................................................... 100
Table 11. SMT Message Filter Table........................................................................................... 107
Table 12. Summary of Data Buffer Modes. ................................................................................ 162
Table 13. Circular Buffer Mode 2 (Initialization factors based on message block size).............. 184
Table 14. Mode Code Command Summary............................................................................... 189
Table 15. External EEPROM minimum instruction set. ............................................................. 193
Table 16. Terminal Unlock Word Encoding................................................................................. 194
Table 17. Registers not included in checksum........................................................................... 196
Table 18. READY delay times: from MR input pin rising edge to READY output pin rising edge.....
198
Table 19. RT Soft Reset Summary............................................................................................. 202
Table 20. SMT Soft Reset Summary.......................................................................................... 203
Table 21. Fast-Access SPI Commands for Lower Registers ..................................................... 221
Table 22. SPI Commands using Memory Address Pointer......................................................... 222

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HI-6138
1. BLOCK DIAGRAM
HI-6135 / HI-6136 / HI-6137 / HI-6138

MIL-STD-1553 Terminal with SPI Host Interface
RTA4 - 0
RTAP
Configuration EE2K
Option BENDI
IRQ
Logic LOCK
READY Discrete
Signal Static RAM MTSTOFF
ACTIVE and
Outputs MODE1760
RTMC8 Registers
BC
Message
Address
TXINHA
Control
Processor
Data
Addres & Control

HI-6137
Bus A
HI-6138 BUSA
Words
Manchester
Encoder
BUS
Bus A
MT
Address Memory Manchester
CE Message BUSA
SPI and Processor
Decoder
SCK Data
Host Register
SI Interface Control Access HI-6136
SO Control HI-6138
Rx 1553 Words
Tx 1553 Words
RT TXINHB
MCLK Message
Address
Control
INTERNAL Processor Bus B

Data
TTCLK BUSB
CLOCKS Manchester
MTTCLK All Devices Encoder
BUS
Bus B
AUTOEN Reset & Manchester
Decoder BUSB
EECOPY Initialization
MR Logic
TRANSCEIVER
VCCP
POWER
Address
Control
Data
GND
LOGIC POWER VCC
BCTRIG Discrete
Signal Serial
ACKIRQ
Input Peripheral
RTSSF Interface TEST
(SPI) to Test
Logic MODE
EEPROM
MISO
MOSI
ESCK
ECS
OPTIONAL
SERIAL EEPROM
(AUTO-CONFIG)
Figure 1. Block Diagram

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HI-6138
2. FEATURE OVERVIEW
2.1. Bus Controller Operation

The HI-6138 is configurable to operate as a Bus Controller (BC). The BC is a programmable message-sequencing
device for control in MIL-STD-1553B applications. Programmed using a set of 28 instruction op codes, the BC greatly
reduces the host’s processing workload. The BC can optionally use a 16- or a 32-bit time base, clocked from a choice
of six internally generated clocks, or an external time base clock. Special BC op codes manage all 32-bit time base
functions.
The programmable Bus Controller autonomously supports multi-frame message scheduling, message retry schemes,
storage of message data, asynchronous message insertion and status/error reporting to the host processor.
2.2. Remote Terminal Operation

The HI-6138 is configurable to operate one a Remote Terminal. The RT is software compatible with Holt’s popular
HI-6130/31 Remote Terminal.
2.3. Monitor Terminal Operation

Message commands, terminal responses and message data are stored in internal RAM, using Simple Monitor Terminal
(SMT) Mode. When operating in SMT mode, the MT records commands and data separately. The SMT can utilize 16-
or 48-bit time tags with a range of clocking options.
2.4. Interrupts
Host interrupts can originate from device hardware or any of the enabled terminal devices (up to 3 devices). A circular
64-word Interrupt Log Buffer retains interrupt information from the last 32 interrupts, while the hardware maintains a
count of occurring interrupts since the previous host buffer service.
Hardware-assisted interrupt decoding provides quick identification of the interrupt source by terminal device: BC, MT,
RT or hardware. When a hardware interrupt occurs (e.g., Bus A Loopback Failure), a Pending Hardware Interrupt
register bit explicitly identifies the interrupt source. For interrupts from BC, MT or RT, the three low-order bits in the
same register identify the specific interrupt register (or registers) with pending interrupts: that is, the BC, MT or RT
Pending Interrupt registers.
2.5. Reset and Initialization

After hardware Master Reset, there are two initialization methods: host initialization or self-initialization from external
serial EEPROM. For host initialization, the host processor uses the 4-wire SPI to load registers and initialize tables,
data buffers, etc. in internal static RAM. For self-initialization, the device uses setup information contained within an
external serial EEPROM. A dedicated 4-wire SPI port reads data from the serial EEPROM and writes it to registers and
RAM. Error checking is performed, looking for data mismatch or an EEPROM checksum error.
Individual 1553 terminal devices (BC, MT, or RT) can be re-initialized from the serial EEPROM. Refer to “Reset and
Initialization” on page 198.

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HI-6138
3. PIN DESCRIPTIONS
Table 1. Pin Descriptions
Pin Function Description
Input
MCLK Master clock input, 50.0MHz +/-100 ppm.
50kΩ pull-down
TTCLK Inputs Optional clock input for BC time base and RT time tag counters.
MTTCLK 50kΩ pull-down Optional clock input for the MT time tag counter.
Each function (BC, MT, RT) has an independent time tag counter. The BC
and RT counters share a common clock, selectable from internally generated
frequencies, or an external clock input. The MT time tag counter has its own
external or internal clock source.
Master reset, active low. A minimum pulsewidth of 50ns and two rising clock
Input edges are required following the rising edge of MR to complete reset.
MR
50kΩ pull-up The host can also assert software reset by setting bits in the “Master Status and
Reset Register (0x0001)”.
Transmit inhibit inputs for Bus A and Bus B, active high. These two inputs are
TXINHA Inputs logically ORed with the pair of corresponding bits in the “Master Configuration
TXINHB 50kΩ pull-up Register 1 (0x0000)” to enable or inhibit transmit on Bus A or Bus B, affecting
behavior for all enabled 1553 devices.
Memory test disable, active high. When this pin is low, the device performs a
Input memory test on the entire RAM after rising edge on the MR reset pin. When
MTSTOFF
50kΩ pull-down this pin is high, RAM testing is skipped, resulting in a faster reset process. For
further information, refer to “Reset and Initialization” on page 198.
Auto-Initialize Enable, active high. If this pin is high at rising edge on MR reset
Input pin, self-initialization proceeds, copying configuration data to registers and RAM
AUTOEN
50kΩ pull-down from an external serial EEPROM via a dedicated EEPROM SPl port. Refer to
“Reset and Initialization” on page 198.
When the AUTOEN pin is high, the EE2K input sets the range of the auto-
initialization process. When EE2K is low, registers and RAM occupying the 8K
Input address range from 0x0 to 0x1FFF are initialized. For applications needing
EE2K
50kΩ pull-down faster initialization, when EE2K is high, only registers and RAM occupying the
2K address range from 0x0 to 0x07FF are initialized. If the AUTOEN pin is low,
this pin is not used.
This pin is low when auto-initialization or built-in test is in process. The host
cannot read or write device RAM or registers when pin state is low; reads to any
READY Output address return the value in the “Master Status and Reset Register (0x0001)”.
When the AUTOEN pin is low at Master Reset, the host can configure device
RAM and registers after READY goes high.
This pin is high while an enabled BC or RT in the device is processing a 1553

ACTIVE Output message. The IMTA bit 1 in “Master Configuration Register 1 (0x0000)” logically-
ORs bus monitor (MT) activity as well.

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HI-6138
ECS Output
ESCK Output Dedicated 4-wire Serial Peripheral Interface (SPI) for connection to an optional
MOSI Output external EEPROM used for automatic self-initialization when AUTOEN is high
MISO Input at Master Reset.
50kΩ pull-down
EEPROM Copy, active high. Asserting this input initiates RAM and register copy
Input
EECOPY into serial EEPROM used for auto-initialization. Refer to “Reset and Initialization”
50kΩ pull-down
on page 198.
Input
BCTRIG BC Trigger input, active high. Used in conjunction with certain BC instructions.
50kΩ pull-down
Mode 1760 enable, active high. Assert this pin during a hardware reset to enable
Input 1760 mode. During 1760 mode, the device will respond to any valid command
MODE1760
50kΩ pull-down (with matching RT address) with the BUSY bit set in the status word. No data
words will be transmitted and no interrupts or logging of data will occur.
Pin states are latched to the Lock bit in the RT Operational Status Register (see
page 125) when rising edge occurs on the MR pin. If status register Lock bit
Input
LOCK is high, the host cannot overwrite the terminal address in the same register. If
50kΩ pull-down
status register Lock bit is low, the host can overwrite the terminal address and
parity (and the Lock bit) in the RT Operational Status register.
Remote Terminal “Reset RT” mode command (MC8) received. This active low
Output output is asserted at Status Word completion when the RT received a “Reset
RTMC8
Open-Drain Remote Terminal” mode code command. The minimum output pulse width is
100ns, unaffected by MR assertion.
RT Subsystem Fail input, active high. When this input is high, the RT sets the
Input
RTSSF Subsystem Fail flag in its transmit status word. This input is logically-ORed with
50kΩ pull-down
the SSYSF bit in the RTs 1553 Status Word Bits Register.
Interrupt request, active low. This pin is asserted each time an enabled interrupt
event occurs. This signal is programmed as a brief low-going pulse output or
Output
IRQ as a level output by the INTSEL bit in the “Master Configuration Register 1
Open-Drain
(0x0000)”. If level output is selected, IRQ stays low until the host acknowledges
IRQ by pulsing a rising edge at the ACKIRQ pin.
Interrupt Acknowledge, active high. This input is only used when the INTSEL bit
Input in the RT Configuration Register is high, enabling level interrupt assertion for the
ACKIRQ
50kΩ pull-down IRQ pin. When interrupt assertion causes the IRQ pin to go low, a high-going
pulse on ACKIRQ (250ns minimum duration) clears the IRQ output to logic 1.
Remote terminal address bits 4 - 0, and parity bit for the RT. The RTAP pin
provides odd parity for the address on pins RTA4:0.
RTA4:0 Inputs The terminal address and parity pin levels are latched into the RT Operational
RTAP 50kΩ pull-ups Status Register (see page 125) when rising edge occurs on the MR pin. The
RT Operational Status Register value (not these pins) reflects the active terminal
address. The host can overwrite the RT Operational Status register address
value only when the register Lock bit is reset.

17
HI-6138
Big Endian configuration pin for selecting “endianness” or byte order, when
using byte transfers. Endianness is the system attribute that indicates whether
integers are represented with the most significant byte stored at the lowest
address (big endian) or at the highest address (little endian). Internal register /
Input RAM storage is “big endian.”
BENDI
50kΩ pull-down This pin controls the byte order of transferred 16-bit data following the SPI
command. When BENDI is low, “little endian” is chosen; the low order byte (bits
7:0) is transacted on the SPI before the high order byte (bits 15:8). When BENDI
is high, “big endian” is chosen and the high order byte is transacted on the SPI
before the low order byte.
Input Test enable input. The host asserts this pin to perform RAM self-test and loop-
TEST
50kΩ pull-down back tests.
Input
MODE Pin used for factory test. Do not connect.
50kΩ pull-up
VCC
VCCP Power Supply 3.3VDC power supply for logic and bus transceiver.
GND
BUSA Bi-directional Bus A interface to external MIL-STD-1553 isolation transformer.

Analog
BUSA Observe positive / negative polarity.
BUSB Bi-directional Bus B interface to external MIL-STD-1553 isolation transformer.

Analog
BUSB Observe positive / negative polarity.
Table 2. Host Interface Pins
Chip Enable, active low. When asserted, this pin enables host read or write
Input accesses to device RAM or registers via host SPI port. The SPI port operates
CE
50kΩ pull-up in Slave mode. This pin is connected to the Slave Select output on the host
SPI port.
Serial Peripheral Interface (SPI) Serial Output pin. This pin is connected to
SO Output MISO (Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated
when not transmitting serial data to the host.
Input Serial Peripheral Interface (SPI) Serial Input pin. This pin is connected to
SI
50kΩ pull-down MOSI (Master Out - Slave In) pin on host SPI port.
Input Serial Peripheral Interface (SPI) Serial Clock pin. This pin is connected to SCK
SCK
50kΩ pull-down output pin on host SPI port.

18
HI-6138
4. MEMORY MAP
0x1FFF 0x01FF
32 Words
0x01E0
0x01DF
RT Temporary Receive Buffer.
32 Words
0x01C0
0x01BF
Host-Allocated Interrupt Log Data Buffer.

Static RAM. 64 Words
Comprising 97% of the memory
address space, this RAM is
allocated for use by the
enabled terminal devices. 0x0180
0x017F
MT Message Filter Table.

128 Words
0x0600
0x05FF RT Descriptor Table.
Defines terminal behavior 0x0100
for valid commands: 0x00FF
how data is stored,
host interrupts, etc.
512 words BC General Purpose Queue.
64 Words
Multiple Descriptor Tables can be
used for fast context switching.
The active Descriptor Table is 0x00C0
defined by the Descriptor Table
0x00BF MT Address List B. 8 Words
Base Address Register.
0x0400 0x00B8
0x03FF 0x00B7 MT Address List A. 8 Words
0x00B0
256 Words
0x00AF
MT Temporary Buffer B.
42 Words
0x0300 0x0086
0x02FF 0x0085
RT Illegalization Table. MT Temporary Buffer A.
Initialized by the host, this table 42 Words
identifies illegal commands. 0x005C
256 Words 0x005B BC Call Stack. 8 Words
0x0200 0x0054
0x01FF 0x0053 Reserved. 2 Words
0x0052
Expanded 0x0051
at Right Registers
82 Locations
0x0000 0x0000
Figure 2. Address Mapping for Registers and RAM

19
HI-6138
5. RAM STRUCTURES
Figure 2 shows a map for memory and registers. Application requirements dictate the specific RAM structures needed.
These structures listed here are explained later.
5.1. Interrupt Log Data Buffer

The device maintains information from the last 32 interrupts in a 64-word circular buffer in RAM known as the Interrupt
Log. Two 16-bit words characterize each interrupt; one word identifies the interrupt type (Interrupt Identification Word)
and one word identifies the command that generated the interrupt (Interrupt Address Word). After reset, the Interrupt
Log Address Register contains the fixed buffer start address of 0x0180. After each occurring interrupt, the device
updates the register to point to the log address used for the next occurring interrupt.
5.2. Bus Controller (BC) Instruction List

BC message sequencing uses an instruction list, comprised of multiple 2-word entries. Each entry consists of an
instruction word (op code plus execution condition code) followed by a parameter word. Some op codes execute
unconditionally, but most are conditional, and execute only if the condition code specified in the instruction word tests
true. This architecture provides flexibility for message frame scheduling and autonomous BC program execution,
based on various conditions.
5.3. Bus Controller (BC) Msg Control / Status Stack

Referenced when a BC Instruction List parameter is an address pointer, the Message Control Status Stack consists
of 8- or 16-word control blocks for individual MIL-STD-1553 messages. Within the message control/status block,
execution parameters are provided including inter-message gap, message format, active bus, message command
word(s), the address pointer to a message data block in RAM (when the command includes data) and the expected
RT status response.
5.4. Bus Controller (BC) Call Stack

When the Bus Controller executes a “subroutine call” op code, the BC Subroutine Call Stack stores the list address for
the next op code, to be executed upon return from subroutine. The BC call stack allows 8 levels of nesting.
5.5. Bus Controller (BC) General Purpose Queue

The Bus Controller General Purpose Queue provides a convenient way for the BC to convey information to the external
host. Numerous BC op codes push various data onto the queue, including time tag count, data values, message Block
Status Word or the data at specific RAM address locations.
5.6. Monitor Terminal Temporary Buffers A & B

The Monitor Terminal (MT) has one 42 word receive buffer for each bus. Received command words, status words and
data words are temporarily stored in these buffers. At message completion, the recorded data is copied to Monitor
Terminal buffer(s).
5.7. Monitor Terminal (MT) Address List

The monitor Address List contains user-written RAM addresses assigning buffer start and end addresses, and buffer
utilization interrupt addresses. It also has device-maintained data buffer pointer(s).

20
HI-6138
5.8. Monitor Terminal (MT) Message Filter Table

This 128-word table is optionally used to selectively monitor MIL-STD-1553 messages based on each command’s RT
address and subaddress, and the transmit/receive bit status.
5.9. Monitor Terminal (MT) Data Buffers

For bus monitor applications, the SMT simple monitor stores command and data words in separate RAM buffers. The
monitor Address List assigns RAM buffer boundaries.
5.10. RT Command Illegalization Table

Optional illegal command detection utilizes this table in RAM. The table can illegalize any logical combination of 11
command word bits comprising subaddress, the transmit/receive bit and word count (or mode code), plus broadcast
vs non-broadcast status, resulting in a total of 4,096 possible combinations. Terminal response to an illegal command
sets “Message Error” status and transmits Status Word only. If illegal command detection is not used (that is, no
“illegal” entries in Illegalization Table), the terminal responds “in form” to all valid commands.
5.11. RT Descriptor Table

A host-initialized Descriptor Table in RAM defines how the terminal responds to valid commands. The table is comprised
of 128 four-word descriptor blocks. Each of 32 subaddresses and 32 mode code values has one descriptor block for
transmit and another for receive. The descriptor table defines message options (interrupt selections, data buffer mode,
etc.) and contains pointers to allocated data storage in RAM.
5.12. RT Temporary Receive Buffer

The Remote Terminal temporarily stores command and data words during message transaction. At successful
message completion, all data is transferred to assigned subaddress buffers. This strategy prevents valid data from
being overwritten by incomplete or bad data from a later message ending in error.
5.13. RT Message Data Buffers

Subaddress transmit and receive commands transact from 1 to 32 data words. For each transmit or receive subaddress,
the application allocates space in RAM for storing a Message Information Word, Time Tag Word and the transacted
message data words.
5.14. RT Storage for Mode Code Commands

In addition to commands used for data transmit and receive, MIL-STD-1553 also defines “mode code commands” for
command and control. These “mode commands” either transfer a single data word, or no data word at all. The user
has the option for storing mode data words in RAM buffers assigned in the Descriptor Table, or stored within the RT
Descriptor Table itself. The second option is often preferred for its simplicity.

21
HI-6138
6. HARDWARE FEATURES
6.1. Remote Terminal Address Inputs

The 5-bit Remote Terminal address for the RT is set using pins RTA4:0. The RTAP input pin should be set or reset
to present matching odd parity. The state of the RT address and parity pins is latched into the RT Operational Status
register (see page 125) upon rising edge on the MR master reset input. The state of the LOCK input is latched into the
RT Operational Status register at the same time, and controls whether or not the terminal address and parity in the RT
Operational Status register can be overwritten by host writes into the register. When the LOCK input pin is high, auto-
initialization cannot overwrite the RT address value latched from the input pins. Between Master Reset assertions, the
state of the RTA and RTAP input pins is “don’t care”. If the value of RT address and parity in the RT Operational Status
register has parity error, terminal operation is disabled.
6.2. Dual Transceivers for MIL-STD-1553 Bus

Built-in bus transceivers provide direct interface between the device and MIL-STD-1553 bus isolation transformers.
The transceivers convert digital data to and from differential Manchester II encoded bus signals. A pair of “transmit
inhibit” input pins exercises direct control over transmission for both buses.
6.3. Encoder and Decoders

The device uses separate Manchester II encoders and decoders for each bus. Decoders check for proper sync pulse
and Manchester waveform, edge skew, correct number of bits and parity. Encoders are used for transmission. During
transmit, each encoded word is looped back through the bus decoder for error checking. Receiver bus sampling is
clocked at 50 MHz, providing excellent tolerance to zero-crossing distortion.
6.4. Auto-Initialization Serial EEPROM Interface

The device has an automatic self-initialization feature. If self-initialization is enabled after MR master reset, the device
reads configuration settings from an external serial EEPROM during initialization to initialize registers and RAM
structures. A method is provided to initially program or later overwrite the external serial EEPROM by copying host-
loaded tables and register values to the serial EEPROM.
6.5. Transmit Time-out Fail-Safe Counter

BUS A and BUS B transmitters both have continuously running watchdog timers that prevent continuous transmission
beyond 663μs. Configuration options can optionally set the Terminal Flag status bit in the “Remote Terminal MIL-
STD-1553 Status Word Bits Register (0x001A)” and inhibit all further transmissions once watchdog timer timeout has
occured.
6.6. MIL-STD-1760 Mode

A dedicated hardware pin is available to activate MIL-STD-1760 Mode. When operating in MIL-STD-1760 mode, the
device responds to any valid command (with matching RT address) with the BUSY bit set in the status word. No data
words will be transmitted and no interrupts or logging of data occurs during post-reset initialization when operating in
MIL-STD-1760 mode.

22
HI-6138
7. REGISTER & MEMORY ADDRESSING

The HI-6138 has an internal address space of 8,192 (8K) 17-bit words. Registers occupy the low 80 locations in this
address space. In this data sheet, register / RAM addresses are expressed as hexadecimal numbers, using the C
programming convention where the prefix “0x” denotes a hexadecimal value; e.g., 0x00FF represents 00FF hex.
Figure 2 shows address mapping for registers and RAM. All registers and some RAM structures have fixed addresses.
Other RAM structures shown are relocatable; Each relocatable structure has a base address register. Figure 2
shows the default locations for relocatable structures. RAM allocations for0 unused MIL-STD-1553 functions can be
reassigned as needed. For example, an application using just a Bus Monitor can reassign all BC and RT RAM for
monitor needs. Device RAM and register address mapping is word oriented, rather than byte oriented.
8. REGISTER DEFINITIONS
Residing at the start of the memory address space, 82 addresses are reserved for registers. Register addresses
overlay the shared RAM address space. Register bits are active high and bit 15 is the most significant.
Table 3 lists all device registers.

23
HI-6138
Table 3. Register Summary
Hard
Register Hex
Used By Register Name Reset
Number Address
Default
0 0x0000 All “Master Configuration Register 1 (0x0000)” on page 28 0x0000
1 0x0001 All “Master Status and Reset Register (0x0001)” on page 33 0x0000
When TEST pin is logic 0, this address is “Remote Terminal

Current Command Register (0x0002)” on page 127
2 0x0002 RT 0x0000
When TEST pin is logic 1, this address is “Loopback Test
Receive Data Register (0x0002)” on page 209
“Remote Terminal Current Control Word Address Register

3 0x0003 RT 0x0000
(0x0003)” on page 127
4 0x0004 ---- Reserved 0x0000
5 0x0005 ---- Reserved 0x0000
6 0x0006 All “Hardware Pending Interrupt Register (0x0006)” on page 41 0x0000
“Bus Controller (BC) Pending Interrupt Register (0x0007)” on page

7 0x0007 BC 0x0000
95
“SMT Bus Monitor Pending Interrupt Register (0x0008)” on page
8 0x0008 MT 0x0000
116
“Remote Terminal (RT) Pending Interrupt Register (0x0009)” on
9 0x0009 RT 0x0000
page 135
10 0x000A All “Interrupt Count & Log Address Register (0x000A)” on page 37 0x0180
11 0x000B All “Memory Address Pointer Registers” on page 52 0x0000
12 0x000C All “Memory Address Pointer Registers” on page 52 0x0000
13 0x000D All “Memory Address Pointer Registers” on page 52 0x0000
14 0x000E All “Memory Address Pointer Registers” on page 52 0x0000
15 0x000F All “Hardware Interrupt Enable Register (0x000F)” on page 41 0x6018
“Bus Controller (BC) Interrupt Enable Register (0x0010)” on page

16 0x0010 BC 0x0000
95
“SMT Bus Monitor Interrupt Enable Register (0x0011)” on page

17 0x0011 MT 0x0000
116
“Remote Terminal (RT) Interrupt Enable Register (0x0012)” on

18 0x0012 RT 0x0000
page 135
“Hardware Interrupt Output Enable Register (0x0013)” on page

19 0x0013 All 0x6018
41
“Bus Controller (BC) Interrupt Output Enable Register (0x0014)”

20 0x0014 BC 0x0000
on page 95

24
HI-6138
Hard
Register Hex
Number Address
Default
“SMT Bus Monitor Interrupt Output Enable Register (0x0015)” on

21 0x0015 MT 0x0000
page 116
“Remote Terminal (RT) Interrupt Output Enable Register (0x0016)”

22 0x0016 RT 0x0000
on page 135
23 0x0017 RT “Remote Terminal Configuration Register (0x0017)” on page 119 0x0000
“Remote Terminal Operational Status Register (0x0018)” on page

24 0x0018 RT 0x0000
125
“Remote Terminal Descriptor Table Base Address Register

25 0x0019 RT 0x0400
(0x0019)” on page 127
“Remote Terminal MIL-STD-1553 Status Word Bits Register

26 0x001A RT 0x0000
(0x001A)” on page 128

Current Message Information Word Register (0x001B)” on page
27 0x001B RT 129. 0x0000
When TEST pin is logic 1, this address is “RAM Self-Test Fail
Address Register (0x001B)” on page 209.
28 0x001C RT “Remote Terminal Bus A Select Register (0x001C)” on page 130 0x0000
29 0x001D RT “Remote Terminal Bus B Select Register (0x001D)” on page 130 0x0000
“Remote Terminal Built-In Test (BIT) Word Register (0x001E)” on

30 0x001E RT 0x0000
page 131

Alternate Built-In Test (BIT) Word Register (0x001F)” on page
31 0x001F RT 132. 0x0000
When TEST pin is logic 1, this address is “Loopback Test
Transmit Data Register (0x001F)” on page 209.
32 0x0020 ---- Reserved 0x0000
33 0x0021 ---- Reserved 0x0000
34 0x0022 ---- Reserved 0x0600
35 0x0023 ---- Reserved 0x0000
When the AUTOEN input pin is logic 1 at rising edge of MR

Master Reset and RAM or register initialization failure (RAMIF)
occurs, this register is the “Memory Test Fail Address Register
36 0x0024 ---- (0x0024)” on page 201. This register holds the first encountered 0x0000
RAM / register address with data mismatch. There may be others.
Once execution starts (or when not using auto-initialization), this
register has no function.
37 0x0025 ---- Reserved 0x0000
38 0x0026 ---- Reserved 0x0000

25
HI-6138
Hard
Register Hex
Number Address
Default
39 0x0027 ---- Reserved 0x0000
When TEST pin is logic 0, this register has no function.

40 0x0028 ---- When TEST pin is logic 1, this address is “Self-Test Control 0x0000
Register (0x0028)” on page 205
41 0x0029 MT “SMT Configuration Register (0x0029)” on page 108 0x0801
42 0x002A ---- Reserved 0x0000
43 0x002B ---- Reserved 0x0000
44 0x002C ---- Reserved 0x0000
45 0x002D ---- Reserved 0x0000
46 0x002E ---- Reserved 0x0000
“SMT Bus Monitor Address List Start Address Register (0x002F)”

47 0x002F MT 0x00B0
on page 111
“SMT Next Message Command Buffer Address (0x0030)” on page
48 0x0030 MT 0x0000
111
“SMT Last Message Command Buffer Address (0x0031)” on page
49 0x0031 MT 0x0000
112
“BC (Bus Controller) Configuration Register (0x0032)” on page

50 0x0032 BC 0x0000
78
“Start Address Register for Bus Controller (BC) Instruction List

51 0x0033 BC 0x0000
(0x0033)” on page 87
“Bus Controller (BC) Instruction List Pointer (0x0034)” on page

52 0x0034 BC 0x0000
87
“Bus Controller (BC) Frame Time Remaining Register (0x0035)”

53 0x0035 BC 0x0000
on page 88
“Bus Controller (BC) Time To Next Message Register (0x0036)” on

54 0x0036 BC 0x0000
page 88
“Bus Controller (BC) Condition Code Register (Read 0x0037)” on

page 88
55 0x0037 BC 0x0000
“Bus Controller (BC) General Purpose Flag Register (Write
0x0037)” on page 91
“Bus Controller (BC) General Purpose Queue Pointer Register

56 0x0038 BC 0x00C0
(0x0038)” on page 91
57 0x0039 All “Time Tag Counter Configuration Register (0x0039)” on page 48 0x0000
“SMT Bus Monitor Time Tag Count Register (0x003A)” on page

58 0x003A MT 0x0000
112
“SMT Bus Monitor Time Tag Count Mid Register (0x003B)” on

59 0x003B MT 0x0000
page 112

26
HI-6138
Hard
Register Hex
Number Address
Default
“SMT Bus Monitor Time Tag Count High Register (0x003C)” on

60 0x003C MT 0x0000
page 112
“SMT Bus Monitor Time Tag Utility Register (0x003D)” on page

61 0x003D MT 0x0000
113
“SMT Bus Monitor Time Tag Utility Mid Register (0x003E)” on page
62 0x003E MT 0x0000
113
“SMT Bus Monitor Time Tag Utility High Register (0x003F)” on

63 0x003F MT 0x0000
page 113
“SMT Bus Monitor Time Tag Match Register (0x0040)” on page

64 0x0040 MT 0x0000
114
“SMT Bus Monitor Time Tag Match Mid Register (0x0041)” on

65 0x0041 MT 0x0000
page 114
“SMT Bus Monitor Time Tag Match High Register (0x0042)” on
66 0x0042 MT 0x0000
page 114
67 0x0043 BC “Bus Controller (BC) Time Tag Counter (0x0043)” on page 92 0x0000
“Bus Controller (BC) Time Tag Counter High (0x0044)” on page

68 0x0044 BC 0x0000
92
“Bus Controller (BC) Time Tag Utility Register (0x0045)” on page
69 0x0045 BC 0x0000
93
“Bus Controller (BC) Time Tag Utility High Register (0x0046)” on

70 0x0046 BC 0x0000
page 93
“Bus Controller (BC) Time Tag Match Register (0x0047)” on page

71 0x0047 BC 0x0000
93
“Bus Controller (BC) Time Tag Match High Register (0x0048)” on

72 0x0048 BC 0x0000
page 93
“Remote Terminal Time Tag Counter Register (0x0049)” on page

73 0x0049 RT 0x0000
132
“Remote Terminal Time Tag Utility Register (0x004A)” on page

74 0x004A RT 0x0000
133
75 0x004B ---- Reserved 0x0000
76 0x004C ---- Reserved 0x0000
77 0x004D BC / RT “Extended Configuration Register (0x004D)” on page 44 0x0000
78 0x004E All “Master Configuration Register 2 (0x004E)” on page 31 0x3100
79 0x004F BC BC Last Message Block Address 0x0000
80 0x0050 BC Default location for BC WMI address pointer 0x0000
81 0x0051 ---- Checksum Fail Address & EEPROM Lock/Unlock 0x0000

27
HI-6138
9. REGISTERS USED BY ALL DEVICE FUNCTIONS
9.1. Master Configuration Register 1 (0x0000)
AP L1
e 0
TS d
TE d
TE d
d
TS O
es L
E T
D X
R rve
M rve
R rve
ve
TX HA
BC HB
M SE
IM EL
R SE
R NA
M NA
R NA
BC TR
IN TX
BS TE
er
TA
e
e
IN
IN
AP
S
es
es
es
TX
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
All bits in this 16-bit register are read-write and are fully maintained by the host. This register is cleared after MR pin
master reset, and is unaffected by assertion of the MTRESET, RTRESET bits in the “Master Status and Reset Register
(0x0001)”.
When configuring registers and RAM following Reset, “Master Configuration Register 1 (0x0000)” should always be
written last to ensure configuration and initialization is complete before starting terminal operation (i.e. this ensures
BCSTART and RTSTEX bits are not set until after configuration is complete). See “20.1. Hardware Master Reset and
Optional Auto-Initialization” for further details.
Bit No. Mnemonic R/W Reset Function
Transmit Inhibit Bus A.
15 TXINHA R/W 0 This bit is logically ORed with the TXINHA input pin. This register bit and
the corresponding TXINHA pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus A.
Transmit Inhibit Bus B.
14 TXINHB R/W 0 This bit is logically ORed with the TXINHB input pin. This register bit and
the corresponding TXINHB pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus B.
Bus Controller Start.
13 BCSTRT R/W 0 If the BCENA register bit is logic 1, a host write which sets this bit to 1
begins Bus Controller operation. When written to 1, this bit self-resets to
0. This bit always reads back a logic 0 state.
Bus Controller Enable.

If this bit is logic 0, Bus Controller operation is disabled.
When the BCENA bit is logic 1, the Bus Controller device is enabled,
12 BCENA R/W 0 but BC operation does not begin until BCSTRT bit 13 is set. If this bit
becomes logic 0 while the BC operation is underway, all BC timers will be
reset to 0, current message transmission will complete, and BC operation
will terminate when the current opcode is complete.

28
HI-6138
MAP (Memory Address Pointer) Select.

The host SPI relies on a hardware memory address pointer for many SPI
register or RAM accesses. This 2-bit field specifies which MAP is active
for SPI transactions:
Register Bit Active Map MAP Register Enabling SPI

11-10 Address Op Code
0-0 MAP1 0x000B 0xD8
0-1 MAP2 0x000C 0xD9
1-0 MAP3 0x000D 0xDA
1-1 MAP4 0x000E 0xDB
11 − 10 MAPSEL1:0 R/W 0 The full 16-bit register can be directly written by the host using SPI op
code 0x10, followed by 16-bit data word. An alternative method uses SPI
op codes 0xD8 – 0xDA that write just the 2-bit MAPSEL field, without
affecting other register data. These four SPI op codes only require
transmission of an 8-bit instruction, without accompanying data.
Note: “Fast access” SPI op codes contain embedded register addresses
and use a separate memory address pointer. This preserves values
contained in MAP1 through MAP4. The “fast access MAP” cannot be
read by the host but is written each time a “fast access” op code is
processed. Fast Access op codes are provided for these SPI operations:
• SPI reads to register addresses 0 through 0x000F (decimal 15)
• SPI writes to register addresses 0 through 0x003F (decimal 63)
9 Reserved - - This bit is not used and reads logic 0.
Bus Monitor Enable.

If this bit equals logic 0, Bus Monitor operation is disabled.
When the MTENA bit is logic 1, the Bus Monitor is enabled. Operation
commences when the receiver first decodes MIL-STD-1553 activity
8 MTENA R/W 0
meeting the “start record” criteria selected by bits 6:5 in the MT
Configuration Register. If monitor operation is underway when the
MTENA bit becomes logic 0, monitor operation stops after completion of
any message already underway; monitor resumes when the MTENA bit
is logic 1.
Remote Terminal Enable.

If this bit equals logic 0, RT operation is disabled.
6 RTENA R/W 0
When this bit is logic 1, Remote Terminal is enabled, but operation is
controlled by the state of the RTSTEX register bit.
Remote Terminal Start Execution.
4 RTSTEX R/W 0 If register bit 6 is logic 1, setting this bit begins Remote Terminal
operation. Once running, resetting this bit (or the RTENA register bit)
immediately stops RT operation.

29
HI-6138
Bus Shutdown Transmit Only.

The bit only applies when Remote Terminal is enabled. The BSDTXO
bit determines how a 1553 bus inhibit works when (a) the RTINHA
or RTINHB bit is set in the “Remote Terminal Configuration Register
(0x0017)”, or (b) the RT receives a valid “bus shutdown” mode code
command, either MC4 or MC20:
• When the BSDTXO bit is reset, logic 1 for an RTINHA or RTINHB
bit in “Remote Terminal Configuration Register (0x0017)” (or a “bus
shutdown” mode command with auto shutdown enabled) inhibits
both transmit and receive on the selected bus.
• When the BSDTXO bit is set, logic 1 for an RTINHA or RTINHB bit
in “Remote Terminal Configuration Register (0x0017)” (or a “bus
shutdown” mode command with auto shutdown enabled) inhibits
transmit only on the selected bus; but receive functions are
unaffected. Valid commands are heeded, but the RT transmits no
responses. NOT RECOMMENDED.
The RT automatically fulfills unconditional MC4 “bus shutdown” in
accordance with the BSDTXO setting, as well as MC5 “override bus
shutdown.”
3 BSDTXO R/W 0 The AUTOBSD bit in the “Remote Terminal Configuration Register
(0x0017)” determines whether conditional MC20 “selected bus shutdown”
and MC21 “override selected bus shutdown” are fulfilled automatically,
or by host writes to the RTINHA or RTINHB bits in the “Remote Terminal
Configuration Register (0x0017)”:
• When the AUTOBSD bit is logic 1 in the “Remote Terminal
Configuration Register (0x0017)” (see page 119), automatic
fulfillment is disabled for MC20 “selected bus shutdown” and MC21
“override selected bus shutdown” mode commands. The host fulfills
bus shutdown and override by writing the RTINHA and RTINHB bits
in the “Remote Terminal Configuration Register (0x0017)”.
• When the AUTOBSD bit is logic 0 in the “Remote Terminal
Configuration Register (0x0017)”, automatic fulfillment is enabled
for MC20 “selected bus shutdown” and MC21 “override selected bus
shutdown” mode commands. When the received mode data word
matches the value stored in the RT “Bus A (or B) Select” register, the
RT automatically fulfills MC20 “selected bus shutdown” in accordance
with the BSDTXO setting, as well as MC21 “override selected bus
shutdown”. Auto-shutdown bypasses the RTINHA and RTINHB bits
in the “Remote Terminal Configuration Register (0x0017)”, but the
upper 4 bits in the RT’s BIT Word register indicate Tx and Rx bus
shutdown status.
IRQ Output Type Select.
When this bit is 0, the IRQ (interrupt request) output generates a 1µs
negative pulse when enabled interrupt events occur. When this bit is
2 INTSEL R/W 0 logic 1, the IRQ output consists of a continuous low level output requiring
host action to negate IRQ to the high state. When level interrupts are
enabled, the host negates IRQ by asserting the ACKIRQ input pin for at
least 250ns.

30
HI-6138
Indicate MT Activity.
When this bit equals 0, the ACTIVE status output is not asserted for Bus
Monitor activity, unless the monitored message involves another on-
1 IMTA R/W 0 chip terminal). When this bit equals 1, enabled Bus Monitor activity is
logically-ORed with the activity of the other on-chip devices to determine
ACTIVE status; the ACTIVE output is asserted during such Bus Monitor
activity, whether or not the monitored message involves another on-chip
terminal.
9.2. Master Configuration Register 2 (0x004E)
K T
D ID1 D
R rve 0
LB TA
e 6
BC H
EV N
es d
TE d
es 7
D XIN
TX EST
D STP
W ST
TF rve
R ID0
R ID3
R ID2
R ID1
M ID0
BC MS
R E1
W F
D
T
T
EV
EV
EV
EV
EV
T
T
D
D
O
TX
0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 MR Reset
RW R RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Transmitter Timeout Protection Test.

BUS A and BUS B transmitters both have continuously running
watchdog timers that prevent continuous transmission beyond 663μs.
This bit is used to test the transmitter timeout protection feature. The
following host initiation sequence needs to occur to activate the test:
• Assert the TEST pin.
• Write logic “1” to TXTEST bit 15 (the test pin may now be
negated).
15 TXTEST R/W 0 • On the next host access, write logic “0” to TXTEST bit 15.
Following the host initiation sequence, bit 14 will be set and the next
RT transmission or response will attempt to transmit 35 MIL-STD-1553
data words with incrementing data count, totaling 700μs. If the
transmitter timeout protection is functioning correctly, the transmission
will stop after 663μs. If enabled, this will also result in Loopback Fail
Interrupt bits 12 or 11 being set in the “Hardware Pending Interrupt
Register (0x0006)”.
Note: This bit will be reset when read and always reads back logic “0”.
Transmitter Timeout Protection Test Pending.
14 TXTSTPND R/W 0 This bit is set when the host initiates a transmitter timeout protection
test. When the test begins on the next transmission, this bit clears
automatically.

31
HI-6138
Device ID
13 − 12 DEVID[1:0] R 11
These bits read 11 for HI-6138 following reset.
Revision ID.
11 − 8 REVID[3:0] R/W 0001
Following Reset, these bits will read 0001, the current revision ID.
Mode 1760 Status.

This bit is set when the MODE1760 pin was high at MR rising edge,
so the device is operating in 1760 mode (see “MIL-STD-1760: Busy
Status Assertion After Power-Up”). The host may read this bit to
confirm the device is operating in 1760 mode. Once in 1760 mode,
the RT immediately responds to any valid command (with matching
RT address) with BUSY bit set in the Status Word. No data words are
transmitted. No interrupts or logging of data occurs. Such responses
7 MODE1760 R/W 0 can occur during power-up RAM self-test, autoinitialization from
EEPROM or host-written register and RAM initialization.
There are three ways to exit 1760 mode and clear this bit:
1. write “1” to this register bit,
2. write “1” to the RTSTEX bit 4 in “Master Configuration Register 1
(0x0000)”, or
3. drive the MODE1760 input pin to logic “0” state.
6−5 Reserved R/W 0 These bits are not used and read logic 0.
RT Terminal Flag Test

This bit should normally remain logic 0. If this bit is set, the RT
responds to valid non-broadcast commands with the TF bit set in its
4 TFTEST R/W 0
Status Word.
Note: Use the “Remote Terminal MIL-STD-1553 Status Word Bits
Register (0x001A)” to control state of the Terminal Flag status bit.
Watchdog Timer Transmitter Timeout Terminal Flag
3 WDTF R/W 0 If this bit is set, watchdog timer transmitter timeout will cause the
Terminal Flag status bit 0 in “Remote Terminal MIL-STD-1553 Status
Word Bits Register (0x001A)” to be set.
Watchdog Timer Transmitter Timeout Transmit Inhibit

If this bit is set, watchdog timer timeout on BUS A or BUS B will cause
transmission to be inhibited on the corresponding bus.
If timeout occurs on BUS A, RTINHA bit 13 will be set in “Remote
Terminal Configuration Register (0x0017)”.
2 WDTXINH R/W 0 If timeout occurs on BUS B, RTINHB bit 12 will be set in “Remote
Terminal Configuration Register (0x0017)”.
Note: If WDTXINH bit 2 is NOT set, then watchdog timer timeout
will stop a transmission on BUS A or BUS B after 663μs for the next
transmission only. WDTXINH bit 2 must be set to inhibit subsequent
transmissions on BUSA or BUS B.

32
HI-6138
Dynamic Bus Control Masked Status Bit Flag
1 DBCMSTAT R/W 0 If this bit is set and the RT responds to a MC0 (Mode Code 0 Dynamic
Bus Control), the Masked Status Bit 7 of the “BC Block Status Word”
will be set if the RT Status Word DBCA bit 1 is set.
BC to RT/MT Digital Loopback Test
0 BCLBK R/W 0 Setting this bit enables BC to RT and MT digital loopback testing. No
loopback activity is transmitted to the bus. See Sections 21.2.6 and
21.2.7 for more details on digital loopback testing.
9.3. Master Status and Reset Register (0x0001)

E
e T
M ET
TM IV
TM d
TO d
TR d
es d
TI d
TR N
es E
R rve
AU rve
R rve
R erve
R rve
R ES
R DY
M E
R KE
BC ES
M CT
R IP
BC IP
R IP
IF
EE H
e
e
e
N
AM
C
EA
A
es
es
es
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register has a combination of read only and read-write bits. This register is cleared after MR pin master
reset, but is unaffected by assertion of MTRESET, RTRESET register bits.
The READY output pin reflects the state of this register bit. READY
is low when auto-initialization, a soft reset caused by bit 12~10
assertion, or built-in test is underway. Host access to device registers
15 READY R 0 or RAM is locked out while READY is low. While READY = 0, any host
read access returns the value in this register, regardless of address
provided. When READY goes high, the host may access registers and
RAM.
14 Reserved R 0 This bit is not used.
Auto-Initialization Enable Status.
13 AUTOEN R 0 This bit reflects the state of the AUTOEN input pin that applied at the
rising edge on the MR Master Reset input pin. If the register bit is high,
auto-initialization was performed following MR reset.
Bus Monitor Reset.

When written to logic 1, this bit initiates Bus Monitor reset. This bit
remains high until reset is complete. While this bit remains high, the
12 MTRESET R/W 0 READY output pin and register bit 15 are held low, host RAM and
register access is suspended. While READY = 0, any host read access
returns the value in this register, regardless of address provided. Upon
reset completion, this bit self-clears to logic 0, the READY pin goes
high and host read/write access is restored.

33
HI-6138
Remote Terminal Reset.

When written to logic 1, this bit initiates RT reset by clearing the
RTSTEX Start Execution bit in the “Master Configuration Register
1 (0x0000)”, then performing the RT soft reset actions described in
“Reset and Initialization” on page 198. This bit remains high until
10 RTRESET R/W 0 reset is complete. While this bit remains high, the READY output pin
and register bit 15 are held low, host RAM and register access is
suspended. While READY = 0, any host read access returns the value
in this register, regardless of address provided. Upon reset completion,
this bit self-clears to logic 0, the READY pin goes high and host read/
write access is restored.
BC Message in Process.
9 BCMIP R 0 This bit is high when the BC is processing a MIL-STD-1553 message.

Falling edge occurs at message completion, after register and RAM
buffer updates.
BC Active.
8 BCACTIVE R 0 This bit is high when the BC is enabled and running. It will read logic
1 during MIL-STD-1553 message processing and during programmed
delays.
Bus Monitor Message in Process.

7 MTMIP R 0 This bit is set when a valid MIL-STD-1553 command is decoded, and is
reset upon monitored message completion.
Remote Terminal Message in Process.

4 RTMIP R 0 This bit is set when a valid MIL-STD-1553 command is decoded for the
RT, and is reset upon message completion.
Remote Terminal Bus Inhibited.

This bit is high when one bus is inhibited for RT due to execution of a
2 RTINH R 0 “bus shutdown” mode code command. The shut-down bus is identified
in the RT BIT (built-in test) Word Register (see page 131). Shut-down
can be ended by “bus shutdown override” mode code command, MR
reset or setting the RTRESET bit in this register.

34
HI-6138
EEPROM Checksum Error.

This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as RT or MT soft reset with auto-initialization.
1 EECKE R 0 The EECKE bit is set (as well as bit 14 in the “Hardware Pending
Interrupt Register (0x0006)” on page 41) when a serial EEPROM
checksum failure occurs. Such failure may occur during full auto-
initialization after MR master reset, or during execution of a partial,
terminal-specific reset after assertion of the RTRESET or MTRESET
bits in this register.
RAM Initialization Fail Interrupt.

This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as terminal-specific partial auto-initialization
during RT or MT soft reset.
0 RAMIF R 0 The RAMIF bit is set (as well as bit 13 in the “Hardware Pending
Interrupt Register (0x0006)” on page 41) when one or more
initialized RAM locations do not match their two corresponding serial
EEPROM byte locations. Such failure may occur during full auto-
initialization after MR master reset, or during execution of a partial,
terminal-specific reset after assertion of the RTRESET or MTRESET
bits in this register.
9.4. Overview of Interrupts

For interrupt management, the host accesses up to seven registers and a 64-word circular Interrupt Log Buffer in RAM.
The log buffer and the Interrupt Count & Log Address Register are utilized in any system design involving interrupts.
In addition, there are four 3-register groups, identified by terminal function. One 3-register group is for Hardware
interrupts; this register triplet is always active. The other 3-register groups are only active when the corresponding
terminal functions are enabled; these are the interrupt register triplets used for Bus Controller, Bus Monitor and Remote
Terminal interrupts.
Each interrupt register triplet for BC, SMT, RT or Hardware consists of

• An Interrupt Enable Register to enable and disable interrupt event recognition
• A Pending Interrupt Register to capture the occurrence of enabled interrupt events
• An Interrupt Output Enable Register selectively enables IRQ output to host when enabled interrupts occur
Within each register triplet, corresponding register bits are mapped to the same interrupt-causing event. Initialize the
Interrupt Enable Register to select interrupt-causing events heeded by the HI-6138; most applications utilize just a
subset of the available interrupt options. Interrupt-causing events are ignored if their corresponding bits are reset in
the Interrupt Enable Register. Setting an Interrupt Enable register bit from 0 to 1 does not trigger interrupt recognition
for events that occurred while the bit was zero.
The next datasheet sections describe interrupt features, namely the Interrupt Log Buffer, the Interrupt Count & Log
Address Register and the Hardware Interrupt register triplet.

35
HI-6138
9.5. Hardware Interrupt Behavior

Behavior described here for Hardware Interrupts closely resembles the behavior for the BC, RT and SMT interrupt
register triplets, described later in the corresponding sections of this datasheet.
When an enabled hardware interrupt event occurs, the Interrupt Log Buffer is updated and a bit is set in the “Hardware
Pending Interrupt Register (0x0006)”. This action takes place only if the bit for the interrupt-causing event was already
set in the “Hardware Interrupt Enable Register (0x000F)”. The host can poll the “Hardware Pending Interrupt Register
(0x0006)” to detect occurrence of hardware interrupts, indicated by non-zero value. When the host reads the “Hardware
Pending Interrupt Register (0x0006)”, it automatically clears to 0x0000.
When an enabled hardware interrupt event occurs, if the corresponding bit is also set in the “Hardware Interrupt Output
Enable Register (0x0013)”, the IRQ output is asserted to alert the host. Thus, the “Hardware Interrupt Output Enable
Register (0x0013)” establishes two interrupt priority levels for hardware events: high priority interrupts generate an
IRQ signal output, while low priority interrupts do not. The host detects low priority interrupts by polling the “Hardware
Pending Interrupt Register (0x0006)”.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the Hardware,
BC, RT or MT Interrupt Output Enable registers. Multiple interrupt-causing events can occur simultaneously, so each
IRQ output assertion can result from one or more interrupt conditions.
When the host receives an IRQ signal from the device, it identifies the event (or events) that triggered the interrupt.
The host has two options: (a) go to the Interrupt Log Buffer (using the method described in “9.6. Interrupt Count & Log
Address Register (0x000A)” and “9.7. Interrupt Log Buffer”), or (b) use a hardware-assisted scheme using the three
low order bits in the “Hardware Pending Interrupt Register (0x0006)” to identify new interrupt(s).
For the second method, the host reads the “Hardware Pending Interrupt Register (0x0006)”. While bits 15-3 in this
register identify hardware interrupt conditions, the three low-order register bits indicate zero vs. non-zero status for
the BC, RT and MT Pending Interrupt Registers. If any of these bits is logic 1, the corresponding Pending Interrupt
Register has one or more interrupt flags set. Any combination of these three bits may be set, or all three bits may be
zero, if only hardware interrupt(s) occurred. When the host reads any of the four Pending Interrupt registers, the read
access self-resets the register to 0x0000. Thus, the host should retain the read value from the “Hardware Pending
Interrupt Register (0x0006)” when 1 or more bits are non-zero in the bit 2-0 range. These bits indicate zero vs. non-
zero status for the BC, RT and MT Pending Interrupt Registers:
• When bits 2-0 in the “Hardware Pending Interrupt Register (0x0006)” read 000, there are no new interrupts in the
BC, RT and MT Pending Interrupt Registers.
• When BCIP (BC Interrupt Pending) bit 0 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “Bus
Controller (BC) Pending Interrupt Register (0x0007)” contains a nonzero value. The host can read the “Bus
Controller (BC) Pending Interrupt Register (0x0007)” Register to identify the specific bus controller interrupt
event(s).
• When MTIP (SMT Interrupt Pending) bit 1 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “SMT
Bus Monitor Pending Interrupt Register (0x0008)” contains a nonzero value. The host can read this register to
identify the specific bus monitor interrupt event(s).
• When RTIP (RT Interrupt Pending) bit 2 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)” contains a nonzero value. The host can read the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)” to identify specific RT interrupt event(s).
When polling the Pending Interrupt registers to identify low priority interrupts that do not assert the IRQ output, the
same decoding method can be applied. A single read of the “Hardware Pending Interrupt Register (0x0006)” reveals
zero vs. non-zero status of all Pending Interrupt registers.
Alternately, the host can poll the “Interrupt Count & Log Address Register (0x000A)” to identify low priority interrupts
that do not assert the IRQ output. Bits 15:9 in this register contain a 7-bit count value indicating the number of
interrupts logged (0 - 127) since the “Interrupt Count & Log Address Register (0x000A)” was last read. Although the
“Interrupt Log Buffer” only holds data from the last 32 interrupts, register bits 15:9 count beyond 32 for buffer overrun

36
HI-6138
detection. Counting stops at 127. Register bits 15:9 are reset automatically when the host reads the “Interrupt Count
& Log Address Register (0x000A)”.
9.6. Interrupt Count & Log Address Register (0x000A)

MSB Interrupt Count MSB Interrupt Log Address
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is read-only and is fully maintained by logic. The register contains 0x0180 after error-free MR pin
master reset. It is not affected by assertion of MTRESET, RTRESET bits in the “Master Status and Reset Register
(0x0001)”. Note: Four bits in the “Hardware Interrupt Enable Register (0x000F)” come out of MR master reset fully
enabled (see 9.8.1). If error occurs after reset to trigger one of these 4 interrupts, the post-reset value in the register
will not be 0x0180. The upper bits will reflect 1 to 4 interrupts have occurred (count left-shifted 9 places) and the lower
bits (ranging from 1 to 4 interrupts) will reflect an even pointer address of 0x182, 0x184, 0x186 or 0x188.
The value in Interrupt Log Address Register bits 8:0 is a 9-bit address pointer to the circular 64-word “Interrupt Log
Buffer”, located in RAM. Register bits 8:6 are always 1-1-0 so the 9-bit address pointer ranges from 0x0180 to 0x01BE.
This pointer indicates the storage address for two information words that will be stored for the next-occurring interrupt.
The value is always even since two words are stored for each interrupt.
Upper register bits 15:9 contain a 7-bit count value for the number of interrupts logged (0 − 127) since the Interrupt
Count & Log Address Register was last read. Although the circular “Interrupt Log Buffer” only retains data from the last
32 interrupts, counting continues beyond 32 so the host can detect circular buffer overrun. Bits 15:9 stop incrementing
at full count (127 interrupts) and automatically reset to zero when the host reads this register.
After MR master reset, the HI-6138 initializes this register to 0x0180, an interrupt count of zero and Interrupt Log Buffer
address of 0x180. After reset, the first interrupt stores words at buffer addresses 0x0180 and 0x0181. Subsequent
interrupts store word pairs at sequential addresses. Information words for the 32nd interrupt are stored in last two
buffer addresses 0x01BE and 0x01BF, and the Interrupt Log Address “rolls over” to read 0x0180, where interrupt
information for the 33rd post-reset interrupt will be stored.
9.7. Interrupt Log Buffer

Shown in Figure 3, the Interrupt Log Buffer is a circular 64-word buffer in RAM, residing at address range 0x0180
to 0x01BF. Device logic stores two information words in the buffer for each enabled interrupt that occurs, so buffer
size dictates storage for up to 32 interrupt events. After the 32nd, 64th, 96th,... interrupt occurs, the buffer address
pointer (bits 8:0 in register 0x000A) “wraps around” to buffer start address 0x0180 and subsequent interrupts overwrite
previously stored interrupt information (see “Interrupt Count & Log Address Register (0x000A)” on page 37).
Interrupt logic stores two words in the Interrupt Log Buffer for each enabled interrupt that occurs: an Interrupt
Identification Word and an Interrupt Address Word. The Interrupt Identification Word (IIW) identifies the occurring
interrupt type (BC, MT or RT) using the same format as the three low order bits in the “Hardware Pending Interrupt
Register (0x0006)”, and the interrupt itself by matching bits [15:3] to the applicable Pending Interrupt Register. More
than one bit may be asserted in an Interrupt Identification Word. For example, IBR (interrupt broadcast received) and
MERR (interrupt message error) can occur for the same RT message. One assertion of the INT output pin alerts the
host when concurrent message interrupts occur.

37
HI-6138
The log buffer Interrupt Address Word varies, depending on the interrupt type. Hardware interrupts are not directly
linked with command or message processing. Hardware interrupts write an Interrupt Address Word value of 0x0000,
except when a RAMPF (RAM Parity Fail) interrupt occurs (see Table 4 below). For BC or SMT interrupts, the Interrupt
Address Word (IAW) identifies the message in which the interrupt occurred. For RT interrupts, the Interrupt Address
Word (IAW) identifies the start location of the Descriptor Table entry for the message in which the interrupt occurred:
Table 4. Format of IIW and IAW in Interrupt Log Buffer
Interrupt Type Interrupt Identification Word (IIW) Interrupt Address Word (IAW)
Always 0x0000.
Matches format of “Hardware Pending Interrupt EXCEPTION: When a RAMPF (RAM Parity
Hardware Fail) interrupt occurs, the IAW will contain
Register (0x0006)” on page 41
the address of the location in RAM where the
parity failure occured.
Bits 2:0 will match bits 2:0 of the “Hardware

Pending Interrupt Register (0x0006)” on page
41, indicating the interrupt type. For a BC
Bus Controller interrupt, bit 0 will be set. Points to the address of the Opcode in the
(BC) BC Instruction List that triggered the interrupt.
Bits 15:3 will match bits 15:3 of the “Bus Controller
(BC) Pending Interrupt Register (0x0007)” on page
95, indicating which interrupt occured.

41, indicating the interrupt type. For a MT An SMT Command Buffer address, points
Simple Bus interrupt, bit 1 will be set. to the Block Status Word of the message in
Monitor (SMT)
Bits 15:3 will match bits 15:3 of the “SMT Bus which interrupt occurred
Monitor Pending Interrupt Register (0x0008)” on
page 116, indicating which interrupt occured.

41, indicating the interrupt type. For a RT
interrupt, bit 2 will be set.
Bits 15:3 will match bits 15:3 of the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)”
on page 135, indicating which interrupt occured.
RT Descriptor Table address pointing to the
Remote Terminal
EXCEPTION: If INTBUSY bit 2 is set in “Extended start location of the Descriptor Table entry of
RT
Configuration Register (0x004D)”, then bit 9 of RT the message in which interrupt occurred
Interrupt Information Word serves as WASBUSY
status flag, asserted if terminal was BUSY when
message interrupt occurred.
See “Extended Configuration Register (0x004D)”
on page 44.
Note: Busy status is not an interrupt causing
event.
For a given terminal (BC, SMT, or RT) multiple interrupts can be enabled, and two or more interrupts can occur in a
single message. There will be a single 2-word Log Buffer update and the Interrupt Information Word will have one
bit set for each occurring interrupt. Simultaneous interrupts for one terminal (having interrupt output enabled) are
logically-ORed, resulting in a single assertion of the IRQ output to the host.

38
HI-6138
When operating with two or more enabled terminal devices (BC, SMT, or RT), simultaneous interrupts can occur in
the same message for multiple terminals. Each terminal device with occurring interrupt(s) will have its own 2-word
Log Buffer update. Simultaneous interrupts for multiple terminals (having interrupt output enabled) are logically-ORed,
resulting in a single assertion of the IRQ output to the host. See Sections “Bus Controller Interrupt Registers and Their
Use” on page 94, “SMT Bus Monitor Interrupt Registers and Their Use” on page 115 and “Remote Terminal Inter-
rupt Registers and Their Use” on page 134 for further information.

39
HI-6138
0x01BF INTERRUPT 32 Interrupt Address Word
0x01BE INTERRUPT 32 Interrupt Information Word The Interrupt Log Address Register
points to this address after Interrupt
0x01BD INTERRUPT 31 Interrupt Address Word 31 event occurs. Upon Interrupt 32
completion, device logic reinitializes
0x01BC INTERRUPT 31 Interrupt Information Word the log address pointer to 0x0180
before Interrupt 33 is processed.
0x01BB INTERRUPT 30 Interrupt Address Word
0x01BA INTERRUPT 30 Interrupt Information Word
0x01B9 INTERRUPT 29 Interrupt Address Word
0x01B8 INTERRUPT 29 Interrupt Information Word
0x018B INTERRUPT 6 Interrupt Address Word
0x018A INTERRUPT 6 Interrupt Information Word
0x0189 INTERRUPT 5 Interrupt Address Word
0x0188 INTERRUPT 5 Interrupt Information Word
0x0180 INTERRUPT 1 Interrupt Information Word Interrupt Log Address Register

is initialized by device logic to
point to this address after
hardware reset (MR) or software reset
Figure 3. Fixed Address Mapping for Interrupt Log Buffer

40
HI-6138
9.8. Hardware Interrupt Registers
9.8.1. Hardware Interrupt Enable Register (0x000F)

D F
FA / W P
TX
LB IF AM
R
TT d
d
es d
es d
TA d
T O
es O
C T
AM /
R erve
ve
R rve
R rve
R rve
BC TM
R TM
M TM
BC TR
R KE
EE IIN
R TR
R PF
er
FB
e
e
e
TT
SP
TT
es
es
LB
M
H
0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 MR Reset
RW R Host Access * Bits 4 - 0 are read-only and cannot be modified by host.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
9.8.2. Hardware Pending Interrupt Register (0x0006)

D F
FA / W P
TX
LB IF AM
R
TT d
TA d
T O
es O
C T
AM /
R erve
R rve
BC TM
R TM
M TM
BC TR
R KE
EE IIN
R TR
R PF
FB
P
IP
e
P
TT
SP
TT
T
es
TI
TI
BC
LB
M
M
H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R R* Host Access * Bits 2 - 0 are set for pending interrupts
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit from RT, MT or BC
9.8.3. Hardware Interrupt Output Enable Register (0x0013)

D F
FA / W P
TX
LB IF AM
R
TT d
d
es d
es d
TA d
T O
es O
C T
AM /
R erve
ve
R rve
R rve
R rve
BC TM
R TM
M TM
BC TR
R KE
EE IIN
R TR
R PF
er
FB
e
e
e
TT
SP
TT
es
es
LB
M
H
0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 MR Reset
RW R Host Access * Bits 4 - 0 are read-only and cannot be set by host.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These three registers govern hardware interrupt behavior. As explained earlier, bits 2-0 in the Hardware Pending
Interrupt Register are set whenever interrupt bits are set in the other three pending interrupt registers (RT, MT and
BC). The table below first describes the common bits 15-3 in all three registers and then describes register-to-register
differences for bits 2-0.
Host SPI Interrupt.

15 HSPIINT R/W 0 An unexpected number of SCK clock pulses occured during a SPI
transaction.

41
HI-6138
EEPROM Checksum Error Interrupt.

This function only applies when the AUTOEN input pin is logic 1 at rising
edge of MR Master Reset. This enables auto-initialization from serial
EEPROM, as well as RT soft reset with auto-initialization. This bit is logic 1
in the “Hardware Interrupt Enable Register (0x000F)” and in the “Hardware
EECKE Interrupt Output Enable Register (0x0013)” after MR master reset.
The EECKE bit is set in the “Hardware Pending Interrupt Register (0x0006)”
(as well as bit 1 in the “Master Status and Reset Register (0x0001)” when
a serial EEPROM checksum failure occurs during auto initialization, or
14 R/W 1 execution of a partial reset caused by assertion of the RTRESET bit in the
“Master Status and Reset Register (0x0001)”.
RAM Parity Fail Interrupt.

The RAMPF bit will be set to logic “1” when the device fails RAM parity
check. RAM data errors are uncorrectable.
RAMPF When bit 14 is asserted in the “Hardware Pending Interrupt Register
(0x0006)”, the host can distinguish an EECKE interrupt from a RAMPF
interrupt by reading the “Master Status and Reset Register (0x0001)”.
EECKE bit 1 in that register will be logic 1 for EECKE interrupt, logic 0 for
RAMPF interrupt.
RAM Initialization Fail Interrupt.

This function only applies when the AUTOEN input pin is logic 1 at rising
edge of MR Master Reset. This enables auto-initialization from serial
EEPROM, as well as RT soft reset with auto-initialization. This bit is logic 1
in the “Hardware Interrupt Enable Register (0x000F)” and in the “Hardware
Interrupt Output Enable Register (0x0013)” after MR master reset.
RAMIF
The RAMIF bit is set in the “Hardware Pending Interrupt Register (0x0006)”
(as well as bit 0 in the “Master Status and Reset Register (0x0001)”) when
one or more initialized RAM locations do not match their two corresponding
13 R/W 1 serial EEPROM byte locations. Such failure occurs during auto initialization,
or execution of a partial reset caused by assertion of the RTRESET bit in
the “Master Status and Reset Register (0x0001)”.
Transmitter Watchdog Timeout

BUSA and BUSB transmitters each have a watchdog timer to prevent
continuous transmission beyond 663μs. If WDTX is set in the “Hardware
WDTX Interrupt Enable Register (0x000F)” , the corresponding bit will be set in
the “Hardware Pending Interrupt Register (0x0006)” and the Interrupt Log
Buffer is updated. If bit 13 is set in the “Hardware Interrupt Output Enable
Register (0x0013)”, an interrupt is generated at the IRQ pin.

42
HI-6138
Loopback Fail Bus A Interrupt (LBFA) − Valid only for RT

Loopback Fail Bus B Interrupt (LBFB) − Valid only for RT
For all words transmitted by the RT, the device checks MIL-STD-1553 word
validity for the subsequently received/decoded word detected on the bus.
This includes sync, encoding, bit count and parity checking. The last word
12 LBFA in each message transmitted by the RT is also checked for data matching.
R/W 0
11 LBFB The LBFA bit is set each time loop-back detects an invalid or mismatched
word on Bus A. The LBFB bit is set each time loop-back detects an invalid
or mismatched word on Bus B.
NOTE: Once LBFA or LBFB are set by a loopback failure on Bus A or Bus
B respectively, they remain set (persistent) until cleared by reading the
“Hardware Pending Interrupt Register (0x0006)”.
MT Time Tag Counter Rollover.
10 MTTTRO R/W 0 The Bus Monitor time tag counter rolled over from full count to zero.
Depending on options selected in the “Time Tag Counter Configuration
Register (0x0039)”, the MT time count may be either 16 or 48 bits.
BC Time Tag Counter Rollover.
9 BCTTRO R/W 0 The Bus Controller time tag counter rolled over from full count to zero.
Depending on options selected in the “Time Tag Counter Configuration
Register (0x0039)”, the BC time count may be either 16 or 32 bits.
RT Time Tag Match.

7 RTTTM R/W 0 The 16-bit Remote Terminal time tag counter incremented to a count
matching the contained value in the RT Time Tag Reload / Match Register.
MT Time Tag Match.

6 MTTTM R/W 0 The Bus Monitor time tag counter incremented to a count matching the
contained value in the MT Time Tag Match Registers.
BC Time Tag Match.

5 BCTTM R/W 0 The Bus Controller time tag counter incremented to a count matching the
contained value in the BC Time Tag Match Register(s).
RT Terminal Address Parity Fail Interrupt.
3 RTAPF R 1 The Remote Terminal address and parity bits (latched into the RT
Operational Status Register (see page 125) at rising edge of MR) do not
exhibit odd parity (do not have an odd number of bits having logic 1 state).

43
HI-6138
For the Hardware Interrupt Enable Register and the Hardware Interrupt Output Enable Register only
2−0 Reserved Bits 2-0 cannot be written and read back 000.
For the Hardware Pending Interrupt Register only
RT Interrupt Pending.
2 RTIP R 0 When this bit is high, one or more bits are set in the “Remote Terminal (RT)
Pending Interrupt Register (0x0009)”. The host can read that register to
determine the RT interrupt event(s).
MT Interrupt Pending.
1 MTIP R 0 When this bit is high, one or more bits are set in the “SMT Bus Monitor
Pending Interrupt Register (0x0008)”. The host can read that register to
determine the MT interrupt event(s).
BC Interrupt Pending.
0 BCIP R 0 When this bit is high, one or more bits are set in the BC Pending Interrupt
Register. The host can read that register (0x0007) to determine the BC
interrupt event(s).
9.9. Extended Configuration Register (0x004D)

Q FF
TB T
PB Y
es d
IR d
FF
IN S
R erve
C rve
D US
IR TO
BC
O
e
es
R
X X X X X X X X X X 0 0 0 0 0 0 MR Reset
R/W Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This register contains four bits which provide global options for RT operation.
Bit No. Mnemonic Function
15 − 6 ----- Not Used.
5−4 Reserved Do not use. Setting these bits may cause unpredictable behavior.
Circular Buffer Mode Gap Error / Broadcast Flag.

When CIRBCST = 0, bit 13 GAP/BCAST in Receive and Transmit “Subaddress Message
Information Words” on page 162 and Receive and Transmit “Mode Command Message
3 CIRBCST Information Words” on page 166 is a Gap Error flag.
When CIRBCST = 1, bit 13 GAP/BCAST in Receive and Transmit “Subaddress Message
Information Words” on page 162 and Receive and Transmit “Mode Command Message
Information Words” on page 166 is a Broadcast flag.

44
HI-6138
Report terminal Busy status for RT message interrupts; set WASBUSY flag bit 9 in log
buffer Interrupt Identification Word. See “Interrupt Log Buffer” on page 37.
Setting INTBUSY = 1 causes the WASBUSY status bit 9 to be set in the RT Interrupt
Identification Word (IIW) when an enabled interrupt event occurs with RT Busy status.
Therefore, RT subaddresses or mode codes with enabled message interrupts can
optionally report when Busy status applied during those events. For example, assume the
RT Rx subaddress 1 Interrupt When Accessed event (IWA) is enabled. If RT subaddress 1
sees a legal, valid receive message but the RT is Busy, the IWA and WASBUSY flags are
both set in the Interrupt Log Buffer’s written Interrupt Identification Word. If RT is not Busy,
2 INTBUSY
only the IWA flag is set in the written IIW.
When INTBUSY is reset, terminal Busy status for interrupts is not reported; the WASBUSY
status bit in the logged RT Interrupt Identification Word is always 0.
Note 1: The Interrupt Log Buffer is updated only when enabled interrupt events occur. By
itself, RT Busy status is not an interrupt-causing event.
Note 2: INTBUSY bit 2 does not affect the “Remote Terminal (RT) Pending Interrupt
Register (0x0009)” on page 135; register bit 9 is reserved. Only WASBUSY bit 9 in the
Interrupt Log Buffer Interrupt Identification Word (IIW) is affected.

45
HI-6138
Bit 1 DPBTOFF disables ping pong DPB pointer toggle when the received valid command
is illegal, or when a message occurs with Busy status.
When using ping pong buffers, the DPB buffer pointer never toggles for valid, legal
messages ending in error. Setting DPBTOFF = 1 also disables ping pong DPB pointer
toggle when the received valid command is illegal, or when a message occurs with Busy
status.
For RT subaddresses using ping pong data buffers (see “Ping-Pong Data Buffering” on
page 170), the device alternates message data storage between Data Buffer A and Data
Buffer B, on a message-by-message basis. The Descriptor Table Control Word DPB bit
10 indicates the data buffer to be used by the next-occurring message to this subaddress
(see Section “16.4. Descriptor Table” on page 145). When the DPB bit is logic 0, the next
message uses Data Buffer A; when DPB is logic 1, the next message uses Data Buffer B.
Set DPBTOFF = 1 to prevent toggle of the Control Word DPB bit for Illegal or RT Busy
messages, as well as valid, legal messages ending in error. The DPB pointer therefore
remains static until the next successful message is received, which overwrites the
Message Information Word and Time Tag Word in the current ping pong buffer location.
Note that receive and transmit subaddresses may have both legal and illegal word counts,
1 DPBTOFF dictated by the Command Illegalization Table. For such subaddresses, DPB toggle only
occurs when a supported legal word count message is transacted.
When the DPBTOFF option bit is set to modify behavior for ping pong buffers, DPB
toggle is disabled for valid messages that are illegal, or legal messages resulting in RT
Busy or Message Error status. Important note: message data words in the “next-used”
(designated active) buffer are NOT altered for incomplete (illegal, Message Error or RT
Busy) messages. However the buffer Message Information and Time Tag Words are
updated in that message data buffer so the host can detect when such messages
occur. Bits 10:8 in the buffer Message Information Word indicate Message Error, Busy
and/or Illegal status. When any of these 3 bits are set, the accompanying data should
always be disregarded (whether or not the DPBTOFF option is used).
To maintain data integrity, the primary benefit of DPBTOFF = 1 is that the complemented
DPB pointer always indicates the last-transacted “good” data set. For example if DPB is
logic 0, the last successful message used Data Buffer B.
The default condition after power-on reset in register 0x4D contains 0x0000. Thus
configuration bit DPBTOFF is logic-0. For this case, the Control Word DPB bit toggles
after completion of error-free messages (expected), but also illegal commands and
messages resulting in Message Error or Busy status.

46
HI-6138
Suppress IRQ interrupt pin assertion for enabled RT message interrupts when the
command is illegal or the message results in RT Busy status.
RT Interrupt Registers are described on page 135. Globally enable RT interrupt types
(MERR, IWA, IBR) by setting bits in the “Remote Terminal (RT) Interrupt Enable Register
(0x0012)”. Enable these interrupts for individual receive or transmit subaddresses (or
mode commands) by setting bits in their Descriptor Table Control Words. When an
enabled RT interrupt event occurs, the corresponding “type” bit is set in the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)” and “Interrupt Log Buffer” on
0 IRQOFF
page 37 is updated. In addition, the IRQ output pin is normally asserted (low) if the
corresponding bit is also set in the “Remote Terminal (RT) Interrupt Output Enable
Register (0x0016)”. This IRQOFF option bit modifies interrupt output behavior.
The IRQOFF option bit prevents nuisance IRQ pin assertion when the command is
illegal or when the message occurs with RT Busy status. Note that receive and transmit
subaddresses may have both legal and illegal word counts, dictated by the Command
Illegalization Table. For such subaddresses, an interrupt is only generated when a
supported legal word count message is transacted.
9.10. Time Tag Counter Configuration

Each device (RT, BC or MT) has an independent time tag counter used for time-stamping messages. In the “Time Tag
Counter Configuration Register (0x0039)”, bits 2-0 select the clock source for the RT and time tag counter. The same
clock source is shared by the Bus Controller. The host controls the free-running RT time tag counter using bit pairs 9-8
in the “Time Tag Counter Configuration Register (0x0039)”. Here is a summary of host-initiated operations involving
the RT time tag counter:
a. Clearing the 16-bit RT time tag count to 0x0000.
b. Copying the RT Time Tag Utility Register value (see page 133) into the 16-bit RT time tag counter.
c. Copying the current 16-bit RT time tag count value into the RT Time Tag Utility Register.
The bus controller (BC) can operate using either a 16- or 32-bit time tag counter, selected using register bit 3, BCTT32,
in the “Time Tag Counter Configuration Register (0x0039)”. The BC time tag counter clock source is selected using
register bits 2-0. This common clock source is shared by the BC, and RT. Bit pair 13-12 is used for clearing BC time tag
counter, loading the counter with a 16- or 32-bit value contained in the “Bus Controller (BC) Time Tag Utility Register
(0x0045)” on page 93, or writing the current 16- or 32-bit BC time tag counter value to the “Bus Controller (BC) Time
Tag Utility Register (0x0045)”.
The free-running BC time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be
captured. In 32-bit time tag mode, the full count is captured by simultaneously loading two utility registers. Writing bits
13-12 in the Time Tag Counter Configuration Register initiates these operations. Here is a summary of host-initiated
operations involving the BC time tag counter:
a. Clearing a 16- or 32-bit BC time tag count, whichever is enabled.
b. When 16-bit BC time tag count is enabled,
• loading the 16-bit BC time tag counter with the 16-bit value contained in the “Bus Controller (BC) Time
Tag Utility Register (0x0045)”
• capturing the current 16-bit BC time tag counter value to the “Bus Controller (BC) Time Tag Utility Register
(0x0045)”

47
HI-6138
c. When 32-bit BC time tag count is enabled,
• loading the 32-bit BC time tag counter with the 32-bit value contained in the register pair “Bus Controller
(BC) Time Tag Utility Register (0x0045)” and “Bus Controller (BC) Time Tag Utility High Register (0x0046)”.
• capturing the current 32-bit BC time tag counter value to the register pair “Bus Controller (BC) Time Tag
Utility Register (0x0045)” and “Bus Controller (BC) Time Tag Utility High Register (0x0046)”
The bus monitor (MT) can operate using either a 16- or 48-bit time tag counter, selected using MT Configuration
Register bits 1-0. When using 16-bit resolution, one register is adequate for holding time tag values. When using 48-bit
time tag count resolution, three 16-bit registers are needed for each stored time tag count. The MT time tag counter
clock source is selected using bits 7-5 in the “Time Tag Counter Configuration Register (0x0039)”. The MT time tag
clock source is separate from the source shared by the BC and RT.
The free-running MT time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be
captured. In 48-bit time tag mode, the full count is captured by simultaneously loading three utility registers. Writing bits
15-14 in the “Time Tag Counter Configuration Register (0x0039)” initiates these operations.
Here is a summary of host-initiated operations involving the MT time tag counter:

a. Clearing a 16- or 48-bit MT time tag count, whichever is enabled.
b. When 16-bit MT time tag count is enabled,
• loading the 16-bit MT time tag counter with the 16-bit value contained in the “SMT Bus Monitor Time Tag
Utility Register (0x003D)”
• capturing the current 16-bit MT time tag counter value to the “SMT Bus Monitor Time Tag Utility Register
(0x003D)”
c. When 48-bit MT time tag count is enabled,
• loading the 48-bit MT time tag counter with the 48-bit value contained in the register triplet “SMT Bus
Monitor Time Tag Utility Register (0x003D)”, “SMT Bus Monitor Time Tag Utility Mid Register (0x003E)” and
“SMT Bus Monitor Time Tag Utility High Register (0x003F)”.
• capturing the current 48-bit MT time tag counter value to the register triplet “SMT Bus Monitor Time Tag
Utility Register (0x003D)”, “SMT Bus Monitor Time Tag Utility Mid Register (0x003E)” and “SMT Bus Monitor
Time Tag Utility High Register (0x003F)” when 48-bit MT time tag count is enabled
Host interrupts can be generated when any of the four time tag counters in the device reach preset values contained
in Time Tag Match registers. Refer to the Section 9.4.
9.11. Time Tag Counter Configuration Register (0x0039)

es d
TT d
TT 1
T 0
TT 2
TT 3
TT 1
T 0
T 1
R TA0
TT 1
M TA0
R erve
R rve
TT T32
M CK
BC CK
M CK
M CK
M TA
BC TA
BC TA
R TA
TT K1
TT K2
K0
e
TT
TT
C
C
C
es
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit read-write register is cleared after MR pin master reset, but is unaffected by assertion of MTRESET or
RTRESET register bits.
When written, register bits 15-8 work in pairs to initiate a particular action, such as clearing or loading one of these
counters. When written, register bits 15-8 self reset to zero after initiating the assigned action. Thus, bits 15-8 always
read logic 0. Register bits 7-0 are used for configuring the various time tag counters in the device. These bits will
read back the last value written by the host.

48
HI-6138
MT Time Tag Action Bits 1-0.

After performing the action below, these host-written bits self reset to 00:
Bits 15-14 Action
00 Do Nothing.
01 Reset 16- or 48-bit MT Time Tag count to zero.
Load the 16- or 48-bit value from SMT Time Tag Utility
10
Register(s) into the SMT Time Tag Count register(s).
Capture current 16- or 48-bit value in the SMT Time Tag

11
Count Register(s) into the SMT Time Tag Utility Register(s).
If the MT is using 16-bit time tag, the SMT Time Tag Counter uses a
single register address, 0x003A. The SMT Time Tag Utility Register used
for the load and capture operations is register address 0x003D.
15 MTTTA1
R/W 0 If the MT is using 48-bit time tag, the SMT Time Tag Counter uses three
14 MTTTA0 register addresses. The High-Mid-Low words are found at 0x003C,
0x003B and 0x003A respectively. The triplet of SMT Time Tag Utility
Register Triplet used for the load and capture operations is located at
register addresses 0x003F (High), 0x003E (Mid) and 0x003D (Low).
Bits 1-0 in the “SMT Configuration Register (0x0029)” select SMT 16-bit
or 48-bit time tag counting:
SMT Configuration
Time Tag Mode
Register, bits 1-0
01 16-bit time tag
11 48-bit time tag
When the MT is operating in Simple mode with 48-bit time tag, the
recorded Command Buffer entry for each 1553 message has eight 16-
bit words. When operating with 16-bit time tag, the recorded Command
Buffer entry for each 1553 message has four 16-bit words.

49
HI-6138
BC Time Tag Action Bits 1-0.

After performing the action below, these host-written bits self reset to 00:
Bits 13-12 Action
00 Do Nothing.
01 Reset 16- or 32-bit BC Time Tag count to zero.
Load the 16- or 32-bit value from BC Time Tag Utility

10
Register(s) into the BC Time Tag Count Register(s).
13 BCTTA1 Load the 16- or 32-bit value from the BC Time Tag Count
R/W 0 11
12 BCTTA0 Register(s) into the BC Time Tag Utility Register(s).
If BCTT32 register bit 3 equals 0, the BC is using 16-bit time tag. The
BC Time Tag Counter uses a single register address, 0x0043. The “Bus
Controller (BC) Time Tag Utility Register (0x0045)” is used for these
operations.
If BCTT32 register bit 3 equals 1 the BC is using 32-bit time tagging, so
the BC Time Tag Counter requires two 16-bit register addresses. The High
and Low BC time tag counter words are found at 0x0044 and 0x0043
respectively. The pair of BC Time Tag Utility Registers used for timer
operations are located at register addresses 0x0046 (High word) and
0x0045 (Low word).
11 − 10 Reserved R 0 These bits are not used.
RT Time Tag Action Bits 1-0.

After performing the RT time tag counter action below, these host-written
bits self reset to 00:
9 RTTTA1 Bits 9-8 Action

R/W 0
8 RTTTA0 00 or 11 Do Nothing.
01 Reset 16-bit RT Time Tag count to zero.
Load the 16-bit value from the RT Time Tag Utility Register
10
(0x004A) into the RT Time Tag Counter (0x0049).
MT Time Tag Clock Selection Bits 7-4.

These four bits select the clock source for the MT Time Tag Counters from
the following options:
Bits 7-6-5-4 MT Time Tag Counter Clock Source

7 MTTCK3
6 MTTCK2 0-0-0-0 Time Tag Counter Disabled.
R/W 0 0-0-0-1 External clock provided at the MTTCLK input pin.
5 MTTCK1 0-0-1-0 Internally generated 2μs clock.
4 MTTCK0 0-0-1-1 Internally generated 4μs clock.
0-1-0-0 Internally generated 8μs clock.
1-x-x-x Internally generated 100ns clock.

50
HI-6138
BC Time Tag 32-Bit Count Enable.

3 BCTT32 R/W 0 When the BCTT32 bit equals 0, the BC time tag counter is 16 bits.
When the BCTT32 bit equals 1, the BC time tag counter is 32 bits.
BC and RT Time Tag Clock Selection Bits 2-0.

These three bits select the clock source for the BC and RT Time Tag
Counters from the following options:
Bits 2-1-0 Time Tag Counter Clock Source

2 TTCK2
0-0-0 Time Tag Counter Disabled.
1 TTCK1 R/W 0 0-0-1 External clock provided at TTCLK input pin.
0 TTCK0 0-1-0 Internally generated 2μs clock.
0-1-1 Internally generated 4μs clock.

51
HI-6138
9.12. Memory Address Pointer Registers

The Serial Peripheral Interface (SPI) uses predefined 8-bit instruction op codes to perform a variety of predetermined
actions. Some op codes must be followed by two or more operand bytes, while other SPI codes perform their desired
action without additional operands. Examples of self-contained SPI op codes include the “Fast access” op codes used
for reading or writing registers at the low end of the address space.
“Fast access” op codes used for direct addressing contain embedded register addresses, but only work over a limited
address range.
• SPI reads to register addresses 0 through 0x000F (decimal 15) use an 8-bit op code of the form
0x00 + (Reg_Addr << 2) where Reg_Addr = 0 to 0xF before left-shifting two bits.
• SPI writes to register addresses 0 through 0x003F (decimal 63) use an 8-bit op code of the form
0x80 + Reg_Addr where Reg_Addr equals 0 to 0x3F.
The two “fast access” op codes use a dedicated memory address pointer to perform their duties without affecting
values contained in other Memory Address Pointer registers. The “fast access” Memory Address Pointer cannot be
read by the host, but is written each time a “fast access” op code is processed.
The HI-6138 uses a Memory Address Pointer for SPI reads to register addresses over 0x000F, or for SPI writes
to register addresses over 0x003F. For most SPI read and write operations, the starting memory address for the
requested operation is written to the Memory Address Pointer (or MAP) before the op code (using the MAP) is invoked.
In the case of a multiword data transfer involving a range of sequential addresses, the memory address pointer is
initialized with the starting (lowest) address. After the SPI transfers data from the first address, the memory address
pointer automatically increments to the next address. When read access occurs, the device prefetches the data stored
at the next address to support the fastest possible data rates. As long as the chip select stays low (asserted) and the
SPI master continues to provide serial clocks, data read/write transfers for sequential addresses continue until the chip
select is negated. Please refer to section “Host Serial Peripheral Interface (SPI)” on page 212, describing SPI host
access and the SPI op codes used for data transfer.
For flexibility in configuring the device, four independent Memory Address Pointers are available. These can be
assigned in any manner that supports application requirements. For example:
• To simplify data access while supporting concurrent terminal devices (BC, MT and RT), some devices may need
a dedicated Memory Address Pointer (MAP) while other devices may be able to share a MAP.
• Consider using a dedicated Memory Address Pointer for interrupt service routines. Many SPI operations are
multiword transfers that utilize the Memory Address Pointer auto-increment feature. If interrupts are enabled
during multiword transfers, a dedicated Memory Address Pointer for the interrupt service routine avoids corruption
of the MAP used by the interrupted routine.
Residing in the lower register address space, the four Memory Address Pointers can be read or written with a single
8-bit “fast access” op code (plus the desired 16-bit data value, when writing).
Just one of the four MAP registers is enabled at any time. Each of the four Memory Address Pointers has a dedicated
8-bit “MAP Select” op code that enables it by writing the “Master Configuration Register 1 (0x0000)”. Or the host can di-
rectly write the MAPSEL (Memory Address Pointer select) bits 11-10 in the “Master Configuration Register 1 (0x0000)”
to enable the desired MAP register. Full descriptions of SPI data transfer methods are provided later in this document.

52
HI-6138
The four memory address pointer registers are:
MAP1 Memory Address Pointer Register 0x000B

MAP2 Memory Address Pointer Register 0x000C
MAP3 Memory Address Pointer Register 0x000D
MAP4 Memory Address Pointer Register 0x000E
MSB Register Value LSB

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These 16-bit registers are read-write (except bit 15 MSB, which is Read-Only) and are fully maintained by the host.
These registers are cleared after MR pin master reset, but are unaffected by assertion of RTRESET or MTRESET bits
in the “Master Status and Reset Register (0x0001)”.
Each of these registers has a unique SPI op code that reads the MAP value in the register, and another op code that
writes a new MAP value into the register. See SPI op code table. The host selects the active MAP register by writing
the MAPSEL (memory address pointer select) bits 11-10 in the “Master Configuration Register 1 (0x0000)”, or by using
the four defined “MAP Select” SPI op codes, described in the section “Host Serial Peripheral Interface (SPI)” on page
212. The active MAP register contains the memory address used for SPI read write access to registers and RAM.
Please refer to Section 22 for a full description of the interface and the SPI instruction op codes.

53
HI-6138
10. BUS CONTROLLER − CONFIGURATION AND OPERATION

The HI-6138 can operate as an autonomous MIL-STD-1553 Bus Controller (BC), requiring minimal host processor
support. All MIL-STD-1553B error-checking is automatically performed, including RT response time, Manchester II
encoding, sync type, bit count, word parity, word count, responding RT address, and detection of the full range of pos-
sible error conditions encountered during BC operation. The device implements all MIL-STD-1553B message formats.
Message format is configurable on a message by message basis. Each message is individually programmable for
command type. Individual messages can be programmed for automatic retries on either bus, and interrupt requests
may be enabled or disabled.
The Bus Controller provides a flexible means for scheduling major and minor frames, allowing insertion of asynchro-
nous messages during frame execution. Upon error, individual messages can be programmed for one or two auto-
matic retries, and the BC can switch buses before retry occurs. Message data is separated from control and status
data, to serve the needs for double buffering in RAM and bulk data transfers.
Before Bus Controller operation can begin, the BCENA bit 12 in “Master Configuration Register 1 (0x0000)” on page
28 must be logic 1 to allow BC operation. All Bus Controller operational registers (see Section 11) must be properly
configured. The BC Instruction List in RAM must be initialized to define message sequencing and conditional execution,
and finally the host must assert BCSTRT bit 13 in the “Master Configuration Register 1 (0x0000)” to initiate execution
of Instruction List op codes. The following pages provide the necessary details for successful Bus Controller operation.
Figure 4 shows the registers and RAM resources utilized by the Bus Controller. All Bus Controller registers are fully
described in Section 11.
Initial control of BC message sequencing involves the “Bus Controller (BC) Instruction List Pointer (0x0034)”. Before
BC execution begins, the instruction list starting address is copied from the “Start Address Register for Bus Controller
(BC) Instruction List (0x0033)”. Once message sequencing is underway, the “Bus Controller (BC) Instruction List
Pointer (0x0034)” is updated by the BC control logic.
The BC Instruction List in RAM comprises a series of 2-word entries, an instruction op code followed by a parameter
word. While processing messages, the BC control logic fetches and executes the instruction op code referenced by the
“Bus Controller (BC) Instruction List Pointer (0x0034)” from the BC Instruction List. The pointer parameter, referencing
the first word in the Message Control/Status Block, must have the form 0xHHH8 or 0xHHH0, where each H represents
a hex character, 0-9 or A-F. If the individual message is RT-to-RT, the address must have the form 0xHHH0.
Each op code word in the BC Instruction List has the format:
Odd
Parity
X X X X X X 0 1 0 1 0 X X X X X
P Op Code Field Validation Field Condition Code
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Bus Controller execution stops immediately if the BC logic fetches an op code word having one or more of these error
conditions:
• Bit 15 contains even parity
• Bits 14-10 contain an undefined op code
• Validation field bits 9-5 do not equal 01010
If enabled in the “Bus Controller (BC) Interrupt Enable Register (0x0010)”, a BCTRAP interrupt occurs when execution
stops because of an illegal op code.

54
HI-6138
GPQ Word 63 6 Unused Addresses
GPQ Words 1 - 62 2nd RT Status Word RT-RT Message Only

BC General Purpose
Queue Pointer GPQ Word 63 Tx Command Word
reg 0x0038
RT Status Word Time Tag Bits 31-16
if BC Uses 32-Bit
BC GP Queue Loopback Word Time Base
in RAM
Block Status Word
Time Tag Word Data Word N
Increasing Time to Next Msg Data Word(s)

Memory
Address Parameter Data Block Pointer Data Word 1
Op Code Command Word *
Parameter (pointer) BC Control Word Message Data

BC Instruction
Op Code Block in RAM
List Pointer
reg 0x0034
Parameter Message
BC Instruction Control / Status
List Start Address Op Code Block in RAM * Rx Command Word
reg 0x0033 if RT-RT Message
Register Bus Controller

Space Instruction List
in RAM
Figure 4. Bus Controller Message Sequence Structures
10.1. Bus Controller Condition Codes

For most op codes, execution is conditional, depending on evaluation of the Condition Code field. Condition Code bits
3-0 define the specific condition. Condition Code bit 4 identifies the required outcome for op code execution, true or
false, following evaluation of Condition Code bits 3-0. The host has read-only access to the BC condition codes by
reading the “Bus Controller (BC) Condition Code Register (Read 0x0037)”.
Eight of the condition codes (1000 through 1111) are set or cleared based on the outcome of the most recent message.
The remaining eight codes are General Purpose Condition Codes, GP0 through GP7. Three processes affect values
of the General Purpose Condition Code bits: (a) they may be toggled, set or cleared when the BC logic executes a FLG
(GP Flags Bits) op code. (b) they may be toggled, set or cleared when the host writes the “Bus Controller (BC) General
Purpose Flag Register (Write 0x0037)”. (c) only GP0 and GP1 may be set or cleared when the BC logic executes a
CMT (Compare Message Timer) op code, or a CFT (Compare Frame Timer) op code. The sixteen BC Condition Codes
are summarized in Table 5.

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Table 5. Bus Controller Condition Code Table
Code Condition Code Inverse

Function
Bit 3-0 Bit 4 = 0 Bit 4 = 1
Less Than or GP0 Flag.

This flag may be toggled, set or cleared when the BC logic
executes a FLG (General Purpose Flags Bits) op code, or
when the host writes the “Bus Controller (BC) General Purpose
LT / GP0 GT-EQ / GP0
Flag Register (Write 0x0037)”.
This flag is also set or cleared based on the evaluation of a
CMT (Compare Message Timer) or CFT (Compare Frame
Timer) instruction op code:
If CMT parameter < BC Time to Next Message Reg

0x0 LT / GP0 = 1 GT-EQ / GP0 = 0
If CFT parameter < BC Frame Time Remaining Reg
If CMT parameter = BC Time to Next Message Reg

LT / GP0 = 0 GT-EQ / GP0 = 1
If CFT parameter = BC Frame Time Remaining Reg
If CMT parameter > BC Time to Next Message Reg

LT / GP0 = 0 GT-EQ / GP0 = 1
If CFT parameter > BC Frame Time Remaining Reg
LT / GP0 = 1 GT-EQ / GP0 = If CMT parameter ≠ BC Time to Next Message Reg

or 0 based on 0 or 1 based on
compared values compared values If CFT parameter ≠ BC Frame Time Remaining Reg
Equal To or GP1 Flag.

This flag may be toggled, set or cleared when the BC logic
when the host writes the “Bus Controller (BC) General Purpose
EQ / GP1 NE / GP1
Flag Register (Write 0x0037)”.
This flag is also set or cleared based on the evaluation of a
CMT (Compare Message Timer) or CFT (Compare Frame
Timer) instruction op code:
If CMT parameter < BC Time to Next Message Reg

0x1 EQ / GP1 = 0 NE / GP1 = 1
If CFT parameter < BC Frame Time Remaining Reg
If CMT parameter = BC Time to Next Message Reg

EQ / GP1 = 1 NE / GP1 = 0
If CFT parameter = BC Frame Time Remaining Reg
If CMT parameter > BC Time to Next Message Reg

EQ / GP1 = 0 NE / GP1 = 1
If CFT parameter > BC Frame Time Remaining Reg
If CMT parameter ≠ BC Time to Next Message Reg

EQ / GP1 = 0 NE / GP1 = 1
If CFT parameter ≠ BC Frame Time Remaining Reg

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Function
Bit 3-0 Bit 4 = 0 Bit 4 = 1
0x2 GP2 GP2
0x3 GP3 GP3 General Purpose Flag Bits 2-7.

0x4 GP4 GP4 These flags may be toggled, set or cleared when the BC logic
0x5 GP5 GP5 when the host writes the “Bus Controller (BC) General Purpose
0x6 GP6 GP6 Flag Register (Write 0x0037)”.
0x7 GP7 GP7
No Response Flag.
This flag is set when an RT failed to respond to a command,
0x8 NORESP RESP or responded later than the BC No Response Timeout
programmed using bits 15-14 in the “BC (Bus Controller)
Configuration Register (0x0032)”.
Format Error Flag.

This flag is set when the received response to the last
message had one or more violations to MIL-STD-1553B
validation criteria, including problems with sync, encoding, bit
0x9 FMTERR FMTERR
count, parity, or word count.
This flag is also set when the received RT Status Word
response from the last message contained an incorrect RT
address field.
Good Data Block Transfer.

Reflecting status for the last 1553 message, this flag is set
after completion of error-free RT-to-BC transfers, RT-to-RT
transfers, or transmit mode code commands with data. This
0xA GOODBLOCK GOODBLOCK flag is reset after invalid messages, or after completion of BC-
to-RT transfers, receive mode code commands with data, or
mode code commands without data. This flag may be used to
determine when the transmit aspect of an RT-to-RT transfer is
error-free.
Masked Status Set.

Reflecting status for the last 1553 message, this flag is set
when one or both of the following conditions occurred:
• In the message BC Control Word, at least one of the
Status Mask bits 14-9 are logic 0, but the corresponding bit
or bits are set in the received RT Status Word. When the
Reserved Bits Mask (message BC Control Word bit 9) is
0xB MSKSTATSET MSKSTATSET logic 0, this flag is set when any or all of the three reserved
bits are set in the received RT Status Word.
• In the “BC (Bus Controller) Configuration Register
(0x0032)”, the BCR (broadcast command received)
Mask Enable bit 0 is logic 1. The Mask Broadcast bit 5
in the message BC Control Word is logic 0, and the BCR
(Broadcast Command Received) bit 4 is logic 1 in the
received RT Status Word.

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Function
Bit 3-0 Bit 4 = 0 Bit 4 = 1
Bad Message.
Reflecting status for the last 1553 message, the Bad Message
flag is set for Format Error, No Response error, or Loopback
0xC BADMSG GOODMSG
error.
A Status Set condition has no effect on the Bad Message
condition code.
1 Retry.
If Condition Code bits 3:0 = 0xD and bit 4 = 0, one or two
0xD 1RETRY 1RETRY message retries is indicated.
If Condition Code bits 3:0 = 0xD and bit 4 = 1, zero message
retries is indicated.
2 Retries.
If Condition Code bits 3:0 = 0xE and bit 4 = 0, two message
0xE 2RETRY Undefined
retries is indicated.
Condition Code bits 3:0 = 0xE and bit 4 = 1 is undefined.
Always.
The ALWAYS bit is set (Condition Code bit 4 = 0) to designate
0xF ALWAYS NEVER an instruction op code as unconditional.
The NEVER bit is set (Condition Code bit 4 = 1) to designate
an instruction op code as NOP (no operation).
10.2. Bus Controller Instruction Op Codes

In the BC Instruction List, each op code word contains a 5-bit instruction field that spans bits 14-10. The instruction op
codes are described in Table 6. Four instructions execute unconditionally, without evaluating the condition code test.
For these instructions, the Condition Code field is “don’t care”.
The four unconditional instruction op codes are:

1. CMT (Compare Message Timer)
2. CFT (Compare Frame Timer)
3. FLG (General Purpose Flag Bits)
4. XQF (Execute and Flip)
All other instruction op codes execute conditionally. They execute only if evaluation of the Condition Code tests true,
logic 1. If the Condition Code field tests false, the BC Instruction List Pointer skips to the next instruction op code in
the BC Instruction List.
Many instruction op codes utilize the following parameter word in the BC Instruction List. Depending on the op code,
the parameter may be a RAM address, a time value, an interrupt bit pattern, an argument that sets or clears General
Purpose Flag bits, or an immediate value. For some op codes, the parameter word is not used and is therefore “don’t
care.” For an XEQ (execute message) instruction, the parameter is a RAM address pointer referencing the start of
the message Control/Status Block.

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These instructions control program execution: Halt, Jump, Subroutine Call and Subroutine Return. Subroutine calls
can be nested 8 levels deep. If BC Call Stack overflow or underflow occurs, device logic generates a CSTKERR (Call
Stack Pointer Error) interrupt, if enabled. Other host interrupts are generated under program control using the Interrupt
Request instruction. In this case, a 4-bit user-defined interrupt code is written to the BC Interrupt Request Bits 3-0 in
the “Bus Controller (BC) Pending Interrupt Register (0x0007)”.
Other instructions perform various duties: set, reset or toggle General Purpose Flag bits; load the Time Tag counter;
load the Frame Time counter; begin a new BC frame; wait for external trigger, then start a new BC frame; evaluate
remaining Frame Time; or evaluate time to next message.
Table 6. Bus Controller Instruction Op Codes
Op
Name Instruction Parameter Function
Code
If the Condition Code evaluates True, execute the message

at the parameter-specified Message Control Status Block
address. Otherwise (Condition Code Evaluates False),
continue execution at the next op code in the BC Instruction
List.
At the start of XEQ message execution, if the fourth word in
the Message Control/Status Block is nonzero, it is copied to
the BC Time to Next Message Register, and message timer
begins decrementing. The BC message sequencer does not
fetch the next instruction op code until the message timer
reaches zero.
Execute
RAM Address for Regarding Condition Codes used with XEQ:
Message
XEQ 0x01 Message Control/
Status Block • If using LT, GT-EQ, EQ and NE (which are only
Conditional modified by the device upon completion of CMT or CFT
op codes) the host must not change the value of the
shared function GP0 or GP1 flag bit during execution of
the contingent message.
• If using GP Flag Bit status (GP0 through GP7) to enable
a message, host must not alter the tested GP Flag bit
during execution of a contingent message.
• The ALWAYS and NEVER Condition Codes may be
used with XEQ. The following Condition Codes must
not be used with XEQ: BADMSG, RETRY1 or RETRY2,
NORESP, MSKSTATSET, FMTERR or GOODBLOCK.

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Op
Code
If the Condition Code evaluates True, execute the message

at the parameter-specified Message Control Status Block
address. Otherwise (Condition Code Evaluates False),
continue execution at the next op code in the BC Instruction
List.
Regarding Condition Codes used with XQG:
• If using LT, GT-EQ, EQ and NE (which are only
modified by the device upon completion of CMT or CFT
op codes) the host must not change the value of the
shared function GP0 or GP1 flag bit during execution of
the contingent message.
• If using GP Flag Bit status (GP0 through GP7) to enable
a message, host must not alter the tested GP Flag bit
during execution of a contingent message.
Execute • The ALWAYS and NEVER Condition Codes may be
Message and RAM Address for used with XQG. The following Condition Codes must
XQG Go 0x16 Message Control/ not be used with XQG: BADMSG, RETRY1 or RETRY2,
Status Block NORESP, MSKSTATSET, FMTERR or GOODBLOCK.
Conditional At the start of XQG message execution, if the fourth (Time
to Next Message) word in the Message Control/Status Block
is nonzero, it is copied to the “Bus Controller (BC) Time To
Next Message Register (0x0036)”, and this message timer
begins countdown. Completion of an XQG message may
occur while message timer countdown continues.
Unlike XEQ, the XQG op code does not wait for the
decrementing message timer to hit 0 before fetching the
next instruction op code. As long as op codes following
XQG do not execute a 1553 message, each op code
is performed after fetch. Upon reaching a following
XEQ, XQG, XQF or XFG execute-message instruction,
transaction of its 1553 message does not begin until Time
to Next Message count reaches 0. Thus, programmed 1553
message timing is maintained, while allowing execution of
non-message instruction op codes.
If the Condition Code evaluates True, jump to the
Jump RAM Address parameter-specified instruction op code in the BC
JMP 0x02 within the BC Instruction List. Otherwise (Condition Code Evaluates
Conditional Instruction List False), continue execution at the next op code in the BC
Instruction List.
If the Condition Code evaluates True, push address of the

Call next instruction op code onto the 8-level BC Call Stack, then
RAM Address
Subroutine jump to the parameter-specified instruction op code in the
CAL 0x03 within the BC
BC Instruction List. Otherwise (Condition Code Evaluates
Instruction List
Conditional False), continue execution at the next op code in the BC
Instruction List.

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Op
Code
If the Condition Code evaluates True, pop the top address

Return from
Not Used from the BC Call Stack, then jump to the popped instruction
Subroutine
RTN 0x04 op code address in the BC Instruction List. Otherwise
(Don’t Care) (Condition Code Evaluates False), continue execution at the
Conditional
next op code in the BC Instruction List.
If the Condition Code evaluates True, generate a host

Interrupt interrupt by writing the parameter-specified 4-bit value N
Request 4-Bit Interrupt to bits 8-5 in the “Bus Controller (BC) Pending Interrupt
IRQ 0x06 Register (0x0007)”. Otherwise, continue execution at the
Pattern, 0x000N
Conditional next op code in the BC Instruction List.
Note: no interrupt is generated if N = 0
If the Condition Code evaluates True, stop execution of the

Halt Not Used BC Instruction List until a new BC Start is issued by the
HLT 0x07
(Don’t Care) host. Otherwise (Condition Code Evaluates False), continue
Conditional
execution at the next op code in the BC Instruction List.
If the Condition Code evaluates True, initiate a delay equal
to the parameter-specified value. Otherwise (Condition
Delay Delay Time Value Code Evaluates False), continue execution at the next op
DLY 0x08 (1 μs per LSB code in the BC Instruction List.
Conditional resolution) If the Time-to-Next Message counter is in use, the DLY
parameter has higher priority than the count for an
unfinished Message Timer delay.
Wait until
If the Condition Code evaluates True, stop BC Instruction
Frame Timer Not Used List execution until the BC Frame Time Counter decrements
WFT Equals 0 0x09
(Don’t Care) to 0. Otherwise (Condition Code Evaluates False), continue
Conditional
Compare to Time Value Compare the parameter-specified Time Value to the “Bus
Frame Timer Controller (BC) Frame Time Remaining Register (0x0035)”.
CFT 0x0A (100 µs / LSB Set and clear LT and EQ bits 1 and 0 in the “Bus Controller
Unconditional resolution) (BC) General Purpose Flag Register (Write 0x0037)”.

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Op
Code
Compare the parameter-specified Time Value to the “Bus

Controller (BC) Time To Next Message Register (0x0036)”.
Set and clear LT and EQ bits 1 and 0 in the “Bus Controller
(BC) General Purpose Flag Register (Write 0x0037)”.
When CMT is preceded by an XEQ or XQF instruction,
Compare the “Bus Controller (BC) Time To Next Message Register
to Message Time Value (0x0036)” value used for comparison is always 0x0000
CMT Timer 0x0B because the message timer (initiated by XEQ or XQF)
(1 µs per LSB
decrements to zero before fetching the CMP instruction. In
resolution)
Unconditional this case, a CMT with non-zero parameter word always sets
GT-EQ and NE and always resets LT and EQ flags. When
CMT is preceded by an XEQ or XQF instruction, a CMT with
parameter word 0x0000 always sets GT-EQ and EQ and
always resets LT and NE flags. Further, the CMT op code
will never set LT and NE, while clearing GT-EQ and EQ
flags.
Time Value
If the Condition Code evaluates True, load the “Bus
(Resolution is
Controller (BC) Time Tag Counter (0x0043)” with the
Load Time programmed
parameter-specified Time Value. This represents bits 15-0
Tag Counter by bits 2-0
LTT 0x0D when the BC operates with 32-bit time tag. Otherwise
in the “Time
(Condition Code Evaluates False), continue execution at the
Conditional Tag Counter
Configuration
Register Read LTH regarding LTT-LTH sequences.
(0x0039)”)

Controller (BC) Time Tag Counter High (0x0044)” with the
parameter-specified Time Value. This represents bits 31-16
when BC operates with 32-bit time tag.
Load Time Otherwise (Condition Code Evaluates False), continue
Tag Counter Time Value
High (Resolution is
If LTH immediately follows an LTT instruction, all 32 counter
programmed
Conditional bits are loaded simultaneously. If LTH is not preceded by an
by bits 2-0
LTH 0x18 LTT instruction, time count bits 15-0 in “Bus Controller (BC)
in the “Time
LTH only Time Tag Counter (0x0043)” will be cleared to 0x0000 when
Tag Counter
applies bits 31-16 are written to register “Bus Controller (BC) Time
Configuration
when 32-bit Tag Counter High (0x0044)”.
Register
time base is (0x0039)”) This instruction is only allowed when BCTT32 bit 3 is logic 1
enabled in the “Time Tag Counter Configuration Register (0x0039)”,
selecting 32-bit time base operation for the BC and RT.
If BCTT32 is logic 0, this instruction stops instruction list
execution, and generates an illegal instruction BCTRAP
interrupt, if enabled.

Load Frame Time Value Controller (BC) Frame Time Remaining Register (0x0035)”
Timer
LFT 0x0E (100 µs / LSB with the parameter-specified Time Value. Otherwise
resolution) (Condition Code Evaluates False), continue execution at the
Conditional

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Op
Code
If the Condition Code evaluates True, start decrementing

Start Frame
Not Used the “Bus Controller (BC) Frame Time Remaining Register
Timer
SFT 0x0F (0x0035)”. Otherwise (Condition Code Evaluates False),
(Don’t Care) continue execution at the next op code in the BC Instruction
Conditional
List.
If the Condition Code evaluates True, push the value in

Push Time
Not Used the “Bus Controller (BC) Time Tag Counter (0x0043)” onto
Tag Count
PTT 0x10 the “Bus Controller General Purpose Queue”. Otherwise
Conditional
Push Time the “Bus Controller (BC) Time Tag Counter High (0x0044)”
Tag Count onto the “Bus Controller General Purpose Queue”. This
High represents bits 31-16 when BC operates with 32-bit time
tag. Otherwise (Condition Code Evaluates False), continue
Conditional Not Used execution at the next op code in the BC Instruction List.
PTH 0x19
PTH only (Don’t Care) This instruction is only allowed when BCTT32 bit 3 is logic 1
applies in the “Time Tag Counter Configuration Register (0x0039)”,
when 32-bit selecting 32-bit time base operation for the BC and RT.
time base is If BCTT32 is logic 0, this instruction stops instruction list
enabled execution, and generates an illegal instruction BCTRAP

the “Bus Controller (BC) Time Tag Counter High (0x0044)”
Push Time and then push the value in the “Bus Controller (BC) Time
Tag Count Tag Counter (0x0043)” onto the “Bus Controller General
Both Purpose Queue”. (Both words are fetched simultaneously
but pushed serially.) Otherwise (Condition Code Evaluates
Conditional Not Used False), continue execution at the next op code in the BC
PTB 0x1A Instruction List.
PTB only (Don’t Care)
applies This instruction is only allowed when BCTT32 bit 3 is logic 1
when 32-bit in the “Time Tag Counter Configuration Register (0x0039)”,
time base is selecting 32-bit time base operation for the BC and RT.
enabled If BCTT32 is logic 0, this instruction stops instruction list
execution, and generates an illegal instruction BCTRAP
If the Condition Code evaluates True, push the value of

Push Block
Not Used the Block Status Word from the most recent message onto
Status Word
PBS 0x11 the “Bus Controller General Purpose Queue”. Otherwise
Conditional
Push If the Condition Code evaluates True, push the parameter-

Immediate specified immediate value onto the “Bus Controller General
PSI Value 0x12 Immediate Value Purpose Queue”. Otherwise (Condition Code Evaluates
False), continue execution at the next op code in the BC
Conditional Instruction List.

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Op
Code
If the Condition Code evaluates True, push the value stored

Push Indirect at the parameter-specified address onto the “Bus Controller
PSM 0x13 Memory Address General Purpose Queue”. Otherwise (Condition Code
Conditional Evaluates False), continue execution at the next op code in
the BC Instruction List.
Wait for If the Condition Code evaluates True, wait for a rising edge
External Not Used (logic 0 to 1 transition) on the BCTRIG pin before continuing
WTG Trigger 0x14 execution at the next op code in the BC Instruction List
(Don’t Care) Otherwise (Condition Code Evaluates False), continue
Conditional execution at the next op code in the BC Instruction List.
Unconditionally execute the message at the parameter-
specified Message Control/Status Block Address. At
message completion, if the Condition Code evaluates
True, then toggle bit 4 of the Message Control/Status Block
Address, and store the new Message Control/Status Block
Address as the updated value of the parameter following
the XQF instruction op code. As a result, the next time
this address in the BC Instruction List is executed, the
Execute and processed Message Control/ Status Block resides at the
RAM Address for
Flip updated address (old address XOR 0x0010) instead of the
XQF 0x15 Message Control/
Status Block old address. Otherwise (Condition Code Evaluates False)
Unconditional the value of the Message Control/Status Block Address
parameter is not changed.
At the start of XQF message execution, if the fourth word in
the Message Control/Status Block is nonzero, it is copied
to the “Bus Controller (BC) Time To Next Message Register
(0x0036)”, and message timer begins decrementing. The
BC message sequencer does not fetch the next instruction
op code until this message timer reaches zero.

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Op
Code
Unconditionally execute the message at the parameter-

specified Message Control/Status Block Address. At
message completion, if the Condition Code evaluates
True, then toggle bit 4 of the Message Control/Status Block
Address, and store the new Message Control/Status Block
Address as the updated value of the parameter following
the XFG instruction op code. As a result, the next time
this address in the BC Instruction List is executed, the
processed Message Control/ Status Block resides at the
updated address (old address XOR 0x0010) instead of the
old address. Otherwise (Condition Code Evaluates False)
the value of the Message Control/Status Block Address
parameter is not changed.
Execute, Flip
RAM Address for At the start of XQG message execution, if the fourth (Time
and Go
XFG 0x17 Message Control/ to Next Message) word in the Message Control/Status Block
Status Block is nonzero, it is copied to the “Bus Controller (BC) Time To
Unconditional
Next Message Register (0x0036)”, and this message timer
begins countdown. Completion of an XQG message may
occur while message timer countdown continues.
Unlike XQF, the XFG op code does not wait for the
decrementing message timer to hit 0 before fetching the
next instruction op code. As long as op codes following XFG
do not execute a 1553 message, each op code is performed
after fetch. Upon reaching a following XEQ, XQG, XQF
or XFG execute-message instruction, transaction of its
1553 message does not begin until Time to Next Message
count reaches 0. Thus, programmed 1553 message timing
is maintained, while allowing execution of non-message
instruction op codes.
If the Condition Code evaluates True, write the parameter-

Write specified immediate value to the dedicated WMI memory
Immediate pointer (a register not accessible by the host). Otherwise
Value to WMI (Condition Code Evaluates False), continue execution at the
WMP Memory 0x1B Immediate Value next op code in the BC Instruction List.
Pointer
Immediate value must exceed 0x4F or WMP instruction has
Conditional no effect. After reset, the default WMI memory pointer value
is 0x0050.
Write
If the Condition Code evaluates True, write the parameter-
Immediate
specified immediate value to 0x0050 or the memory
Value to
WMI 0x1C Immediate Value address specified by the last WMP instruction performed.
Memory
Otherwise (Condition Code Evaluates False), continue
Conditional

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Op
Code
Decrement If the Condition Code evaluates True, the memory address

RAM specified by the parameter word is decremented. If the new
Specified value is non-zero, the next instruction is executed. If the
by Memory decremented value is zero, the next instruction is skipped.
Address, Otherwise (Condition Code Evaluates False), continue
DSZ 0x1D Memory Address
Skip the Next execution at the next op code in the BC Instruction List.
Instruction if
Zero The primary purpose of DSZ is N-iteration repeating
execution loops. N is initialized with a WMI op code, and the
Conditional instruction following DSZ is a JMP to top-of-loop.
General The parameter word value is used to set, clear, or toggle the
Word value sets,
Purpose Flag lower byte in the “Bus Controller (BC) General Purpose Flag
clears or toggles
FLG Bits 0x0C Register (Write 0x0037)”. The upper and lower bytes in the
General Purpose
parameter word provide 2-bit arguments that modify each of
Flag Bits
Unconditional the eight GP flag bits, as illustrated below.
GP7 GP0
H7 H6 H5 H4 H3 H2 H1 H0 Hx = 0 0 1 1
Parameter High Byte: Clear GP Bits 7-0 No Set Clear Toggle

Word Bit 15 14 13 12 11 10 9 8 Change GPx GPx GPx
L7 L6 L5 L4 L3 L2 L1 L0 Lx = 0 1 0 1
Low Byte: Set GP Bits 7-0 H-L Bit Combinations Modify GP Flag Bits
Parameter
Word Bit 7 6 5 4 3 2 1 0
Figure 5. Bus Controller Flag Operation

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10.3. Bus Controller General Purpose Queue

The BC architecture includes a General Purpose Queue, a 64-word circular buffer which the BC can use to convey
information to the external BC host. Various BC instruction op codes push data values onto the queue, such as the
Block Status Word for the last message, Time Tag Counter values, immediate data values, or values stored in specific
RAM addresses.
The “Bus Controller (BC) General Purpose Queue Pointer Register (0x0038)” is initialized with the default starting
address 0x00C0 after reset. The queue is relocatable, so the host may overwrite the default base address. Updated
by the BC logic each time a data word is pushed onto the queue, the pointer in register 0x0038 always points to the
next storage address in the queue to be written. The address pointer rolls over every 64th word written. If the BCGPQ
bit 13 is logic 1 In the “Bus Controller (BC) Interrupt Enable Register (0x0010)”, a BC interrupt is generated when the
General Purpose Queue Pointer rolls over from its ending address to its base address.
10.4. Bus Controller Message Control / Status Blocks

In the BC Instruction List, each occurrence of the “execute message” instructions, XEQ, XQG, XQF and XFG, refer-
ences a MIL-STD-1553B message. The op code word is followed by the parameter word, a memory pointer indicating
the RAM start address for a corresponding Message Control/Status Block. The pointer address indicates the first word
in the Message Control/Status Block, the BC Control Word. Figure 6 illustrates this relationship.
The HI-6138 is fully compatible with all MIL-STD-1553B message formats. For most MIL-STD-1553 messages, the
corresponding Message Control/Status Block contains 8 words:
• BC Control Word. This word contains flags that select message format, choose the active bus, enable message
retry and end-of-message interrupt, indicate expected RT status word flags, etc.
• MIL-STD-1553 Command Word. When message is RT-to-RT, this is the Receive Command Word.
• Data Block Pointer. For subaddress commands and mode code commands with data, this word identifies the
start address of the Message Data Block in RAM. For mode commands without data, this word is not used.
• Time-to-Next Message. The time count loaded here begins decrementing at start of message. When value ex-
ceeds message execution time, it paces delivery of the next message.
• Time Tag Word. The current value of the internal time tag count is written to the Time Tag Word at Start-of-Mes-
sage and again at the End-of-Message. When the BC uses a 16-bit time base, this location contains the complete
time count. When the BC uses 32-bit time base, this word contains time bits 15-0 and block word 7 contains time
bits 31-16 (instead of Loopback Word).
• Block Status Word. This word contains various message result flags.
• Loopback Word, containing the last word transmitted by the BC (16-bit time base only) or
Time Tag Bits 31-16 (32-bit time base only)
• RT Status Word received.
This is the Transmit RT Status Word when message is RT-to-RT.
When the message is RT-to-RT, the Message Control/Status Block contains 8 additional words:
• Transmit Command Word.
• Receive RT Status Word.
• Six unused word locations, to maintain 8 or 16 words per Message Control/Status Block.
Figure 6 shows the range of Message Control/Status Block variations. Selected words in the Message Control/Status
Block are described next.

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HI-6138
6 Unused Addresses 6 Unused Addresses
Rx RT Status Word Increasing Rx RT Status Word

Memory
Tx Command Word Address Tx Command Word
RT Status Word Tx RT Status Word RT Status Word Tx RT Status Word
Loopback Word Loopback Word High Time Tag Word High Time Tag Word
Block Status Word Block Status Word Block Status Word Block Status Word
Time Tag Word Time Tag Word Low Time Tag Word Time Tag Word
Time to Next Msg Time to Next Msg Time to Next Msg Time to Next Msg
Data Block Pointer Data Block Pointer Data Block Pointer Data Block Pointer
Command Word Rx Command Word Command Word Rx Command Word
BC Control Word BC Control Word BC Control Word BC Control Word
Message Message Message Message

Control / Status Block Control / Status Block Control / Status Block Control / Status Block
for all messages for RT-to-RT for all messages for RT-to-RT
except RT-to-RT messages only except RT-to-RT messages only
Bus Controller Configured for 16-Bit Time Base Bus Controller Configured for 32-Bit Time Base
Figure 6. Structure of Bus Controller Message Control / Status Blocks in RAM
10.4.1. BC Control Word

R AS K
SR AS 7
R TFM T
YM SK
M CR
K
A
Y SK
M AS
T
LF SA
TF T
EM C1
S M
AS T
Q K
O d
TR S
SE N
M
SV K
es T
M TS
M rve
BS MA
BC DF
R MA
SS A
TF SM
EO KB
U YE
SE BU
M TM
R IN
e
TR
T
C
TX
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The BC Control Word is the first word in each Message Control / Status Block. The BC Control Word is not transmitted
on the MIL-STD-1553 bus. This word is initialized and maintained by the host to specify message attributes: message
format, which bus to use, bit masks for the received RT Status Word, enabling interrupt at end-of-message, and
enabling self test:

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HI-6138
Transmit Time Tag for Synchronize Mode Code Command MC17.

This option bit only applies when “BC (Bus Controller) Configuration
Register (0x0032)” TTSYNEN bit 3 is logic 1. This bit affects only the
“synchronize with data” mode code command, (mode code 0x11 or decimal
17).
• If this Control Word bit is logic 0 (or if “BC (Bus Controller) Configuration
Register (0x0032)” TTSYNEN bit 3 is logic 0) the BC transmits the
value contained in the Message Data Block as the data word for a
“synchronize” mode code command MC17. The transmitted word is
fetched from the RAM address referenced by the Data Block Pointer.
15 TXTTMC17 R/W 0 • If this Control Word bit and “BC (Bus Controller) Configuration Register
(0x0032)” TTSYNEN bit 3 are both logic 1, the “synchronize” mode data
word value originates from the 16-bit BC time base counter (low order
16 bits when using the 32-bit BC time base option).
• If “BC (Bus Controller) Configuration Register (0x0032)” ETTSYN
bit 2 is also logic 1, the transmitted time tag data word is always an
even value; the least significant bit is always 0.
• When ETTSYN bit 2 is logic 0, the data word least significant bit
may be 0 or 1.
The transmitted data value is saved in the message data block, at the
address indicated by the Data Block Pointer word.
Message Error Bit Mask.

If this BC Control Word bit is logic 0 and the Message Error bit 10 is logic 1
in the received RT Status Word, a “Status Set” condition will result.
If this BC Control Word bit is logic 1, the Message Error bit 10 in the
received RT Status Word has no effect on the outcome for a “Status Set”
condition.
Note: A “Status Set” condition results if one or more of these events occurs:
• one or more of the mask bits 14-9 in the BC Control Word is logic 0 and
the corresponding bit is logic 1 in the received RT Status Word,
14 MEMASK R/W 0
• the BCRME bit 0 is logic 1 in the “BC (Bus Controller) Configuration
Register (0x0032)” and the MASKBCR bit in the BC Control Word is
logic 0 and the Broadcast Command Received bit 4 is logic 1 in the RT
Status Word
• the BCRME bit 0 is logic 0 in the “BC (Bus Controller) Configuration
Register (0x0032)” and the MASKBCR bit in the BC Control Word
differs from the Broadcast Command Received bit 4 in the RT Status
Word
• The received RT Status Word contains an RT Address field different
from the RT Address field in the transmitted Command Word

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HI-6138
Service Request Bit Mask.

If this BC Control Word bit is logic 0 and the Service Request bit 8 is logic 1
13 SRQMASK R/W 0 If this BC Control Word bit is logic 1, the Service Request bit 8 in the
condition.
See “Note” at end of MEMASK bit description above.
Busy Bit Mask.

If this BC Control Word bit is logic 0 and the Busy bit 3 is logic 1 in the
received RT Status Word, a “Status Set” condition will result.
12 BSYMASK R/W 0
If this BC Control Word bit is logic 1, the Busy bit 3 in the received RT
Status Word has no effect on the outcome for a “Status Set” condition.
Subsystem Flag Bit Mask.
If this BC Control Word bit is logic 0 and the Subsystem Flag bit 2 is logic 1
11 SSYSMASK R/W 0 If this BC Control Word bit is logic 1, the Subsystem Flag bit 2 in the
condition.
Terminal Flag Bit Mask.

If this BC Control Word bit is logic 0 and the Terminal Flag bit 0 is logic 1 in
the received RT Status Word, a “Status Set” condition will result.
10 TFMASK R/W 0
If this BC Control Word bit is logic 1, the Terminal Flag bit 0 in the received
RT Status Word has no effect on the outcome for a “Status Set” condition.
Reserved Bits Mask.

If this BC Control Word bit is logic 0 and one or more of the three Reserved
bits 7-5 is logic 1 in the received RT Status Word, a “Status Set” condition
will result.
9 RSVMASK R/W 0
If this BC Control Word bit is logic 1, the three Reserved bits 7-5 in the
received RT Status Word have no effect on the outcome for a “Status Set”
condition.

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HI-6138
Retry Enabled.
If this Control Word bit is logic 1 and BCRE (BC Retry Enable) bit 12 is
logic 1 in the “BC (Bus Controller) Configuration Register (0x0032)”, the BC
will retry a message if RT response timeout or Format Error occurs.
8 RTRYENA R/W 0 If this Control Word bit is logic 1 and BCRE (BC Retry Enable) bit 12 is
logic 1 and BCRSB (BC Retry If Status Word Bits Set) bit 8 is also logic 1
in the “BC (Bus Controller) Configuration Register (0x0032)”, the BC will
retry a message when a “Status Set” condition occurs. See “Note” at end of
MEMASK bit 14 description above.
Use Bus A / Use Bus B.

7 USEBUSA R/W 0 If this Control Word bit is logic 1, the BC transmits the command on Bus A.
If this Control Word bit is logic 0, the BC transmits the command on Bus B.
Self-Test Message Off-Line.

If this Control Word bit is logic 1, transmission of this message onto the
1553 bus is inhibited. Instead the digitally-encoded Command Word is
looped back into the receive decoder for the selected bus. This tests both
the encoding and decoding signal paths. Upon message completion, Loop
6 SELFTST R/W 0 Test Fail bit 8 in the Block Status Word indicates the self-test result.
If BC is configured for 16-bit time base, the received Loopback Word is
stored in the Message Control/Status Block. If the BC is configured for 32-
bit time base, time tag bits 31-16 are stored in the Loopback Word location.
See Section “21.2.7. Programmed BC-Mode Digital Loopback Testing (Off-
Line)” on page 211.

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HI-6138
Mask Broadcast Command Received Bit.

If the BCRME bit 0 is logic 1 in the “BC (Bus Controller) Configuration
Register (0x0032)”, then this Control Word bit is a “mask bit” like bits 14-9,
acting upon the BCR Broadcast Command Received bit 4 in the received
RT Status Word:
• If this MASKBCR Control Word bit is logic 0 and the Broadcast
Command Received bit 4 is logic 1 in the received RT Status Word, a
“Status Set” condition will result.
• If this MASKBCR Control Word bit is logic 1, the Broadcast Command
Received bit 4 in the received RT Status Word has no effect on the
outcome for a “Status Set” condition.
5 MASKBCR R/W 0
If the BCRME bit 0 is logic 0 in the “BC (Bus Controller) Configuration
Register (0x0032)”, then this MASKBCR Control Word bit reflects the
expected state of the Broadcast Command Received bit 4 in the received
RT Status Word:
• If this MASKBCR Control Word bit does not match the logic state
of the Broadcast Command Received bit 4 in the received RT Status
Word, a “Status Set” condition will result.
• If this MASKBCR Control Word bit matches the logic state of the
Broadcast Command Received bit 4 in the received RT Status Word,
then the Broadcast Command Received bit 4 in the received RT Status
Word has no effect on the outcome for a “Status Set” condition.
See Table 7.
BC Selected Message Interrupt.

If this Control Word bit is logic 1 and the SELMSG bit 14 is logic 1 in the
4 SELMSGINT R/W 0 “Bus Controller (BC) Interrupt Enable Register (0x0010)”, a SELMSG
interrupt will occur upon message completion (i.e. SELMSG bit 14 will be
set in the BC Pending Interrupt Register (0x0007)).
3 Reserved R/W 0 This bit is not used.

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2 MCODFMT Mode Code Message Format.

1 BCSTFMT Broadcast Message Format.
0 RTRTFMT RT to RT Message Format.
The combination of these three Message Format bits selects the MIL-STD-
1553B message type:
Mode Broadcast RT-RT

Message Type
Code Bit 2 Bit 1 Bit 0
0 0 0 BC-to-RT if the T/R bit * equals logic 0

RT-to-BC if the T/R bit * equals logic 1
R/W 0 0 0 1 RT-to-RT
0 1 0 Broadcast BC-to-RT
0 1 1 Broadcast RT-to-RT
1 0 0 Mode Code Command
1 0 1 Do Not Use
1 1 0 Broadcast Mode Code Command
1 1 1 Do Not Use
* Transmit / Receive bit in Command Word

Note: Bit 0 must be logic 1 for RT-RT messages. This is the single control
point enabling the 16-word Control Block that configures RT-RT messages.
10.4.2. Time to Next Message Word

The Bus Controller provides a programmable delay for Time to Next Message. This word in the Message Control /
Status Block specifies the delay from the start of this message, to the start of the next message. The delay is program-
mable with 1 µs per LSB resolution, and has a maximum value of 65.535 milliseconds.
When the specified Time to Next Message value is less than the actual time required to transact the current message,
the next message starts immediately upon completion current message, after the minimum inter-message gap time of
4µs. This gap corresponds to a bus “dead time” of 2µs.
10.4.3. Data Block Pointer

The Data Block Pointer in the Message Control / Status Block provides the starting address in RAM for storage of
message data words or mode code data. For BC-to-RT (receive) commands, this pointer contains the RAM location
for the first data word transmitted by the BC.
For RT-to-BC (transmit) commands or RT-to-RT commands, this pointer contains the RAM location for storing the first
data word transmitted by the RT (and received by the BC).

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HI-6138
10.4.4. BC Block Status Word
RT Y1 T
R SE
T
F E T SE
RT AT
G Y0
ST E
AG
M
M
BC
B
ST
R
A
E
D
D
SO
EO
TM
SE
LB
LE
IW
BI
W
M
M
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The Block Status Word in the Message Control / Status Block provides information regarding message status (in-
process or completed), the bus it was transmitted on, whether errors occurred during the message, and the type of
occurring errors. This word is written into RAM by the device after message completion. Because it resides in RAM,
the host has read-write access, although this word is usually treated as read-only by the host.
End of Message.
This bit is set upon completion of a BC message, whether or not errors
15 EOM R/W 0 occurred. When EOM is set, the current value of the Time Tag Word(s) is
(are) written to the corresponding Time Tag Word(s) in the BC Message
Control/Status Block.
Start of Message.
This bit is set at the start of a BC message and cleared at the end of the
14 SOM R/W 0 message. When SOM is set (and reset), the current value of the Time Tag
Word(s) is (are) written to the corresponding Time Tag Word(s) in the BC
Message Control/Status Block.
Bus ID (Bus B / Bus A).

13 BID R/W 0 This bit is logic 1 if the BC message was transacted on Bus B.
This bIt is logic 0 if the BC message was transacted on Bus A.
Message Block Coding Error.

This bit is a programming test aid. Each message BC Control Word has
flags that indicate format: mode code command (bit 2), RT-RT message
(bit 1) and broadcast message (bit 0). When CHKFMT is 1, these flags
are compared to the message Command Word(s) that follow the Control
Word in the Message Block. When message format mismatch occurs (a
12 MBCE R/W 0 BC programming error), this MBCE bit is set in the message Block Status
Word. See CHKFMT description in “BC (Bus Controller) Configuration
Register (0x0032)” on page 78.
NOTE: MBCE will also be asserted when CHKFMT is logic “0” under other
conditions; for broadcast transmit data or mode code with data, broadcast
MC0 (dynamic bus control) or MC2 (transmit status), RTRT with first word
as transmit or second as receive, RTRT word count differences.

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HI-6138
Status Set.
This bit is not affected by the values of mask bits 14-9 in the “BC Control
Word” for the message.
This bit is logic 1 when the received RT Status Word contains an
unexpected bit value in the bit 10-0 range. The expected value is usually
logic 0 for bits 10-0 in the received RT Status Word.
The BCR Mask Enable (BCRME) bit 0 is logic 0 in the “BC (Bus
11 STATSET R/W 0 Controller) Configuration Register (0x0032)”. If opposite logic states
occur for the MASKBCR bit in the message “BC Control Word” and the
Broadcast Command Received (BCR) bit in the received RT Status Word,
then the STATSET bit is set.
The BCR Mask Enable (BCRME) bit 0 is logic 1 in the “BC (Bus
Controller) Configuration Register (0x0032)”. If the Broadcast Command
Received Bit is set in the RT Status Word and the MASKBCR bit 5 in the
“BC Control Word” is logic 0 then the STATSET bit is set.
Format Error.
This bit is logic 1 when a received RT response violates MIL-STD-1553
10 FE R/W 0 message validation criteria. This includes sync, word count, encoding, bit
count or parity errors. Word bits 2-0 provide additional information. This
flag is also set when the received RT Status Word response from the last
message contained an incorrect RT address field.
No Response Timeout Error.
9 TM R/W 0 This bit is logic 1 when an RT fails to respond, or responds later than the
BC No Response Timeout interval specified by bits 15-14 in the “BC (Bus
Controller) Configuration Register (0x0032)”.
Loopback Error.
The BC evaluates its own 1553 message transmissions. The received
version of each word transmitted by the BC is checked for 1553 validity
(sync, encoding, bit count and/or parity error). In addition, for each
message transacted, the received image for the last word transmitted by
8 LBE R/W 0
the BC is evaluated for data match.
This bit is logic 1 when the received version for one or more words
transmitted by the BC fails 1553 “word validity” criteria, and/or the
received version for the last word transmitted by the BC does not match
the Manchester II word transmitted by the BC.
Masked Status Set.

This bit is logic 1 when any of the following conditions occurs:
• One or more of the mask bits 14-9 in the BC Control Word is logic 0
and the corresponding bit is logic 1 in the received RT Status Word.
7 MSTATSET R/W 0 • Or the BCRME bit 0 is logic 1 in the “BC (Bus Controller) Configuration
Register (0x0032)” and the MASKBCR bit in the BC Control Word is
logic 0 and the Broadcast Command Received bit 4 is logic 1 in the
RT Status Word.
• DBCA bit 1 is set in the RT Status Word and DBCMSTAT bit 1 is set
in “Master Configuration Register 2 (0x004E)”.

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HI-6138
Retry Count 1 and Retry Count 0

If BCRE (BC Retry Enable) bit 12 is logic 1 in the “BC (Bus Controller)
Configuration Register (0x0032)” and RTRYENA bit 8 is logic 1 in the
“BC Control Word” for this message, the BC will retry the message if RT
response timeout or Format Error occurs.
Also, if BCRE (BC Retry Enable) bit 12 is logic 1 and BCRSB (BC
Retry if Status Word Bits Set) bit 8 is logic 1 in the “BC (Bus Controller)
Configuration Register (0x0032)” and RTRYENA bit 8 is logic 1 in the “BC
6 RTRY1 Control Word” for this message, the BC will retry the message when a
R/W 0 “Status Set” condition occurs. See “MSTATSET” bit 7 description above.
5 RTRY0
The combination of these two bits indicates the number of times this
message was retried:
RTRY1 Bit 6 RTRY0 Bit 5 Number of Retries

0 0 0
0 1 1
1 0 2
1 1 Not Used
Good Transmit Data Block Transfer.

This bit is set to logic 1 upon successful completion of an error-free RT-to-
BC message, RT-to-RT message, or transmit mode code message with
data. This bit always resets to logic 0 for any BC-to-RT message, mode
code message without data, or any incomplete or invalid message.
4 GDB R/W 0
This bit may be used for determining when the transmit portion of an
RT-to-RT message is error-free. If this bit and Error Flag bit 12 are both
set to logic 1 in the Block Status Word for an RT-to-RT message, the
transmitting RT responded correctly but error occurred in the receiving RT
portion of the message.
Wrong RT Address and/or No Gap.

This bit is logic 1 when one or both of the following conditions occur
• the RT address field within a received RT Status Word does not match
3 WAG R/W 0 the RT address field in the Command Word transmitted by the BC
• the BCGCE BC Gap Check Enable bit 1 in the “BC (Bus Controller)
Configuration Register (0x0032)” and the RT responds with response
time less than 4 µs per MIL-STD-1553B, mid-parity bit to mid-sync, (2
µs bus “dead time”).
Word Count (Length) Error.
This bit is logic 1 when an RT-to-BC message, RT-to-RT message, or
transmit mode code message with data is transacted with the wrong
2 LE R/W 0
number of data words.
This bit always resets to logic 0 for BC-to-RT messages, receive mode
code messages, or transmit mode code messages without data.
Sync Error.
1 SE R/W 0 This bit is logic 1 when an RT responds with Data Sync in its Status Word,
or with Command/Status Sync in a Data Word.

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HI-6138
Invalid Word Error.
0 IWE R/W 0 This bit is logic 1 when an RT response in one or more words having
at least one of the following errors: sync encoding error, Manchester II
encoding error, bit count error, parity error.

77
HI-6138
11. BUS CONTROLLER REGISTER DESCRIPTION

In addition to the registers described here, the Bus Controller also utilizes one or more Memory Address Pointer
registers (described in Section 9.12) for managing SPI read/write operations.
11.1. BC (Bus Controller) Configuration Register (0x0032)
T EN
S E
R T
G V
BC SYN
TT DT
BS DV
E
BC CE
BC FM
M SB
BC ND
BC TE
BC O1
C 0
BC RE
BC 1A
BC 2A
ET YN
M
TO
BC E
W
EN
G
R
K
R
R
T
Y
2
H
BC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
BC Time Out Select.

This 2-bit field selects the BC “no response” time-out delay from four
available selections. Excluding RT-RT commands, response delay is
measured from command word mid-parity bit to status word mid-sync:
Bit 15:14 Bus Dead Time Time Out (excludes RT-RT)
00 16μs 18μs
01 21μs 23μs
10 80μs 82μs
11 138μs 140μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
15 − 14 BCTO1:0 R/W 0
receive command to mid-sync of the first received data word. This
adds 42µs for the embedded parity half-bit, transmit command word,
transmit-RT status word and data half-sync within this interval:
TxRT Bus Dead

Bit 15:14 RT-RT Time Out*
Time
00 19μs 61μs
01 24μs 66μs
10 80μs 122μs
11 138μs 180μs
*Note: per RT Validation Test Plan, Fig. 8.

All time out select values have –100ns / +500ns tolerance.

78
HI-6138
Check Message Format.

When this bit equals logic 1, “BC Control Word” message format
bits 2-0 (mode command, RT-RT message and broadcast flags) are
compared to values for the message Command Word(s) that follow the
Control Word in the Message Block. This is provided as a BC program
development aid.
When the CHKFMT bit is logic 1 and message format mismatch
occurs, the MBCE Message Block Coding Error bit 12 is set in the
message BC Block Status Word (see Section “10.4.4. BC Block Status
Word” on page 74). If enabled, BC Trap interrupt is generated (see
Section “11.16.3. Bus Controller (BC) Interrupt Output Enable Register
(0x0014)” on page 95).
13 CHKFMT R/W 0
Note: When the CHKFMT bit is logic 0, the MBCE bit 12 in the
message BC Block Status Word will also be set if any of the following
conditions occur; for broadcast transmit data or mode code with data,
broadcast MC0 (dynamic bus control) or MC2 (transmit status), RTRT
with first word as transmit or second as receive, RTRT word count
differences.
When the CHKFMT bit is logic 0, no format checking occurs between
“BC Control Word” bits 2-0 and the MIL-STD-1553 message Command
Word(s). Even with message format checking disabled, “BC Control
Word” bit 0 must be logic 1 for RT-RT messages. This is the single
control point enabling the 16-word BC Control Block that configures an
RT-to-RT message.
BC Retry Enable.
12 BCRE R/W 0 If bit 12 equals logic 0, command retries are disabled for all messages.
If bit 12 equals logic 1, command retries can be enabled on an
individual message basis by setting bit 8 in the “BC Control Word”.
BC Second Retry Enable.
11 BC2RE R/W 0 If retries are enabled (register bit 12 equals 1) this bit selects the
number of retries performed, If bit 11 equals logic 0, a single retry is
performed. If bit 11 equals logic 1, up to two retries are performed.
BC First Retry Use Alternate Bus.

If retries are enabled (register bit 12 equals 1) this bit selects the bus
10 BCR1A R/W 0 used for the first retry. If bit 10 equals 0, the first retry is performed on
the same bus from which the message was originally transmitted. If bit
10 equals 1, first retry is performed on the alternate bus from which the
message was originally transmitted.
BC Second Retry Use Alternate Bus.

If first and second retries are enabled (register bits 12:11 equal 1-1)
9 BCR2A R/W 0 this bit selects the bus used for the second retry. If bit 9 equals 0, the
second retry is performed on the same bus where the message was
originally transmitted. If bit 9 equals 1, second retry is performed on the
alternate bus from where the message was originally transmitted.

79
HI-6138
BC Retry If Unmasked Status Word Bit Set.

This bit affects operation of BC retries. If bit 8 equals logic 0, the BC
will not retry messages because of status bit(s) set in the RT Status
Word, or Status Word with non-matching RT address field.
If retries are enabled and bit 8 equals logic 1, the BC will retry
messages for these RT status word results:
1. One or more “BC Control Word” mask bits 14-9 is logic 0 (bits are
8 BCRSB R/W 0 not masked) and the corresponding bit is logic 1 in the received RT
Status Word.
2. The BCR Mask Enable bit 0 equals 0 in the “BC (Bus Controller)
Configuration Register (0x0032)”. The Broadcast Command
Received (BCR) bit in the received RT Status Word differs from the
Mask BCR bit (bit 5) in the BC Control Word.
3. Received Status Word RT address does not match Command Word
RT address.
Message Error Status, No Data is Valid
Bit 7 affects BC validation of RT responses to transmit commands
when the Message Error (ME) bit is asserted in the received RT Status
Word.
When the MENDV bit equals logic 0:
• When an RT responds Message Error status to a transmit
command, the response is valid only if the Status Word is followed
by the commanded number of data words. Message result:
7 MENDV R/W 0 Condition Block Status Word Condition Code Register
Commanded
Good Data Block Good Data Block Transfer
number of data
(GDB) bit = 1 (GDBT) bit = 1
words
Masked Status Set Masked Status Set

If MEMASK = (MSTATSET) bit = 0. (MSTATSET) bit = 0.
1 in BC Control
Word Status Set
----------
(STATSET) bit = 1.

80
HI-6138
• If the RT responds Message Error status to a transmit command

with the wrong number of data words or no data words, here is the
message result:
Condition Block Status Word Condition Code Register
Wrong number of (or Format Error (FE) Format Error (FMTERR)

no) data words bit = 1 bit = 1

(MSTATSET) bit = 0. (MSTATSET) bit = 0.
If MEMASK = 1 in Word Count Error Bad Message (BADMSG)

BC Control Word (LE) bit = 1. bit = 1
Status Set
----------
(STATSET) bit = 1.
MENDV
7 R/W 0
(continued) When the MENDV bit equals logic 1:
• When an RT responds Message Error status to a transmit
command, the response is valid with the commanded number of
data words, or ME status with no data words. Here is the message
result:
Commanded # of
data words only, Good Data Block Good Data Block Transfer
“Good Data” is not (GDB) bit = 1 (GDBT) bit = 1
shown if no data

If MEMASK = 0 in (MSTATSET) bit = 1. (MSTATSET) bit = 1.
BC Control Word Status Set
----------
(STATSET) bit = 1.

81
HI-6138
• If the RT responds Message Error status to a transmit command

with the wrong number of data words (not 0), here is the message
result:
Wrong number of Format Error (FE) Format Error (FMTERR)

data words bit = 1 bit = 1
If MEMASK = 0 in Word Count Error Bad Message (BADMSG)

BC Control Word (LE) bit = 1. bit = 1
Status Set
----------
(STATSET) bit = 1.
The only 3 cases when an RT transmits Message Error status onto the
bus:
1. An RT using “illegal command detection” receives an illegal command
that otherwise meets all other validation requirements. The RT
MENDV responds with Status Word only, with Message Error bit set. No data
7 R/W 0
(continued) words are sent.
2. An RT receives a “transmit status” mode command (MC2). The
previous valid command for the RT had Message Error status. The
RT responds with Status Word only, with Message Error bit set. No
data words are sent.
3. An RT receives a “transmit last command” mode command (MC18
decimal). The previous valid command for the RT set Message Error
status. The RT responds with Status Word (with Message Error bit
set) and one data word, the previous Command Word.
In summary, Message Error status never occurs with more
than one data word, and only occurs with one data word for the
“transmit last command” mode code.
Besides illegal command detection, there is just one situation where
Message Error status occurs, but Status transmission is suppressed:
The RT detects a valid receive command having correct RT address,
but an invalid word is detected in the accompanying data words, or a
gap occurs between words. In this situation, Message Error status
is set but the RT suppresses its Status Word transmission. This
suppressed ME status is only seen by the BC if retrieved by a following
“transmit status’’ or “transmit last command” mode command.

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Busy Status, No Data, is Valid

Bit 6 affects BC validation of RT responses to transmit commands when
the Busy bit is asserted in the received RT Status Word.
When the BSYNDV bit equals logic 0:
When an RT responds Busy status to a transmit command, the
response is valid only if the Status Word is followed by the commanded
number of data words. Here is the message result:
Commanded number Good Data Block Good Data Block Transfer

of data words (GDB) bit = 1 (GDBT) bit = 1

If BSYMASK = 1 in
BC Control Word
Status Set
BCMRE = 1 ----------
(STATSET) bit = 1.
• If the RT responds Busy status to a transmit command with

the wrong number of data words or no data words, here is the
message result:
Good Data Block Good Data Block Transfer

(GDB) bit = 0 (GDBT) bit = 0
Incorrect
6 BSYNDV R/W 0
commanded number FE bit = 1 FMTERR bit = 1
of data words
Word Count Error
(LE) bit = 1.
If BSYMASK = 1 in Masked Status Set Masked Status Set

BC Control Word (MSTATSET) bit = 0. (MSTATSET) bit = 0.
Status Set Bad Message (BADMSG)

BCMRE = 1
(STATSET) bit = 1. bit = 1
When the BSYNDV bit equals logic 1:

• When an RT responds to a transmit command with Busy status,
the response is valid when accompanied by the commanded
number of data words, or accompanied by no data words. Here is
the message result:
Commanded # of
data words only, Good Data Block Good Data Block Transfer
“Good Data” is not (GDB) bit = 1 (GDBT) bit = 1
shown if no data
If BSYMASK = 1 in Masked Status Set Masked Status Set

BC Control Word
Status Set
BCMRE = 1 ----------
(STATSET) bit = 1.

83
HI-6138
• If the RT responds to a transmit command with Busy status and

the wrong number of data words (but not 0), here is the message
result:
Format Error (FE) Format Error (FMTERR)

Wrong number of bit = 1 bit = 1
data words Word Count Error
(LE) bit = 1.
If BSYMASK = 1 in
BC Control Word Word Count Error Bad Message (BADMSG)
(LE) bit = 1. bit = 1
BSYNDV BCMRE = 1
6 R/W 0 Status Set
(continued) ----------
(STATSET) bit = 1.
A busy RT is one that is functional, but cannot send or receive data

when commanded by the Bus Controller. An RT that is busy sets
the Busy bit in its Status Word responses. In response to transmit
commands, the busy terminal has no words to transmit, so only the
Status Word is transmitted. In the case of the “transmit vector word” and
transmit BIT word” mode code commands, even if the data is available
to the terminal, it is prohibited to send the data word if the Busy bit is set
in the Status Word.
There is just one defined situation in which an RT transmits Busy
status with one (and only one) data word: An RT receives a “transmit
last command” mode command (MC18 decimal). When the previous
valid command for the RT had Busy status, the RT responds with last
message status condition (with Busy bit set) and one data word, the
previous Command Word.
BC Message Gap Timer Enable.

If bit 5 is logic 0, the BC does not add delay between 1553 messages.
Message timing is paced by the time required for the BC to complete
message post processing. In this case, the minimum inter-message gap
will be used, with a bus “dead time” of approximately 6 to 9µs.
If bit 5 is logic 1, the BC Message Timer is enabled. The “Time to Next
5 BCGTE R/W 0 Message” value from the Message Control Block is decremented at
1µs rate. When the count decrements from 1 to 0, the next message
starts. If the specified message gap time is less than the time needed
for the current message, the next message will start immediately after
completion of the current message. In this case, the minimum inter-
message gap will be used, with a bus “dead time” of approximately 6 to
9µs. This allows the BC to implement minor frame cycle times without
host processor intervention.

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BC Watchdog Timer (WDT) Enabled.

When this bit is logic 1, if the BC Watchdog Timer interrupt bit is set
in the “Bus Controller (BC) Interrupt Enable Register (0x0010)”, the
BC sets the BCWDT bit in the “Bus Controller (BC) Pending Interrupt
Register (0x0007)” when the BC Frame Timer decrements from 1 to 0.
4 BCWDTE R/W 0 When using this feature, it is necessary to periodically reload the Frame
Time register by means of the LFT Load Frame Time op code in the BC
message sequence control block. The loaded value must allow for the
worst-case frame time (including message retries). The WDT provides
a failsafe recovery from faults such as message sequence stuck in
repetitive loop without LFT reload, or execution jumping to the wrong
sequence.
BC Time Tag Synchronization Enable

This option bit only affects the “synchronize with data” mode code
command, MC17. When this bit is logic 1, the source of the mode
data issued with the “synchronize” mode command is determined by
message “BC Control Word” TXTTMC17 bit 15 (see Section 10.4.1)
• If “BC Control Word” TXTTMC17 bit 15 = logic 0, the “synchronize”
mode data word originates from the message data block, at the
RAM address indicated by the Data Address Pointer word.
• If “BC Control Word” TXTTMC17 bit 15 = logic 1, the “synchronize”
3 TTSYNEN R/W 0 mode data word value originates from the 16-bit BC time base
counter (or the low order 16 bits, when using the 32-bit BC time
base option). The transmitted data value is saved in the message
data block, at the address indicated by the Data Address Pointer
word.
If the TTSYNEN bit is logic 0, regardless of the state of message
Control Word bit 15, the “synchronize with data” mode command
(MC17) is always issued with mode data originating from the message
data block, at the RAM address indicated by the Data Address Pointer
word.
Even Time Tag Sync.
This bit only applies when TTSYNEN bit 3 is logic 1 and “BC Control
Word” TXTTMC17 bit 15 is also logic 1, selecting “synchronize” mode
2 ETTSYN R/W 0 data origin as time base counter. In this case, if ETTSYN is logic 1,
the transmitted time tag data word is always even; the low order bit is
always 0. When the ETTSYN bit is logic 0, the data word may be even
or odd; the LSB may be 0 or 1.

85
HI-6138
BC Gap Check Enable.

When this bit is logic 1, the BC verifies that any transmission by a
Remote Terminal on the bus is preceded by an inter-word gap of at
least 4µs. When this minimum gap time is violated, the BC declares
the RT Status Word invalid, and the No Gap error bit is set in the Block
Status Word. Gap detection measures the time span from mid-parity of
1 BCGCE R/W 0 last received word, to mid-sync of the following word (defined here as
detection of a properly encoded sync plus two bits). Measured gap time
is adjusted to evaluate just the interval of interest, corresponding to a
bus “dead time” (end-of-parity to start-of-sync) of 2µs minimum.
When this bit is logic 0 (strongly recommended) the BC does not
check for minimum bus “dead time” prior to start of transmission by a
device on the MIL-STD-1553 bus.
BCR Mask Enable.

This bit selects the function of “BC Control Word”, Mask Broadcast,
when evaluating the BCR (Broadcast Command Received) bit in RT
status words.
If BCR Mask Enable bit 0 is logic 1, then RT status word BCR bit
masking is enabled. The state of the Mask BCR bit in each “BC Control
Word” selectively allows or disallows BCR status testing by the BC:
• When “Mask BCR” is logic 1 in a message’s “BC Control Word”
(disabling BCR status bit test), the value of the RT status word BCR
bit is “don’t care” in terms of affecting the occurrence of a “Status
Set” condition.
• When “Mask BCR” is logic 0 in the message’s “BC Control Word”,
“Status Set” occurs when the BCR bit in the received RT Status
0 BCRME R/W 0 Word is logic 1.
• While broadcast commands never result in transmitted RT status,
the “Mask BCR” bit should be set in BC Control Words for “transmit
status” or “transmit last command” mode commands immediately
following broadcast messages. Setting the “Mask BCR” bit of the
message’s “BC Control Word” to logic 1 indicates the expected
value of the BCR bit in the received RT Status Word.
If BCR Mask Enable bit 0 is logic 0, the “Mask BCR” bit in a
message’s “BC Control Word” indicates the expected state of the BCR
bit in the received RT status word. In this situation, whenever the BCR
bit in the received RT status word differs from the state of the “Mask
BCR” bit in the “BC Control Word”, a “Status Set” condition occurs and
the BC generates a Status Set interrupt, if enabled.
Table 7 summarizes the effects of BC configuration, message Control
Word and RT Status Word on “Status Set” bit in the Block Status Word.

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Table 7. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition
BC Configuration Received BCR bit

Message Control Resultant Block
Register 0x0032 4 in the Remote
Word “Mask BCR” Status Word “Status
“BCR Mask Enable” Terminal Status
bit 5 Set” bit 11
bit 0 Word
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 X 0
11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
This register is initialized with the base address of the re-locatable BC Instruction List in device RAM.
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Only and is fully maintained by the device. When the BC is running, the user programming
changes this pointer value indirectly, by executing a JMP op code. When the bus controller is enabled, setting BCSTRT
bit 13 in the “Master Configuration Register 1 (0x0000)” begins bus controller operation. The device copies the
Instruction List base address from register 0x0033 into this register. This pointer references pairs of words in the BC
instruction list. Each word pair is comprised of an op code word followed by a parameter word. Pointer update occurs
just before execution of the next BC instruction list op code, after execution of the prior op code, and evaluation of its
result-dependent outcome.
11.4. Bus Controller (BC) Last Message Block Address (0x004F)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The IP Core Bus Controller Logic will copy the address of the Message Block of the last executed message to
this register upon completion. Each completed BC Message command (XEQ, XQG, XQF, and XFG) will update this

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register with the Message Block location, for last received data or for last transmitted data.
11.5. Bus Controller (BC) Frame Time Remaining Register (0x0035)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write. A value is written to this register upon execution of the BC instruction list op code,
“Load Frame Timer” (LFT). Time remaining value begins decrementing upon execution of the Start Frame Timer (SFT)
instruction op code. The parameter word accompanying the op code word is the desired time value, expressed with a
resolution of 100 µs per LSB, with a maximum value of 6.5535 sec.
11.6. Bus Controller (BC) Time To Next Message Register (0x0036)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Only. This programmable time-to-next message timer is loaded on a message-by-mes-
sage basis, with values from word 4 in each Message Control / Status Block. The BC time-to-next message is defined
as the time from the start of the current message to the start of the next message, i.e., mid-sync zero crossing to the
next mid-sync zero crossing. This timer provides a 1 µs per LSB resolution, with a maximum value of 65.535 ms.
11.7. Bus Controller (BC) Condition Code Register (Read 0x0037)

FM T T
B E
ST G
PF P
O R
D S
P0
/G 1
ET 1
D 0
M MS
R UN
G ES
LT GP
N R
R RY
BA RY
G AT
TE
G 6
G 5
G 4
EQ 2
G 7
G 3
R
R
PF
PF
PF
PF
PF
ET
/
BC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Sharing the same register address as the Write-Only “Bus Controller (BC) General Purpose Flag Register (Write
0x0037)”, this 16-bit register is Read-Only. Bit 15 indicates BC run/stop status. With this exception, the upper 8 bits
indicate results from the last message processed by the Bus Controller. The lower 8 bits of this register are general
purpose flag bits, which may be set, cleared, or toggled by the host using the “Bus Controller (BC) General Purpose
Flag Register (Write 0x0037)”, or by the device by means of the General Purpose Flag Bits (FLG) instruction op code.
Further, bits 1-0 can be set or cleared by the device BC logic by execution of two BC instruction op codes: Compare
to Frame Timer (CFT) and Compare to Message Timer (CMT).

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BC Run / Stop
This is a status bit, not a condition code. This bit indicates whether the
BC is running or stopped. The bit is set to logic 1 when the BCSTRT bit
13 in the “Master Configuration Register 1 (0x0000)” is asserted and the
BCENA bit 12 in the “Master Configuration Register 1 (0x0000)” is logic
15 BC RUN R 0 1.
Once set, this bit resets to logic 0 if the BCENA register bit is reset to
logic 0 by the host, or if the BC executes the HLT instruction, or if the
BC executes an illegal op code. The “illegal op code” case will generate
a BCTRAP interrupt, if enabled (see Section “11.16.3. Bus Controller
(BC) Interrupt Output Enable Register (0x0014)” on page 95).
Message Retry Status Bits.

Bits 14-13 indicate the retry status of the most recent message the
number of times message was retried:
14 RETRY 1 Bit 14:13 Number of Message Re-tries
R 0
13 RETRY 0
0-0 0
0-1 1
1-0 2
1-1 not used
Bad Message.
12 BADMSG R 0 This bit is logic 1 to indicate message format error, loopback test failure,
or no response error for the last message.
Masked Status Set.

This bit is set if one or more of the following conditions occurred during
the last message:
• One or more of the Status Mask bits 14-9 are logic 0 in the “BC
Control Word”, and the corresponding bits are logic 1 in the received
RT Status Word. When BC Control Word “Reserved Bits Mask” bit
9 is logic 0, this Masked Status Set bit is set if any of the three
11 MSTATSET R 0
Reserved bits are set in the received RT Status Word.
• If the BCR Mask Enable bit 0 is logic 1 in the “BC (Bus Controller)
Configuration Register (0x0032)”, and the Broadcast Command
Received Bit is set in the RT Status Word and the MASKBCR bit
5 in the “BC Control Word” is logic 0 then the MSTATSET bit is set.
Table 7 on page 87 shows how the Broadcast Command Received
(BCR) bit in the received RT Status Word affects Masked Status Set.

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Good Data Block Transfer.

Indicating status for the last transmit-data message, this bit is set to
logic 1 after completion of an error-free RT-to-BC transfer, RT-to-RT
transfer, or transmit mode command with data. This bit is reset to logic
0 following any message in which error occurs. This bit is always logic
0 after completion of a BC-to-RT transfer, a receive mode command
10 GDBT R 0 with data, or any mode command without data. This bit can be used
to determine when the transmit portion of an RT-to-RT message was
error-free: A Block Status Word for an RT-to-RT message having both
the Error Flag and Good Data Block Transfer bits set indicates that
the transmitting RT responded correctly, but an error was detected in
the receiving RT portion of the message. This bit is not affected by the
device loop back function.
Format Error.
This bit is logic 1 when the received data from the most recent message
contains one or more violations of the MIL-STD-1553 message
9 FMTERR R 0 validation criteria, including sync, encoding, parity, bit count or word
count errors.
This bit is also set if the received Status Word from the responding RT
contains incorrect RT address bits 15:10.
No Response Error.
This bit is set to logic 1 when an RT fails to respond to a command,
8 NORESP R 0 or responds later than the BC No Response Timeout time. The No
Response Timeout delay is programmed using BC Timeout Select bits
15-14 in the “BC (Bus Controller) Configuration Register (0x0032)”.
General Purpose Flags 7-2.

Interpretation of these flag bits is user defined. These bits are set
7−2 GP7 − GP2 R 0 cleared or toggled by the host, through use of the “Bus Controller (BC)
General Purpose Flag Register (Write 0x0037)”, or by the BC, through
use of the FLG instruction op code.
Equal / General Purpose Flag 1.

This flag bit is manipulated using the same methods as General
1 EQ / GP1 R 0 Purpose Flags 7-2, or may be set or cleared by two BC instruction op
codes, Compare to Frame Time Counter (CFT) or Compare to Message
Time Counter (CMT).
Less Than / General Purpose Flag 0

This flag bit is manipulated using the same methods as General
0 LT / GP0 R 0 Purpose Flags 7-2, or may be set or cleared by two BC instruction
op codes, Compare to Frame Time Counter (CFT) or Compared to
Message Time Counter (CMT).

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11.8. Bus Controller (BC) General Purpose Flag Register (Write 0x0037)
6
5
1
7
3
2
4
T F0
T F6
T F5
T F1
T F7
T F4
T F3
T F2
0
LR F
LR F
LR F
LR F
LR F
LR F
LR F
PF
C GP
C GP
C GP
C GP
C GP
C GP
C GP
SE G P
SE G P
SE G P
SE G P
SE G P
SE G P
SE G P
SE G P
G
LR
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
W Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Sharing the same register address as the Read-Only “Bus Controller (BC) Condition Code Register (Read 0x0037)”,
this 16-bit register is Write-Only. This register is written by the host to set, clear or toggle any combination of the 8
general-purpose flags 7-0 in the “Bus Controller (BC) Condition Code Register (Read 0x0037)”. When this register is
written, general-purpose flags are modified. Reading register address 0x0037 returns the value in the BC Condition
Code Register, containing the modified GP flag bits.
Each general-purpose flag in the BC Condition Code Register is mirrored twice in the General Purpose Flag Register,
once in the upper byte and once in the lower byte. Bits asserted in the lower byte set the corresponding GP flag bits
in the BC Condition Code Register to 1. Bits asserted in the upper byte clear the corresponding GP flag bits in the BC
Condition Code Register to 0. Bits asserted in both the lower and upper bytes for a specific GP flag toggles (inverts)
the corresponding GP flag bit in the BC Condition Code Register. When both bits are written to logic 0 state for a spe-
cific GP flag bit, no change occurs for that GP flag bit. The FLG instruction op code operates similarly, as shown in the
diagram in Figure 5. Writes to this register have no effect unless the BC is already running. The BCENA bit 12 in
“Master Configuration Register 1 (0x0000)” must have previously been written high.
Clear General Purpose Flag 7-0.

CLEAR
15 − 8 W 0 Bits asserted in the upper byte clear the corresponding GP flag bits in
GP7 − GP0
the BC Condition Code Register to 0.
Set General Purpose Flag 7-0.
SET Bits asserted in the lower byte set the corresponding GP flag bits in the
7−0 W 0 BC Condition Code Register to 1. Bits asserted in both the lower and
GP7 − GP0
upper bytes for GPx toggles that GP flag bit in the BC Condition Code
Register.
11.9. Bus Controller (BC) General Purpose Queue Pointer Register (0x0038)
MSB General Purpose Queue RAM Address LSB
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 MR Reset
R RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is a combination of Read-Only and Read-Write bits. This register contains 0x00C0 after MR pin
master reset. The initialized value represents the base address for the 64-word BC General Purpose Queue. The host
can overwrite the default 0x00C0 value, but low order bits 5-0 and bit 15 must equal logic 0 for the initialized value.
The general purpose queue provides a way for the Bus Controller message sequencer to convey various information
to the external host. The BC instruction set includes op codes that push data values onto this queue, including immedi-
ate data values, the Block Status Word from the most recent message, the Time Tag Register count, or the contents
of a specified memory address.

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The General Purpose Queue is implemented as a 64-word circular buffer. This register always points to the next
queue address to be written, the address following the last queue location written by the Bus Controller. This queue
pointer rolls over from bits 5:0 = 11111 to 00000, every 64th word written. (Bits 15:6 are static.) If enabled in the “Bus
Controller (BC) Interrupt Enable Register (0x0010)”, the BCGPQ interrupt will be generated each time queue pointer
rollover occurs.
11.10. Bus Controller (BC) Time Tag Counter (0x0043)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
11.11. Bus Controller (BC) Time Tag Counter High (0x0044)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These registers are read-only and are cleared after MR pin Master Reset. The Bus Controller can be configured for
either 16- or 32-bit time base counting in the “Time Tag Counter Configuration Register (0x0039)”. When configured
for 16-bit time base operation, register 0x0043 contains the entire 16-bit count. When configured for 32-bit time base
operation, count bits 31-16 reside in register 0x0044 while register 0x0043 contains bits 15-0.
For programmed bus controller action, instruction op codes are provided for loading a time tag count value, or pushing
the current time tag count onto the BC General Purpose Queue. If configured for 32-bit time base operation, separate
op codes are provided for loading the upper or lower words individually, or pushing the individual words or simultane-
ously pushing both words onto the BC General Purpose Queue:
Configuration Op Code Description
LTT Load Time Tag Count (parameter) into register 0x0043.

LTH Not used for 16-bit time base.
16-Bit Time
PTT Push Time Tag Count from register 0x0043 onto BC GP Queue.
Base
PTH Not used for 16-bit time base.
PTB Not used for 16-bit time base.
LTT Load Low Time Tag Count (parameter) into register 0x0043.
LTH Load High Time Tag Count (parameter) into register 0x0044.
32-Bit Time PTT Push Low Time Tag Count from register 0x0043 onto BC GP Queue.
Base PTH Push High Time Tag Count from register 0x0044 onto BC GP Queue.
PTB Push Low and High Time Tag Counts from register 0x0043 and 0x0044 onto BC GP
Queue (simultaneous 32-bit count capture)
The host can bypass BC Instruction List execution to exercise direct control over the BC Time Tag counter. By writing
bits 13-12 in the “Time Tag Counter Configuration Register (0x0039)”, the host can clear time tag count to zero, or
load the current value contained in the BC Time Tag Utility Register(s) into the BC Time Tag counter(s). Finally, the BC
Time Tag Match Register(s) provide capability for host interrupts when the time tag count reaches any predetermined
16- or 32-bit value.

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11.12. Bus Controller (BC) Time Tag Utility Register (0x0045)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
11.13. Bus Controller (BC) Time Tag Utility High Register (0x0046)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These registers are read-write and are cleared after MR pin Master Reset. This utility register pair is used for simul-
taneously loading a 16- or 32-bit value into the BC Time Tag Counter. When loading, the value contained in utility
register 0x0045 is copied into “Bus Controller (BC) Time Tag Counter (0x0043)”. If the BC is configured for 16-bit time
base, register 0x0043 contains the entire 16-bit count. If configured for 32-bit time base operation, count bits 31-16 are
simultaneously copied from utility register 0x0046 into “Bus Controller (BC) Time Tag Counter High (0x0044)”. Please
refer to the description for bits 13-12 in the “Time Tag Counter Configuration Register (0x0039)” on page 48.
11.14. Bus Controller (BC) Time Tag Match Register (0x0047)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
11.15. Bus Controller (BC) Time Tag Match High Register (0x0048)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These registers are read-write and are cleared after MR pin Master Reset. When the BCTTM bit 5 is logic 1 in the
“Hardware Interrupt Enable Register (0x000F)”, an interrupt occurs when the BC time tag count matches the value
stored in this register pair. If the BC is configured for 16-bit time base, match register 0x0047 is compared to time base
count register 0x0043 for match determination. If configured for 32-bit time base operation, count bits 31-16 in match
register 0x0048 is also compared to “Bus Controller (BC) Time Tag Counter High (0x0044)” for match determination.
Please refer to the description for BCTTM bit 5 in the Hardware Interrupt Registers in Section 9.8.

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11.16. Bus Controller Interrupt Registers and Their Use

Section 9.5 on page 36 through Section 9.7 describe how the host uses three Hardware Interrupt registers, the
Interrupt Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When the Bus Controller is
enabled, three additional registers are dedicated to Bus Controller interrupts. Comparable to the Hardware Interrupt
register triplet, the Bus Controller has
• A “Bus Controller (BC) Interrupt Enable Register (0x0010)” to enable and disable interrupts
• A “Bus Controller (BC) Pending Interrupt Register (0x0007)” to capture the occurrence of enabled interrupts
• A “Bus Controller (BC) Interrupt Output Enable Register (0x0014)” to enable IRQ output to host, for pending
enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding
interrupt condition is enabled. Numerous interrupt options are available for the BC. At initialization, bits are set in the
“Bus Controller (BC) Interrupt Enable Register (0x0010)” to identify the interrupt-causing events for the BC which are
heeded by the device. Most Bus Controller applications only use a subset of available BC interrupt options. Interrupt-
causing events are ignored when their corresponding bits are reset in the “Bus Controller (BC) Interrupt Enable
Register (0x0010)”. Setting an Interrupt Enable Register bit from 0 to 1 does not trigger interrupt recognition for events
that occurred while the bit was zero.
Whenever a Bus Controller interrupt event occurs (and the corresponding bit is already set in the “Bus Controller (BC)
Interrupt Enable Register (0x0010)”), these actions occur:
• The Interrupt Log Buffer is updated.
• A bit corresponding to the interrupt type is set in the “Bus Controller (BC) Pending Interrupt Register (0x0007)”.
The type bit is logically-ORed with the preexisting register value, retaining bits for prior, unserviced BC interrupts.
• BC Interrupt Pending (BCIP) bit 0 is set in the “Hardware Pending Interrupt Register (0x0006)”. The BCIP bit is
logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts and the pre-
existing status of the MTIP and RTIP (Bus Monitor and RT) interrupt pending bits.
• If the matching bit is already set in the “Bus Controller (BC) Interrupt Output Enable Register (0x0014)”, an IRQ
output occurs.
If the matching bit in the “Bus Controller (BC) Interrupt Output Enable Register (0x0014)” was not already set (i.e., low
priority polled interrupt), the host can poll the “Bus Controller (BC) Pending Interrupt Register (0x0007)” to detect the
occurrence of BC interrupts, indicated by non-zero value. Reading the “Bus Controller (BC) Pending Interrupt Register
(0x0007)” automatically clears it to 0x0000.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four Interrupt
Output Enable Registers (hardware, BC, RT and SMT). Multiple interrupt-causing events can occur simultaneously, so
single or simultaneous interrupt events can assert the IRQ host interrupt output.
When the host receives an IRQ signal from the device, it identifies the event(s) that triggered the interrupt. Section
9.5 describes two methods for identifying the interrupt source(s). One scheme uses the three low order bits in the
“Hardware Pending Interrupt Register (0x0006)” to indicate when BC, RT and SMT interrupts occur. When BCIP (BC
Interrupt Pending) bit 0 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “Bus Controller (BC) Pending
Interrupt Register (0x0007)” contains a nonzero value and may be read next to identify the specific BC interrupt
event(s). Or, the host can directly interrogate the Interrupt Count & Log Address Register, followed by the Interrupt Log
Buffer. Data sheet section 9.5 has a detailed description.

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HI-6138
11.16.1. Bus Controller (BC) Interrupt Enable Register (0x0010)
Y
TR R R
IR T
EO R
es d
d
es d
G G
ST R
A P
BC T SE
BC Q 3
BC Q 2
BC Q 1
BC Q 0
R rve
ve
R rve
SE D T
R M
BC ER
BC PQ
BC S
C ET
ST A
BC KE
LM
er
IR
IR
IR
e
W
e
M
R
es
BC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
11.16.2. Bus Controller (BC) Pending Interrupt Register (0x0007)

Y
TR RR
IR T
EO R
es d
d
es d
G G
ST R
A P
BC TSE
BC Q3
BC Q2
BC Q1
BC Q0
R rve
ve
R rve
SE DT
R M
BC ER
BC PQ
BC S
C ET
ST A
BC KE
LM
er
IR
IR
IR
e
W
e
M
R
es
BC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
11.16.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014)

Y
TR RR
IR T
EO R
es d
d
es d
G G
ST R
A P
BC TSE
BC Q3
BC Q2
BC Q1
BC Q0
R rve
ve
R rve
SE DT
R M
BC ER
BC PQ
BC MS
C ET
ST A
BC KE
er
IR
IR
IR
e
W
e
M
R
L
es
BC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Three registers govern BC interrupt behavior: the “Bus Controller (BC) Interrupt Enable Register (0x0010)”, the “Bus
Controller (BC) Pending Interrupt Register (0x0007)” and the “Bus Controller (BC) Interrupt Output Enable Register
(0x0014)”. When a bit is set in the “Bus Controller (BC) Interrupt Enable Register (0x0010)”, the corresponding BC in-
terrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded.
Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
When an enabled BC interrupt event occurs, the corresponding bit is set in the “Bus Controller (BC) Pending Interrupt
Register (0x0007)” and the Interrupt Log Buffer is updated. To simplify interrupt decoding, BCIP bit 0 in the “Hardware
Pending Interrupt Register (0x0006)” is also set whenever a message sets at least one bit in the “Bus Controller (BC)
If the corresponding bit is set in the “Bus Controller (BC) Interrupt Output Enable Register (0x0014)”, the IRQ output is
asserted at message completion. The “Bus Controller (BC) Interrupt Output Enable Register (0x0014)” establishes two
priority levels: high priority interrupts generate an IRQ output while low priority interrupts do not. Both priority levels
update the “Bus Controller (BC) Pending Interrupt Register (0x0007)” and Interrupt Log Buffer. The host can detect low
priority (masked) interrupts by polling Pending Interrupt registers.
The table below describes common bits in all three BC interrupt registers.

95
HI-6138
BC Watchdog Timer Interrupt.

15 BCWDT
The BC Frame Timer expired.
BC Selected Message Interrupt.

14 SELMSG The completion of a MIL-STD-1553 message that has bit 4 (SELMSGINT) set in the
message block Control Word.
BC General Purpose Queue Rollover Interrupt.

13 BCGPQ The 64-word circular BC General Purpose Queue Pointer rolled over to its base address
value.
BC Retry Interrupt.
12 BCRETRY The occurrence of a retried message by the BC. If enabled, the interrupt will occur after
the last enabled message retry (one or two) regardless of the outcome, successful or
unsuccessful.
BC Call Stack Pointer Error Interrupt.
The BC subroutine stack depth was violated due to an overflow or underflow condition.
Call stack level is incremented each time a BC “subroutine call” op code (CAL) is
11 CSTKERR executed. Call stack level is decremented each time a BC “subroutine return” op code
(RTN) is executed. The allowed range for the call stack level is 0-7. An interrupt occurs
when a CAL op code executes when stack level is 7. An interrupt also occurs when a
RTN op code executes when stack level is 0.
BC Trap Interrupt.
The following conditions can assert this interrupt:
1. The BC fetched an illegal op code. The BC operation stops when the current 1553
message is complete. An illegal op code is either undefined, fails parity check, and/
or has the wrong value for bits 9-5. When this occurs, BCRUN bit 15 resets to logic
0 in the “Bus Controller (BC) Condition Code Register (Read 0x0037)” and “Bus
Controller (BC) General Purpose Flag Register (Write 0x0037)”.
2. When the CHKFMT bit 13 is set in the “BC (Bus Controller) Configuration Register
(0x0032)”, the “BC Control Word” message format bits 2-0 (mode command, RT-RT
and broadcast message flags) are compared to the stored value(s) for the message
Command Word(s) following the Control Word in the Message Block. When mismatch
occurs between Control Word format bits and Command Word(s), the BCTRAP
10 BCTRAP interrupt is asserted, if enabled. BC instruction list execution continues, so this
condition can be differentiated from illegal op code because BCRUN bit 15 remains
high in the BC Condition Code and GP Flag register, 0x0037. For mode command or
broadcast mismatch, the stored message block Command Word(s) are transmitted.
For RT-RT format mismatch, RT-RT bit 1 in the Control Word has priority, determining
whether the message block is treated as an 8- or 16-word entity. For RT-RT format
mismatch, message failure is likely for this message or the next message block,
since the message block boundary is misplaced. The CHKFMT option bit detects BC
programming problems in the development phase. The option is normally disabled
in the field.
3. In addition, this bit will also be asserted if any of the following conditions occur:
Broadcast Transmit Mode Code with Data, Broadcast MC0 and MC2, Broadcast
Transmit Data, RTRT 2nd Transmit Mode Code without data, RTRT 2nd Command
Receive , RTRT Word Count mismatch.

96
HI-6138
BC Status Set Interrupt.

The BC received an RT Status Word having an unexpected bit value for at least one
of the eight non-reserved status bits. The expected value for these bits (excluding the
BCR bit) is usually 0.
9 STATSET The BCR (broadcast command received) bit can have an expected value of 1 when
BCR Mask Enable bit in the “BC (Bus Controller) Configuration Register (0x0032)” is
logic 0. In this case, the Mask Broadcast bit in the message block Control Word shows
the expected value of the Status Word BCR bit. If the Control Word’s Mask Broadcast
bit is logic 1, the expected value of BCR in the RT Status Word is logic 1.
BC Interrupt Request Bits 3-0.
8−5 BCIRQ3:0 When this 4-bit field is nonzero, the BC executed an IRQ op code. The value of bits 8:5
will equal the value of the 4 LSBs in the parameter associated with the IRQ op code.
The user may define the 4- bit pattern to suit application requirements.
BC Message Error Interrupt.
Any one of the following five conditions will assert this interrupt if enabled
1. RT response time-out.
4 BCMERR
2. BC loopback failure.
3. Incorrect address in RT status word.
4. Minimum gap time violated (if enabled).
BC End of Message Interrupt.
3 BCEOM
The successful completion of a message, regardless of validity.
2−0 Reserved Bits 2-0 cannot be written, and read back 000.

97
HI-6138
12. SIMPLE MONITOR TERMINAL (SMT)

The HI-6138 can operate as an autonomous MIL-STD-1553 Bus Monitor, requiring minimal host support.
12.1. Overview
Simple Monitor Terminal (SMT) has its own dedicated Time Tag counter, and can use either a 16- or 48-bit Time Tag
scheme. The SMT monitor utilizes two circular buffers in RAM: a Command Buffer and a Data Buffer. Each recorded
MIL-STD-1553 message appends a fixed length entry into the Command Buffer and a variable length entry into the
Data Buffer.
The SMT message records a fixed length “message block” in the Command Buffer for each MIL-STD-1553 message.
The advantage of fixed length Command Buffer message blocks is that the host can quickly jump to the block start
address for any message.
The number of words added to the Data Buffer for each message depends on the MIL-STD-1553 message type,
ranging from zero (broadcast mode command without data) to 35 words (for a 32 data word RT-RT command).
Both circular buffers are fully utilized for recording message data. The SMT monitor allows selective monitoring of MIL-
STD-1553 messages, based on the address, subaddress and T/R status in each monitored Command Word, or can
monitor all messages, when preferred. The SMT monitor offers flexible interrupt options.
In “Master Configuration Register 1 (0x0000)”, MTENA bit 8 enables the SMT monitor. If “Master Configuration Register
1 (0x0000)” bit 8 equals logic 0, Bus Monitor operation is disabled. When “Master Configuration Register 1 (0x0000)”
MTENA bit 8 is logic 1, the Bus Monitor is enabled. Operation commences when the receiver first decodes MIL-
STD-1553 activity meeting the “start record” criteria selected by bits 6-5 in the “SMT Configuration Register (0x0029)”.
If monitor operation is underway when “Master Configuration Register 1 (0x0000)” MTENA bit 8 becomes logic 0,
monitor operation stops after completion of any message already underway.
The HI-6138 is configured for SMT operation by writing bits 1-0 in the “SMT Configuration Register (0x0029)”.
When “SMT Configuration Register (0x0029)” bits 1-0 equal 01, the SMT operates with 16-bit Time Tag resolution and
each recorded MIL-STD-1553 message adds a four word entry in the Circular Command Buffer. This is summarized
in Table 8.
Table 8. Message Block in Circular Command Buffer for SMT Monitor using 16-bit Time Tag
Message
Word Word Name Word Function when using 16-bit time tag
Block
Message Command Word.

Message
The MIL-STD-1553 Command Word that initiated the message.
Word 3 Command
Word For an RT-RT message, Receive Command Word 1 is stored here; Transmit Command
Word 2 is the first stored word in the Message Data Block.
Data Block
Word 2 Starting address in the Data Buffer for the corresponding message data block.
Pointer
Message Sixteen bit message time stamp.

Word 1 Time Stamp
Bits 15 ~ 0 Word 0 is the first word in the Command Buffer entry for each message.

98
HI-6138
Message
Block
Block Status Message Block Status Word, defined in Section 12.2.

Word 0
Word Word 0 is the first word in the Command Buffer entry for each message.
When “SMT Configuration Register (0x0029)” bits 1-0 equal 11, the Simple Message Monitor operates with 48-bit
Time Tag resolution. Each MIL-STD-1553 message adds an 8-word entry in the Circular Command Buffer. This is
summarized in Table 9. The expanded message block accommodates two additional Time Tag words, a Message
Length word and a Response Time word not found when using 16-bit Time tag resolution.
Table 9. Message Block in Circular Command Buffer for SMT Monitor using 48-bit Time Tag
Message
Block
Message Command Word.

Message
The MIL-STD-1553 Command Word that initiated the message.
Word 7 Command
Word For an RT-RT message, Receive Command Word 1 is stored here; Transmit Command
Word 2 is the first stored word in the Message Data Block.
Data Block
Word 6 Starting address in the Data Buffer for the corresponding message data block.
Pointer
The Message Length Word indicates the total number of bytes of the 1553 message
including all command words and status words. The range is 2 to 72 bytes,
Message corresponding to 1 to 36 16-bit words stored.
Word 5 Length Word Note: Since the Message Command Word is stored within the Message Block itself, the
(bytes) number of bytes to read from the Message Data Block should be reduced by 2 bytes.
That is, the number of bytes to read from the Message Data Block = Message Length
Word − 2.
The Response Time Word contains two 8-bit fields:
• Bits 15 ~ 8 contains GAP2
• Bits 7 ~ 0 contains GAP1
All GAP values are measured from mid-parity zero crossing of the preceding word, to
Response the mid-sync zero crossing of the Status Word (the gap “dead time” interval plus 2 µs).
Word 4 Time resolution is 100 ns per LSB, so the maximum indicated gap time for GAP1 or
Time Word
GAP2 is 25.5 µs.
For RT-RT messages, the GAP1 byte indicates transmit RT response time, and the
GAP2 byte indicates received RT response time.
For all other messages, the GAP1 byte indicates the only RT response time, and the
GAP2 byte reads 0x00.
Block Status
Word 3 Message Block Status Word, defined in Section 12.2.
Word

99
HI-6138
Message
Block
Message
Word 2 Time Stamp Upper 16-bit word of message 48-bit time stamp.
Bits 47 ~ 32
Message
Word 1 Time Stamp Middle 16-bit word of message 48-bit time stamp.
Bits 31 ~ 16
Message Lower 16-bit word of message 48-bit time stamp.

Word 0 Time Stamp
Bits 15 ~ 0 Word 0 is the first word in the Command Buffer entry for each message.
The Circular Command Buffer address range is bounded by the values in Address List Words 0 and 2. The Circular
Data Buffer address range is bounded by the values in Address List Words 4 and 6. The “Next Address” Words 1 and
5 must be initialized by the host for the first data written after reset, usually to match the Word 0 and Word 4 values
respectively. Thereafter, these values are maintained by the device each time a new MIL-STD-1553 message is
recorded.
Two optional Buffer address interrupts are offered. When enabled, a Command or Data Buffer Address Interrupt
occurs whenever the matching RAM address in the Buffer is written. The Address List contains the address values for
these optional “buffer utilization” interrupts.
For SMT, the 8-word Monitor Address List is defined in Table 10.
Table 10. Monitor Address List for SMT
Address
Word Name Description
List Word
Host initialized with a RAM address value if this interrupt is enabled.

Data Buffer
Word 7 Interrupt If enabled, an interrupt occurs when the matching RAM address is written.
Address Address must occur within the range bounded by Words 4 and 6.
Data Buffer
Word 6 Host initialized, defines SMT Data Buffer upper (rollover) address.
End Address
Must be host initialized, usually to match SMT Data Buffer Start Address.
Data
Word 5 Buffer Next Updated by device each time a new MIL-STD-1553 message is recorded.
Address This value advances through the address range in circular buffer fashion.
Data
Word 4 Buffer Start Host initialized, defines SMT Data Buffer lower address boundary.
Address
Command Host initialized with a RAM address value if this interrupt is enabled.
Buffer
Word 3 If enabled, an interrupt occurs when the matching RAM address is written.
Interrupt
Address Address must occur within the range bounded by Words 0 and 2.

100
HI-6138
Address
Word Name Description
List Word
Command
Word 2 Buffer End Host initialized, defines SMT Circular Command Buffer upper (rollover) address.
Address
Must be host initialized, usually to match Command Buffer Start Address.

Command
Word 1 Buffer Next Updated by device each time a new MIL-STD-1553 message is recorded.
Address This value advances through the address range in circular buffer fashion.
Command
Host initialized, defines SMT Circular Command Buffer lower address boundary. Word 0
Word 0 Buffer Start
occurs at the Address List base address in register 0x002F.
Address
For each monitored MIL-STD-1553 command, the written Command Buffer entry is fixed at 4 or 8 words, depending
on selected Time Tag resolution. Depending on MIL-STD-1553 message type, the written Data Buffer entry varies
in length, ranging from zero words (for broadcast mode code commands without data) to 35 words (for an RT-to-RT
message with 32 data words). Simple Monitor Terminal Data Storage is summarized in Figure 7.

101
HI-6138
Command Data Non-Broadcast Corresponding

Buffer Buffer Message Types Broadcast
Messages
Command Word Data Words 1-32 Data Words:
for Message for Message N+1 Data
.........N
Data 1
Data Block Pointer Data Words
for Message N Transmitting RT
for Message Status Word
Message Time RT-to-BC No Broadcast
Data Words
Stamp, Bits 15-0 (Transmit) Command Version
for Message N-1
Block Status Word Receiving RT
for Message Data Status Word
Buffer 1-32 Data Words: 1-32 Data Words:
Command Data
.........N Data
.........N
Buffer Data Buffer Blocks Data 1 Data 1
for Each Message BC-to-RT Broadcast BC-to-RT
Command Buffer
(Receive) Command (Receive) Command
Single Message Block
Initialized for 16-bit Time Stamp Receiving RT
Register 0x0029 Bits 1-0 equal 01 Status Word
1-32 Data Words: 1-32 Data Words:
Data
.........N Data
.........N
Data Data 1 Data 1
Command Buffer Transmitting RT Transmitting RT
Buffer Status Word Status Word
Command Word Data Words Command Word 2 Command Word 2

for Message N+1 to Transmit RT to Transmit RT
for Message
RT-to-RT Broadcast RT-to-RT
Data Block Pointer Data Words Command Command
for Message for Message N
Message Length Data Words Mode Data Word
Word for Message N-1 Transmitting RT
Response Time Status Word
Word Data Transmit Mode Code No Broadcast
Block Status Word Buffer With Data Version
for Message
Data Buffer Blocks Receiving RT
Message Time for Each Message Status Word
Stamp, Bits 47-32
Mode Data Word Mode Data Word
Message Time
Stamp, Bits 31-16 Receive Mode Code Broadcase Receive
With Data Mode Code With Data
Message Time
Stamp, Bits 15-0
For Broadcast Mode
Command RT Status Word Codes Without Data
Increasing
(MC0 - MC15)
Buffer Memory Transmit or Receive No Status or Data
Address Mode Code Without Data Words Are Recorded
Command Buffer
Single Message Block The number of words stored in the Data Buffer varies
Initialized for 48-bit Time Stamp from message to message, based on message type.
Register 0x0029 Bits 1-0 equal 11
Figure 7. Simple Monitor Terminal (SMT) Data Storage

102
HI-6138
12.2. SMT Block Status Word (BSW) Description

The SMT bus monitor stores a Block Status Word in the Circular Command Buffer for each monitored MIL-STD-1553
message. This word provides information regarding message status, the bus on which the message occurred, whether
errors occurred during the message, and the type of occurring errors. The Block Status Word for SMT is defined as
follows:
D d
es d
es d
es d
es d
d
es d
BI rve
R rve
R rve
R rve
LE rve
R rve
ve
R rve
er
e
e
e
e
e
es
es
es
E
E
EO
TM
SE
IG
W
R
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The device offers an Extended Status reporting option, enabled when bit 2 in “SMT Configuration Register (0x0029)”
is logic 1. When this option is enabled, addition status information is available in the SMT block Status Word.
C W2
R SA
E
C
M
M
G
C
B
SR
S
E
D
W
E
D
SO
R
EO
EO
TM
R
SE
SF
LE
IG
BI
W
G
D
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
SMT Block Status Word
with Extended Status Bits Enabled
End of Message.
15 EOM R/W 0 Bit 15 is set upon completion of a monitored message, whether or not
errors occurred. When EOM is set, SOM bit 14 is concurrently reset.
Start of Message.
14 SOM R/W 0 Bit 14 is set to logic 1 approximately 6 μs after message completion and
is reset to logic 0 at the end of message processing. If the monitor uses
message filtering, SOM is only set for monitored messages.
Bus ID (Bus B / Bus A).
13 BID R/W 0 Bit 13 indicates the bus ID for the message. This bit is logic 0 for a
message occurring on Bus A. This bit is logic 1 for a message occurring
on Bus B.

103
HI-6138
Error Occurred Flag.

This bit indicates a message error was encountered. This bit is set when
one or more of the following conditions are true (logical-OR):
• RT Status Word with ME bit asserted (except for Mode Commands
Transmit Status Word and Transmit Last Command).
• An unfinished message is superseded by another valid command
• RT status with busy bit asserted and incorrect number of data words
• Bit 9 Response Timeout is set
• Bit 5 Length (Word Count) Error is set
• Bit 4 Sync Type Error is set
• Bit 3 Invalid Word Error is set
• Bit 2 RT-RT Gap / Sync / Address Error is set
• Bit 1 RT-RT Command Word 2 Error is set (except as noted)
12 EO R/W 0 • Bit 0 Command Word Content Error is set (except as noted)
Note: EO bit is not set when Bit 10 Illegal Gap Error is set. This ensures
that otherwise valid messages (e.g. RT responds faster than minimum
gap time, but there are no other errors) are stored in the monitor. The
gap error is flagged by assertion of bit 10 IGE below.
There are three exceptions where register bit 0 or 1 is set without

affecting bit 12 state:
Bit 1 RT-RT Command Word 2 Errors that do not assert bit 12

• RT-RT Transmit Command Word 2 subaddress field equals 00000
or 11111 (mode code command indicated)
• RT-RT Transmit Command Word 2 has the same RT Address as
Receive Command Word 1
Bit 0 Command Word Content Error that does not assert bit 12
• Undefined receive mode code 0~15 decimal.
RT-to-RT Transfer
11 RR R/W 0 When logic 1, bit 11 indicates an RT-to-RT message, beginning with two
contiguous Command Words.
Illegal Gap Error

10 IGE R/W 0 When logic 1, bit 10 indicates an illegal gap occurred on the bus, other
than Response Timeout.
Response Timeout
When logic 1, bit 9 indicates a response timeout occurred. This bit is
9 TM R/W 0 set if an RT Status Word associated with this message failed to arrive
within the response time interval specified by bits 15-14 in the “SMT
Configuration Register (0x0029)”.

104
HI-6138
Good Data Block Transfer

Bit 8 is set to logic 1 following completion of a valid, error-free message.
8 GDB R/W 0 This bit is reset to logic 0 following completion of a message in which
error occurred. If an RT responds to a transmit command with Busy
status and does not transmit the commanded data words, this is not
considered a message error that causes GDB reset.
Data Buffer Rollover
7 DSR R/W 0 Bit 7 is logic 1 to indicate that this message overran the monitor Data
Buffer end address, causing the storage pointer to roll over to the base
address.
Status Flag Set

6 SFS R/W 0
Bit 6 is logic 1 when a status bit was set in an RT Status Word response.
Word Count (Length) Error

Bit 5 indicates that the number of data words transmitted by the BC or
5 LE R/W 0 RT differs from the Word Count specified in the Command Word. An RT
Status Word with the Busy bit set will not cause Word Count Error. A
transmit command with Response Timeout will not cause Word Count
Error.
Sync Type Error

Bit 4 is logic 1 to indicate that a BC transmitted data sync with a
4 SE R/W 0 Command Word, or a command / status sync occurred with Data Word,
or an RT responded with data sync in its Status Word and/or command/
status sync in a Data Word.
Invalid Word Error (WE)
3 WE R/W 0 Bit 3 is logic 1 indicate on invalid word error occurred. This includes
Manchester decoding errors in the sync pattern or word bits, or the
wrong number of bits in the word, or parity error.
RT-to-RT Gap/Sync/Address Error (RRGSA)

Bit 2 is logic 1 if one or more of the following RT-RT message conditions
occur:
• MT Gap Check is enabled (bit 12 equals 1 in “SMT Configuration
Register (0x0029)”) and an RT Status Word is received having a
2 RRGSA R/W 0 response time less than 4µs, per MIL-STD-1553B (mid-parity to mid-
sync). In other words, the bus “dead time” was less than 2µs.
• One of the RTs responds with an invalid Status Word, having a sync
error, a Manchester encoding error, bit count error and/or parity error
• One of the RT Status Words contains an RT Address that differs
from the RT Address in the corresponding Command Word.

105
HI-6138
RT-to-RT Command Word 2 Error (RRCW2)

Bit 1 is logic 1 if an RT-to-RT message occurs (two contiguous
Command Words) with one or more of the following illogical conditions:
• Transmit Command Word 2 T/R bit equals 0 (receive)
1 RRCW2 R/W 0 • Transmit Command Word 2 subaddress field equals 00000 or 11111
(mode command indicated)
• Transmit Command Word 2 has the same RT Address as Receive
Command Word 1
• Transmit Command Word 2 has sync error
Command Word Content Error (CWCE)
Bit 0 is logic 1 if a received Command Word violates one or more MIL-
STD-1553B requirements:
• A non-mode code broadcast transmit Command Word occurred.
0 CWCE R/W 0 (non-mode has 5-bit subaddress field equal to decimal 1~30)
• A receive mode code Command Word was received with mode code
in the range of 0~15 decimal (undefined)
• A broadcast transmit mode code command occurred having a mode
code value for which broadcast is not allowed (mode code = decimal
0, 2, 16, 18 or 19)
12.3. SMT Message Filter Table

The Simple Monitor Terminal can select messages for monitoring through the use of a 128-word MT Filter Table,
located at fixed RAM address 0x0100. When the table bit corresponding to a new message Command Word is logic
1, that message is ignored by the monitor. If the table bit is logic 0, that message is recorded.
After MR master reset, 100% of MIL-STD-1553 messages are monitored, since the entire table address range 0x0100
through 0x017F inclusive is 0x0000. The result is that every valid Command Word, received on an idle bus, marks the
start of a new MIL-STD-1553 message recorded by the monitor. The Message Filter Table is addressed using three
fields in the received Command Word: the 5-bit RT Address field, the T/R Transmit/Receive bit, and the MSB of the
5-bit Subaddress field. This is illustrated in Figure 8.
Bit Fields Comprising Each Received Command Word

Terminal Word Count
Command Address T/R Subaddress (Mode Code)
Sync TA4:0 Bit SA4:0 WC4:0
Filter Table
0 00 0 0 0 01 0 Address
Figure 8. Deriving the Monitor Filter Table Address from the Received Command Word

106
HI-6138
Each RT Address from 0 to 31 decimal has four 16-bit table words: two words enable/disable individual Receive
Subaddresses, two more words enable/disable individual Transmit Subaddresses. The first four table words apply to
Subaddress 0 and are illustrated in Table 11. This 4-word pattern repeats for all 32 Subaddresses, 0-31 decimal.
Table 11. SMT Message Filter Table
Filter Table addresses

RT Address 31 Subaddresses (4 words)
0x017C - 0x017F
0x0178 - 0x017B
. .
. .
. .
0x0108 - 0x010B
0x0104 - 0x0107
Filter Table address 0x0103 RT Address 0, Transmit Subaddresses 31 to 16
Word Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit SA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Filter Table address 0x0102 RT Address 0, Transmit Subaddresses 15 to 0
Word Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit SA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Filter Table address 0x0101 RT Address 0, Receive Subaddresses 31 to 16
Word Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive SA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Filter Table address 0x0100 RT Address 0, Receive Subaddresses 15 to 0
Word Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive SA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A subaddress message is monitored when the corresponding word
bit equals logic 0. The message is not monitored when the bit equals 1.

107
HI-6138
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION

In addition to the registers described here, the SMT Bus Monitor also utilizes one or more Memory Address Pointer
registers (described in Section 9.12) for managing SPI read/write operations.
13.1. SMT Configuration Register (0x0029)

es d
H d
TT d
TS d
TX d
d
TC 0
R RIW
TS 1
TT 1
es 0
R rve
G rve
M ve
M rve
M rve
ve
M RR
M RR
48 MF
M O1
R O0
M TB
R TB
R T
R K
er
er
BT
e
e
e
TT
TT
es
es
es
es
C
M
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 MR Reset
RW W RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
MT Time Out Select.

This 2-bit field selects the Monitor “no response” time-out delay from
four available selections. Excluding RT-RT commands, the delay is
measured from command word mid-parity bit to status word mid-sync.
Bus Time Out

RT-RT Bus RT-RT Time
Bit 15:14 Dead (excludes RT-
Dead Time Out
Time RT)
15 − 14 MTTO1:0 R/W 0 00 16μs 18μs 19μs 61μs
01 21μs 23μs 24μs 66μs
10 80μs 82μs 80μs 122μs
11 138μs 140μs 138μs 180μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This adds
40µs for the embedded transmit command word and transmit-RT status
word within this interval.
Bit 13 is not used by the bus monitor operating in SMT mode.

13 Reserved W 0
Initialize this bit to logic 0.
Gap Check.
When this bit equals 1, the monitor evaluates inter-message gaps and
RT response times for a minimum preceding bus dead time of 2 µs.
This dead time corresponds to an inter-message gap of 4µs, measured
per MIL-STD-1553, from mid-parity zero crossing of the preceding
12 GCHK R/W 0
word, to mid-sync zero crossing of the following word. A minimum gap
time violation results in a Format Error in the Block Status Word for the
message.
When this bit equals 0 (recommended), the monitor does not check for
short inter-message gap times.
11 Reserved R/W 1 Bit 11 is not used.
10 Reserved R/W 0 Bit 10 is not used.

108
HI-6138
Monitor Time Tag Message Bit Select.

This 2-bit field selects the bit within the MIL-STD-1553 message where
time stamp occurs. Time stamp occurs at mid-bit transition:
Bit 9:8 Time Tag Event
00 Last Bit of Last Word in Message
01 First Bit of First (Command) Word in Message

9−8 MTTTB1:0 R/W 0 10 Last Bit of First (Command) Word in Message
Time tag update disabled, stores last recorded

11 time tag from when bits 9:8 did not equal [11]
otherwise, stores 0.
For options 00 and 10, the “Last Bit” precedes the word’s parity bit. For
option 01, the “First Bit” occurs 0.5µs after command sync. While “First
Word” generally denotes a command word, message recording can
begin with a data word when register bit 5 equals 1.
Bit 7 is not used by the bus monitor.

7 Reserved R/W 0

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HI-6138
MT Start-Record Requirement 1:0.

When register bits 6-5 equal 00, the MT starts recording a new
MIL-STD-1553 message when a properly encoded, complete
MIL-STD-1553 word with command sync is decoded: The command
sync is followed by 16 properly encoded data bits plus a 17th parity bit
expressing odd parity. No data is recorded until this condition is met.
This is the usual setting. (default setting)
MIL-STD-1553 message when a properly encoded, complete
MIL-STD-1553 word with command sync or data sync is decoded.
The properly encoded command sync (or data sync) is followed by 16
properly encoded data bits plus a 17th parity bit expressing odd parity.
If recording begins with data sync, the Sync Error flag will be set in the
Block Status Word.
MIL-STD-1553 message upon detection of a properly encoded
6−5 MTSRR1:0 R/W 0 command sync with two contiguous data bits. If the properly
encoded command sync with two contiguous data bits does not result in
a valid command word, the Invalid Word Error is set in the Block Status
Word. This selection begins recording for complete MIL-STD-1553
command words as well as for command word fragments, or command
words with bad parity. Under some circumstances, this record option
might be helpful for debugging MIL-STD-1553 communication failure.
When register bits 6-5 equal 11, the MT starts recording new bus activity
upon detection of any properly encoded sync (command or data)
with two contiguous data bits. This selection begins recording for
complete MIL-STD-1553 command or data words as well as for word
fragments, or words with bad parity. If the properly encoded sync with
two contiguous data bits does not result in a valid Manchester II word,
the Invalid Word Error is set in the Block Status Word. If recording
begins with data sync, the Sync Error flag will be set in the Block Status
Word. Under some circumstances, this record option might be helpful for
debugging MIL-STD-1553 communication failure.
MT Continue Recording After Invalid Word.

When bit 4 equals 0, the MT stops recording an incomplete message
when an invalid MIL-STD-1553 word is decoded. The invalid word is not
stored, and the MT awaits word detection per register bits 6-5 before the
4 MTCRIW R/W 0 next MIL-STD-1553 message is recorded. (default)
When bit 4 equals 1, the MT continues recording an incomplete
message when an invalid MIL-STD-1553 word is decoded. The invalid
word is stored and the MT continues monitoring the message until
completion or time-out occurs.
Bit 3 is not used by the bus monitor.

3 Reserved R/W 0

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HI-6138
Extended Message Flag Enable.

Usually register bit 2 is set to logic 1 to enable expanded status/error
flags, occupying the “reserved” bit positions in the SMT Block Status
2 MTXMF R/W 0
Word.
When register bit 2 equals 0, the recorded status/error flags are limited
(see “SMT Block Status Word (BSW) Description”).
48-Bit Time Tag / 16-Bit Time Tag

When register bit 1 equals 0, the SMT time tag counter operates with 16-
bit resolution and the recorded entry for each MIL-STD-1553 message in
the Command Buffer is four 16-bit words.
1 48BTT R/W 0 When register bit 1 equals 1, the SMT time tag counter operates with
48-bit resolution. To record the 48-bit time count, the entry for each MIL-
STD-1553 message in the Command Buffer is eight 16-bit words. Two
of the words added are used for Response Time and Message Length
words. See Section 13.5.
0 Reserved R 1 This bit is not used and always reads logic “1”.
13.2. SMT Bus Monitor Address List Start Address Register (0x002F)
0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and is fully maintained by the host. After MR pin master reset, this register is
initialized with 0x00B0, the default base address of the MT Address Table in device RAM. The host can overwrite the
default base address. This register is not affected by MT soft reset, when the MTRESET bit is asserted in the “Master
Status and Reset Register (0x0001)”. The Address List for SMT mode is summarized in Table 10 on page 100.
13.3. SMT Next Message Command Buffer Address (0x0030)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is read-only and is updated by the MT upon completion of a monitored MIL-STD-1553 message.
This register is cleared after MR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the “Master
Status and Reset Register (0x0001)”. This register contains the address for the first word to be stored in MT Command
Buffer, for the next MIL-STD-1553 message. After the first post-reset message is logged, this register mirrors the value
contained in SMT Address List word 1 (see Table 10 on page 100).
The MT logic only updates this “next message address” register after message completion. Therefore, after reset or
after the host has changed the “SMT Bus Monitor Address List Start Address Register (0x002F)”, this register does not

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contain a pointer address until processing for the next message is completed. If the read value equals zero, the “next
message address” is the Command Buffer starting address.
13.4. SMT Last Message Command Buffer Address (0x0031)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is read-only and is updated by the MT upon completion of a monitored MIL-STD-1553 message.
This register is cleared after MR pin master reset or by MT soft reset, when the MTRESET bit is asserted in the “Master
Status and Reset Register (0x0001)”.
This register contains the RAM address for the first word stored in the Circular Command Buffer for the last completed
MIL-STD-1553 message.
13.5. SMT Bus Monitor Time Tag Count Register (0x003A)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
When MT Configuration Register bits 1-0 equal 01, the Simple Message Monitor operates with 16-bit Time Tag
resolution and register 0x003A contains the full 16-bit Time Tag count.
When MT Configuration Register bits 1-0 equal 11, the Simple Message Monitor operates with 48-bit Time Tag
resolution and the full Time Tag Count requires the above register plus two additional registers:
13.6. SMT Bus Monitor Time Tag Count Mid Register (0x003B)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
13.7. SMT Bus Monitor Time Tag Count High Register (0x003C)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
When configured for 48-bit time base operation, count bits 47-17 reside in register 0x003C, count bits 31-16 reside in
register 0x003B while register 0x003A contains bits 15-0.
The host cannot directly write these registers but uses other methods to control or read Time Tag count. By writing bits
15-14 in the “Time Tag Counter Configuration Register (0x0039)”, the host can clear time tag count to zero, copy the
current time count to the SMT Time Tag Utility Register(s), or load the current value contained in the SMT Time Tag
Utility Register(s) into the SMT Time Tag counter(s). Finally, the SMT Time Tag Match Register(s) provide capability for

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HI-6138
host interrupts when the time tag count reaches any predetermined 16- or 48-bit value. For further information, refer
to the description of the “Time Tag Counter Configuration Register (0x0039)”.
13.8. SMT Bus Monitor Time Tag Utility Register (0x003D)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
When “SMT Configuration Register (0x0029)” bits 1-0 equal 01, the Simple Message Monitor operates with 16-bit Time
Tag resolution and register 0x003D is the only Time Tag Utility register needed.
Tag resolution and “utility” operations require the above register plus two additional registers:
13.9. SMT Bus Monitor Time Tag Utility Mid Register (0x003E)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These registers are read-write and are cleared after MR pin Master Reset. This utility register triplet is used for
simultaneously loading or reading a 16- or 48-bit value into or from the SMT Time Tag Counter. Please refer to the
description for bits 15-14 in the “Time Tag Counter Configuration Register (0x0039)”.
Loading a 16-bit or 48-bit value into the SMT Time Tag Count Register(s)
When loading or clearing Time Tag count, the 16-bit value in ”SMT Bus Monitor Time Tag Utility Register (0x003D)” is
copied into ”SMT Bus Monitor Time Tag Count Register (0x003A)”. If configured for 48-bit time stamp operation, count
bits 47-17 and count bits 31-16 are simultaneously copied from Time Tag Utility Registers 0x003F and 0x003E into
SMT Time Tag Count Registers 0x003C and 0x003B respectively.
Capturing a 16-bit or 48-bit value from the SMT Time Tag Count Register(s)
When capturing Time Tag count, the 16-bit value in ”SMT Bus Monitor Time Tag Count Register (0x003A)” is copied
into “SMT Bus Monitor Time Tag Utility Register (0x003D)”. If configured for 48-bit time stamp operation, count bits 47-
17 and count bits 31-16 in SMT Time Tag Count Registers 0x003C and 0x003B are simultaneously copied into Time
Tag Utility Registers 0x003F and 0x003E respectively.

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13.11. SMT Bus Monitor Time Tag Match Register (0x0040)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Tag resolution and register 0x0040 is the only Time Tag Match register needed.
Tag resolution and time tag matching operations require the above register plus two additional registers:
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
These registers are read-write and are cleared after MR pin Master Reset. When the MTTTM bit 6 is logic 1 in the
“Hardware Interrupt Enable Register (0x000F)”, an interrupt occurs when the MT time tag count matches the value
stored in this register triplet. If the MT is configured for 16-bit time tag, Time Tag Match Register 0x0040 is compared
to Time Tag Count register 0x003A for match determination.
If configured for 48-bit time tag operation, count bits 47-17 and 31-16 in Time Tag Match Registers 0x0042 and 0x0041
are also compared to MT Time Tag Count Registers 0x003C and 0x003B for 48-bit match determination.
Please refer to the description for MTTTM bit 6 in the “Hardware Interrupt Registers” on page 41.

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13.14. SMT Bus Monitor Interrupt Registers and Their Use

Interrupt Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. When the SMT is enabled,
three additional registers are dedicated to SMT interrupts. Comparable to the Hardware Interrupt register triplet, the
SMT has
• An “SMT Bus Monitor Interrupt Enable Register (0x0011)” to enable and disable interrupts
• An “SMT Bus Monitor Pending Interrupt Register (0x0008)” to capture the occurrence of enabled interrupts
• An “SMT Bus Monitor Interrupt Output Enable Register (0x0015)” to enable IRQ output to host, for pending
enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available for the SMT. At initialization, bits are set in the “SMT Bus
Monitor Interrupt Enable Register (0x0011)” to identify the interrupt-causing events for the SMT which are heeded by
the device. Most SMT applications only use a subset of available SMT interrupt options. Interrupt-causing events are
ignored when their corresponding bits are reset in the “SMT Bus Monitor Interrupt Enable Register (0x0011)” . Setting
an Interrupt Enable Register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit
was zero.
Whenever an SMT interrupt event occurs (and the corresponding bit is already set in the “SMT Bus Monitor Interrupt
Enable Register (0x0011)”), these actions occur:
• A bit corresponding to the interrupt type is set in the “SMT Bus Monitor Pending Interrupt Register (0x0008)”. The
type bit is logically-ORed with the preexisting register value, retaining bits for prior, unserviced SMT interrupts.
• MT Interrupt Pending (MTIP) bit 1 is set in the “Hardware Pending Interrupt Register (0x0006)”. The MTIP bit is
logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts and the pre-
existing status of the BCIP and RTIP (Bus Controller and RT) interrupt pending bits.
• If the matching bit is already set in the “SMT Bus Monitor Interrupt Output Enable Register (0x0015)”, an IRQ
output occurs.
If the matching bit in the “SMT Bus Monitor Interrupt Output Enable Register (0x0015)” was not already set (i.e., low
priority polled interrupt), the host can poll the “SMT Bus Monitor Pending Interrupt Register (0x0008)” to detect the
occurrence of SMT interrupts, indicated by non-zero value. Reading the “SMT Bus Monitor Pending Interrupt Register
(0x0008)” automatically clears it to 0x0000.
Output Enable registers (hardware, BC, RT and SMT). Multiple interrupt-causing events can occur simultaneously, so
“Hardware Pending Interrupt Register (0x0006)” to indicate when BC, RT and SMT interrupts occur. When MT Interrupt
Pending (MTIP) bit 1 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “SMT Bus Monitor Pending
Interrupt Register (0x0008)” contains a nonzero value and may be read next to identify the specific SMT interrupt
Buffer. Section “9.5. Hardware Interrupt Behavior” has a detailed description.

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13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011)
T
T
TE R
es d
es ved
es d
d
es d
es d
es d
es d
es d
BU d
BU O
BU O
BU A
TM A
R rve
R rve
ve
R r ve
R r ve
R ve
R rve
R ve
C rve
R OM
M ER
D FM
M FM
D FR
C FR
er
er
er
er
e
e
e
e
e
es
es
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
13.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008)

T
T
TE R
es d
es ved
es d
d
es d
es d
es d
es d
es d
BU d
TM A
BU O
BU O
BU A
R rve
R rve
ve
R r ve
R r ve
R ve
R rve
R ve
C rve
R OM
M ER
D FM
M FM
D FR
C FR
er
er
er
er
e
e
e
e
e
es
es
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
13.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015)

T
T
TE R
es d
es ved
es d
d
es d
es d
es d
es d
es d
BU d
BU A
TM A
BU O
BU O
R rve
R rve
ve
R rve
R rve
R ve
R rve
R ve
C rve
R OM
M ER
D FM
M FM
D FR
C FR
er
er
er
er
e
e
e
e
e
es
es
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Three registers govern SMT interrupt behavior: the SMT Interrupt Enable Register, the SMT Pending Interrupt Register
and the SMT Interrupt Output Enable Register. When a bit is set in the SMT Interrupt Enable Register, the corresponding
SMT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally
disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the
bit was zero.
When an enabled SMT interrupt event occurs, the corresponding bit is set in the SMT Pending Interrupt Register
and the Interrupt Log Buffer is updated. To simplify interrupt decoding, MTIP bit 1 in the “Hardware Pending Interrupt
Register (0x0006)” is also set whenever one or more bits are set in the SMT Pending Interrupt Register.
If the corresponding bit is already set in the SMT Interrupt Output Enable Register, the IRQ output pin is asserted at
Pending Interrupt Register assertion. The SMT Interrupt Output Enable Register establishes two priority levels: high
priority interrupts generate an IRQ output while low priority interrupts do not. Both priority levels update the SMT
Pending Interrupt Register and the Interrupt Log Buffer. The host detects low priority (masked) interrupts by polling
SMT Pending Interrupt Register.
The table below describes the bit descriptions shared by all three SMT interrupt registers.

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These bits are not used in SMT monitor mode. They should be initialized logic 0 in the
15 − 9 Reserved “SMT Bus Monitor Interrupt Enable Register (0x0011)”. These bits will always read logic
0 in the “SMT Bus Monitor Pending Interrupt Register (0x0008)”.
Command Buffer Rollover Interrupt.

8 CBUFRO The Command Buffer Pointer value (Word 1 in the SMT Address List) has rolled over to
the Command Buffer Start Address (Word 0 in the SMT Address List).
Data Buffer Rollover Interrupt.

7 DBUFRO The Data Buffer Pointer value (Word 5 in the SMT Address List) has rolled over to the
Data Buffer Start Address (Word 4 in the SMT Address List).
Command Buffer Address Match Interrupt.

6 CBUFMAT The Command Buffer Pointer value (Word 1 in the SMT Address List) has reached the
Command Buffer Address Match value in Word 3 of the SMT Address List.
Data Buffer Address Match Interrupt.

5 DBUFMAT The Data Buffer Pointer value (Word 5 in the SMT Address List) has reached the Data
Buffer Address Match value in Word 7 of the SMT Address List.
SMT Message Error Interrupt.
4 MTMERR This bit will be set if EO bit 12 is set in the SMT Block Status Word (see “12.2. SMT
Block Status Word (BSW) Description” for details).
SMT End of Message Interrupt.
3 MTEOM
Successful completion of a MIL-STD-1553 message, regardless of validity.

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14. REMOTE TERMINAL − OVERVIEW

The HI-6138 can operate as a MIL-STD-1553 Remote Terminal, requiring minimal host support. When the Remote
Terminal (RT) is enabled, its configuration and operation is nearly identical to the Holt HI-6121 integrated circuit. The
Remote Terminal has its own Descriptor Table, command Illegalization Table and host interrupt configuration.
The following signal pins are provided for the Remote Terminal:
• RT Terminal Address 4 - 0 input pins
• RT Terminal Address Parity input pin
• RT (Address) Lock input pin
• RT Subsystem Fail input pins
• RT Mode Code 8 (Reset Remote Terminal) output pins
By writing the “Master Status and Reset Register (0x0001)” , the Remote Terminal can be independently reset using
“soft reset”. The RT can be configured to automatically assert soft reset when a valid “Reset Remote Terminal” mode
code command is received. In this configuration, the serial auto-initialization EEPROM should already be programmed
with the desired attributes for the terminal.
In this section of the data sheet, the Remote Terminal registers are described first, followed by the details for configuring
and operating the RT.

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15. REMOTE TERMINAL REGISTERS

In addition to the registers described here, the RT can also utilize one or more Memory Address Pointer registers (de-
scribed in Section 9.12) for managing SPI read/write operations.
15.1. Remote Terminal Configuration Register (0x0017)
1 D
8O T
C P0
1 1
BC V
T W
C 2
M A
PT
C S
C P
C P
O V
SM CE
R HA
BC HB
D IN
U EN
M OB
M 6O
M 7O
M 7O
AU IT
AL DB
R O1
R O0
N IN
TR P
ST
TB
TI
N
N
1
X
TT
TT
TI
TI
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
RT-RT Time Out Select.

This 2-bit field selects the “no response” time-out delay for RT-to-RT receive
commands from four available selections:
Bit 15:14 Bus Dead Time RT-RT Time Out
00 15μs 57μs
01 20μs 62μs
15 − 14 RTTO1:0 R/W 0
10 80μs 122μs
11 138μs 180μs
For RT-RT commands, time out delay is measured per Figure 8 in the RT
Validation Test Plan, SAE AS4111. That is, from mid-parity of the receive
command to mid-sync of the first received data word. This interval includes 20µs
each for the embedded transmit command word and transmit-RT status word
within this span.
RT Bus A Inhibit.
If this bit is logic 1, Bus A is inhibited, as defined by the BSDTXO bit in “Master
Configuration Register 1 (0x0000)”. The BSDTXO bit offers two options: inhibit
13 RTINHA R/W 0 transmit and receive, or inhibit only transmit.
Note: If this bit is logic 0, Bus A is not inhibited here but its operation may
otherwise be globally inhibited by logic 1 at the TXINHA pin, or logic 1 at the
TXINHA bit in the “Master Status and Reset Register (0x0001)”.
RT Bus B Inhibit.
If this bit is logic 1, Bus B is inhibited, as defined by the BSDTXO bit in “Master
Configuration Register 1 (0x0000)”. The BSDTXO bit offers two options: inhibit
12 RTINHB R/W 0 transmit and receive, or inhibit only transmit.
Note: If this bit is logic 0, Bus B is not inhibited here but its operation may
otherwise be globally inhibited by logic 1 at the TXINHB pin, or logic 1 at the
TXINHB bit in the “Master Status and Reset Register (0x0001)”.

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HI-6138
Broadcast Commands Invalid.

If this bit is high, commands addressed to RT address 31 are treated as invalid:
11 BCSTINV R/W 0 There is no terminal recognition of commands to RT address 31; there is no RT
command response, and no status updating for the benefit of following “transmit
status” or “transmit last command” mode commands. If this bit is low, commands
addressed to RT address 31 are treated as valid broadcast commands.
Dynamic Bus Control Enable.

When this bit is logic 1, the RT accepts bus control after receiving a valid
legal “dynamic bus control” mode command. After automatically responding
an RT Status Word with DBCA status bit 1 set, the RTSTEX bit in the “Master
Configuration Register 1 (0x0000)” resets to 0 and the BCSTRT bit in the
“Master Configuration Register 1 (0x0000)” is set to logic 1. If automatic dynamic
bus control is allowed, the BCENA register bit in the “Master Configuration
Register 1 (0x0000)” must be logic 1, and the bus controller should be fully
initialized in advance to permit immediate operation.
10 DBCENA R/W 0
To assert host control over BC switch-in timing, keep the BCENA register bit in
the “Master Configuration Register 1 (0x0000)” reset to 0; this option’s automatic
BCSTART bit-set then does nothing. When ready to commence BC operation,
the host first sets the BCENA register bit, then the BCSTART bit in the “Master
Configuration Register 1 (0x0000)” to start BC.
When this bit is logic 0, the host must perform all actions necessary to change
from RT to Bus Controller mode. Typically the RT Descriptor Table is configured
to generate an IWA interrupt to alert the host upon receiving a valid legal
Dynamic Bus Control mode code command, MC0.
Undefined Mode Codes Invalid.

This bit determines whether the RT treats undefined mode code commands
as valid (default) or invalid commands. This bit applies only to the following
undefined mode code commands:
• Mode Codes 0 through 15 with T/R bit = 0
• Mode Codes16, 18 and19 with T/R bit = 0
• Mode Codes 17, 20 and 21 with T/R bit = 1
9 UMCINV R/W 0 If this bit is low (default state after MR pin reset) undefined mode code
commands are considered valid, and RT response is based on individual mode
command settings in the Illegalization Table: If mode command is legal, the RT
“responds in form” and updates status. If a mode command is illegal, the RT
asserts Message Error status and (if non-broadcast) transmits only its Status
Word without associated data word.
If this bit is high, undefined mode code commands are treated as invalid: There
is no RT recognition of an invalid command, no RT command response, and
no status updating for the benefit of following “transmit status” or “transmit last
command” mode commands.
Notice 2 Broadcast Data Storage.

If this bit is high, the terminal stores data associated with broadcast commands
8 NOTICE2 R/W 0 separately from data associated with non-broadcast commands to meet the
requirements of MIL-STD-1553B Notice 2. If this bit is low, broadcast command
data is stored in the same buffer with data from non-broadcast commands.

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HI-6138
Simplified Mode Command Processing.
7 SMCP R/W 0 When this bit is asserted, the remote terminal applies “Simplified Mode
Command Processing” for all valid mode code commands, as described in
Section 18.5 on page 191.
Temporary Receive Data Buffer.

When this bit is asserted, the remote terminal enables a temporary receive data
buffer used during receive commands. See Section 16.3 on page 145. When
this bit is asserted, the RT stores received data words in a 32-word data buffer
6 TRXDB R/W 0 during message processing. Only after error-free message completion, are
the buffered words written into the data buffer memory assigned to the specific
subaddress in the RT Descriptor Table. This bit should only be modified when
RTSTEX bit is low in “Master Configuration Register 1 (0x0000)” (see Section
9.1 on page 28). Changing the TRXDB bit when the RTSTEX configuration bit
is logic-1 causes unpredictable results.
Alternate BIT Word Enable.

When this bit is logic 0, the remote terminal responds to a “transmit BIT word”
mode command (MC19) by sending the word stored in its Built-In Test Word
register. The Built-In Test Word register resides at address 0x001E.
5 ALTBITW R/W 0 When this bit is logic 1, the remote terminal responds to a “transmit BIT word”
mode command (MC19) by sending the word stored in its Alternate Built-In
Test Word register. The Alternate Built-In Test Word register resides at address
0x001F. Using an Alternate Built-In Test Word register allows the user to fully
define the BIT word, while the default Built-In Test Word register locations
contain several predefined, device-controlled status bits.

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HI-6138
Automatic Bus Shutdown Enable.

Note: Mode commands MC4 and MC5 are not affected by the AUTOBSD bit,
but are included in this description to present a complete picture of device
response to bus shutdown mode commands.
The Bus Controller exercises “shutdown“ control over Remote Terminal
connections to the inactive MIL-STD-1553 bus using the “transmitter shutdown”
(MC4) or “selected transmitter shutdown” MC20 (decimal) mode code
commands. These apply only to the inactive bus. The RT cannot shutdown
the bus where the command is received. When the inactive bus transmitter is
shutdown, the device inhibits further transmission on that bus for the affected
RT. Once shutdown, the transmitter can be reactivated by (a) an “override
transmitter shutdown” (MC5) mode command, (b) an “override selected
transmitter shutdown” (MC21) mode command, (c) a “reset remote terminal”
(MC8) mode command, (d) asserting hardware MR master reset or (e) software
reset initiated by setting the RTRESET bit 10 in “Master Status and Reset
4 AUTOBSD R/W 0 When the AUTOBSD bit is reset, the device automatically performs bus
shutdown and shutdown override in response to mode commands. When the
AUTOBSD bit is set, the device only transmits status; the host must perform bus
shutdown and override duties by asserting control of the TXINHA and TXINHB
bits in “Master Configuration Register 1 (0x0000)”, or by controlling the input
pins with the same function.
Mode commands MC4 (”transmitter shutdown”) and MC5 (”override transmitter
shutdown”) have unconditional shutdown or override response. When MC4
is received, the terminal fulfills shutdown for the inactive bus, disabling the
transmitter and receiver, or transmitter only, depending on the state of the
BSDTXO bit in “Master Configuration Register 1 (0x0000)”. The device affirms
shutdown status by setting the corresponding “shutdown status” bits 15-12 in
the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”. When mode
command MC5 is received, inactive bus transmit and receive is automatically
reenabled by the device; “shutdown override” status is affirmed by resetting the
corresponding “shutdown status” bits 15-12 in the “Remote Terminal Built-In Test
(BIT) Word Register (0x001E)”.

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The “selected transmitter shutdown” (MC20) and “override selected transmitter

shutdown” (MC21) mode commands act similarly to MC4 and MC5 respectively,
except bus shutdown (or shutdown override) is conditional, based on the value
of a mode data word received with the command. To act on a given bus, the
received mode data word must match a predetermined “bus select” value. Bus
shutdown (or shutdown override) can only act on the inactive bus, and only
when the received mode data word matches the “bus select” value for that bus.
When a MC20 mode data word matches the “bus select” value for the inactive
bus, the terminal fulfills shutdown for the inactive bus, disabling the transmitter
and receiver, or transmitter only, depending on the state of the BSDTXO bit
in “Master Configuration Register 1 (0x0000)”. The device affirms shutdown
status by setting the corresponding “shutdown status” bits 15-12 in the “Remote
Terminal Built-In Test (BIT) Word Register (0x001E)”. When a MC21 mode data
word matches the “bus select” value for the inactive bus, the terminal fulfills
shutdown override for the inactive bus, enabling the transmitter (and receiver,
if BSDTXO bit in “Master Configuration Register 1 (0x0000)” is logic 0). The
device affirms override status by resetting the corresponding “shutdown status”
bits 15-12 in the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”.
AUTOBSD When the AUTOBSD bit equals zero, unique “bus select” values should
4 R/W 0
(continued) be initialized by the host in the “Remote Terminal Bus A Select Register
(0x001C)” and “Remote Terminal Bus B Select Register (0x001D)” for
fulfillment of “selected transmitter” shutdown and override mode commands.
When AUTOBSD equals zero, transmitter shutdown (or shutdown override)
automatically occurs when the received mode data value matches the inactive
bus “Bus Select” register.
Below shows device response for “transmitter shutdown” and “override
transmitter shutdown” mode code commands for different configuration options:
The AUTOBSD bit in RT Configuration Register 0x0017 is logic 0 or 1
In BIT Word
Register,
Inactive Bus Tx & Rx
Status Word TXSD & RXSD
MC4 (or MC5) Disabled (Enabled).
transmitted, bits updated.
unconditional (only Tx is disabled, if
unless (only TXSD bit
fulfillment the BSDTXO config. bit
broadcast updated, if the
= 1)
BSDTXO config.
bit = 1)

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The AUTOBSD bit in RT Configuration Register 0x0017 is logic 0

In BIT Word
Register,
MC20 (or MC21) Status Word TXSD & RXSD
Disabled (Enabled).
if mode data value transmitted, bits updated.
(only Tx is disabled, if
matches “Bus unless (only TXSD bit
the BSDTXO config. bit
Select” value broadcast updated, if the
= 1)
BSDTXO config.
bit = 1)
MC20 (or MC21) Status Word In BIT Word

if mode data does Inactive Bus Tx & Rx transmitted, Register, TXSD
AUTOBSD NOT match “Bus status not changed unless & RXSD bits are
4 R/W 0
(continued) Select” value broadcast static
The AUTOBSD bit in RT Configuration Register 0x0017 is logic 1

status NOT changed
if mode data value transmitted, Register, TXSD
(Host can modify
matches “Bus unless & RXSD bits are
RTINH bits 13,12 in RT
Select” value broadcast static
Config. Reg. 0x0017)
if mode data does Inactive Bus Tx & Rx transmitted, Register, TXSD
NOT match “Bus status not changed unless & RXSD bits are
Select” value broadcast static
MC17 Sync Option Bits 1:0

If register bits 3-2 equal 11, the data word received with a valid “synchronize”
mode command (MC17) is unconditionally loaded into the “Remote Terminal
Time Tag Counter Register (0x0049)”. For non-broadcast MC17 commands,
the counter load occurs before status word transmission. If register bits 3-2
equal 00, the external host assumes responsibility for actions needed to perform
“synchronize” duties upon reception of the valid MC17 “synchronize” mode code
3−2 MC17OP1:0 R/W 0 command, but status transmission automatically occurs.
The binary 01 and 10 combinations of register bits 3-2 support certain
extended subaddress schemes. If bits 3-2 equal 01, the received data word
is automatically loaded into the “Remote Terminal Time Tag Counter Register
(0x0049)” if bit 0 of the received data word equals 0. If bits 3-2 equal 10, the
received data word is automatically loaded into the Time-Tag counter if bit 0
of the received data word equals 1. For non-broadcast MC17 commands, the
counter load occurs before status word transmission.
Host reset of “service request” status bit for mode code 16.
If this bit is logic 0, reception of a “transmit vector word” mode command (MC16)
1 MC16OPT R/W 0 causes automatic reset of the Service Request status bit. The Service Request
bit is reset in the Status Word Bits register before status word transmission
begins. If this bit is logic 1, the external host assumes responsibility for resetting
the Service Request bit in the Status Word Bits register.

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Automatic soft reset for mode code 8.

If this bit is logic 0, reception of a “reset remote terminal” mode command (MC8)
0 MC8OPT R/W 0 causes automatic assertion of SRESET software reset. If non-broadcast mode
command, reset occurs after status word transmission is complete. If this bit is
logic 1, the external host assumes responsibility for actions needed to perform
terminal reset.
15.2. Remote Terminal Operational Status Register (0x0018)
es d
es d
es d
N d
d
R rve
R rve
R rve
M rve
ve
R PF
M D
M D
TD
R K
er
LO P
RT 4
A3
RT 2
A1
RT 0
e
e
e
e
R
C
A
A
A
A
es
es
C
C
C
RT
RT
RT
RT
These bits latch pins 0 0 0 0 0 0 0 0 0 MR Reset

RW (see LOCK bit 9) R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
At rising edge on the MR Master Reset input pin, register bits 15-9 capture the logic states (0 or 1) of the corresponding
input pins having like names (if applicable). After reset, register bits 15-9 can be overwritten only if LOCK bit 9 is logic
0. If the register LOCK bit is logic 1, these bits are read-only.
Bits 8-0 are read-only; these bits are cleared after MR pin master reset, but are unaffected by assertion of RTRESET
remote terminal software reset in the “Master Status and Reset Register (0x0001)”.
Remote Terminal Address bits 4-0.

Remote Terminal Address Parity.
These bits reflect the state of the input pins RTA4 through RTA0 that
15 − 11 RTA4:0 applied at the rising edge of the MR master reset input signal (i.e. the
R/W 0
10 RTAP active remote terminal address). The RTAP bit, when appended to the
remote terminal address bits, provides odd parity. If the register LOCK
bit is high, bits 15-10 are read-only. If the register LOCK bit is low, the
host can overwrite these bits and change the terminal address and
parity.
Remote Terminal Address Lock.

After reset, the host can overwrite bits 15-9 only if register LOCK bit 9
9 LOCK R/W 0 is logic 0. When the LOCK bit is high, the host cannot overwrite register
bits 15-9. To restore host write capability for these bits, the MR master
reset input signal must first be asserted with the LOCK input pin held low
to restore register LOCK bit 9 to logic 0.
8−6 Reserved R 0 These bits are not used.

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No Data Mode Command Flag.

Receive Data Mode Command Flag.
Transmit Data Mode Command Flag.
These three bits reflect the type of command stored in the RT Current
Command Register:
5 MCND
4 MCRD R 0 Bits
Current Command Type Current Command Word
5-4-3
3 MCTD
Subaddress, not mode code 000 Subaddress, transmit or receive
Mode code, no data word 100 MC0 to MC15, T/R bit = 1
Mode code, received word 010 MC16 to MC31, T/R bit = 0
Mode code, transmit word 001 MC16 to MC31, T/R bit = 1
Mode code, undefined 111 MC0 to MC15, T/R bit = 0
Remote Terminal Address Parity Fail.
2 RTAPF R 0 This bit is set when RT address parity error occurs for the value
contained in register bits 15-10. It is low when correct odd parity applies
for bits 15-10.
1−0 Reserved R 0 These bits are not used.

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15.3. Remote Terminal Current Command Register (0x0002)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is read-only and is fully maintained by the device. This register is cleared after MR pin master reset,
but is unaffected by assertion of RTRESET remote terminal software reset in the “Master Status and Reset Register
(0x0001)”.
This register contains the last valid command word received by the Remote Terminal over either MIL-STD-1553 bus.
This register is updated 5µs after the ACTIVE output is asserted.
15.4. Remote Terminal Current Control Word Address Register (0x0003)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is read-only and is fully maintained by the device. This register is cleared after MR pin master reset,
(0x0001)”.
This register contains the address for the descriptor table Control Word corresponding to the current command stored
in the Current Command Register, above. This register is updated 5 µs after the ACTIVE output is asserted for
recognition of a valid command for the RT. Also see description for the “Current Message Information Word” register.
15.5. Remote Terminal Descriptor Table Base Address Register (0x0019)

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MR Reset
R RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and contains the starting address for the Remote Terminal’s Descriptor Table. This
register is initialized with default values after MR pin master reset, or by assertion of RTRESET remote terminal
software reset in the “Master Status and Reset Register (0x0001)”. The post-reset register value is 0x0400. After
initialization, this register is fully maintained by the host. Bit 15 and bits 8:0 cannot be set and will always read logic 0.

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15.6. Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A)

R erv R
L
es ed
es d
es ed
es d
es ed
R d
es Q
es C
R rve
M rve
R rve
BC rve
R RE
R ND
D F
R erv
R erv
TF A
SS Y
YS
e
e
ST
BC
C
S
A
BU
SV
TX
IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R RW R RW RW RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write. With the exception of bits 4 and 10, this register is maintained by the host. This reg-
ister is cleared after MR pin master reset, or by assertion of RTRESET remote terminal software reset in the “Master
Status and Reset Register (0x0001)”.
Register bits 14-10 and 7-4 are read-only. Most of these bits read back zero, except for bits 4 and 10, which are
maintained by the device. The remaining bits in the register are Read-Write and are maintained by the host. All bits are
active high. Register bits 10-0 are reflected in the outgoing MIL-STD-1553 RT status word. The RT status word reflects
the state of host-written register bits until overwritten by the host, unless the Transmit and Clear function (bit 15) is
enabled. When set, the Transmit and Clear bit resets itself and bits 9-5 and 3-0 after the next transmitted status word.
Transmit and Clear.

When this bit is set, it resets itself and bits 9-5 and 3-0 after the next
transmitted status word. This bit does not affect operation of the
Transmit Status Word and Transmit Last Command mode codes.
15 TXANDCLR R/W 0 Example: Transaction of a valid legal command with the INST and
TXANDCLR bits asserted results in status word transmission with the
Instrumentation bit set. If the following command is Transmit Status or
Transmit Last Command mode code, the Instrumentation bit remains
set.
14 − 11 Reserved R 0 These bits are not used, cannot be written, always read back 0000.
Message Error status bit.
10 ME R 0
The device maintains this read-only bit, based on prior message results.
Instrumentation status bit.
9 INST R/W 0
The host maintains this read-write bit.
Service Request status bit.

The host maintains this read-write bit. If the RT’s Configuration Register
8 SVCREQ R/W 0 MC16OPT bit equals 0, reception of a “transmit vector word” mode
command (MC16) causes automatic reset of the SVCREQ status bit in
this register; when this occurs, the register bit is reset before status word
transmission begins.
7−5 Reserved R 0 These bits are not used, cannot be written, always read back 000.
Broadcast Command Received status bit.

4 BCR R 0
The device maintains this read-only bit, based on prior message results.

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Busy status bit.

The host maintains this read-write bit. When set, the RT asserts its
Busy bit in status response for all valid commands. Instead of enabling
Busy for all commands, the host can assert Busy status for selected
commands by asserting the Busy bit in descriptor table Control Words
for the individual commands. When response to a command conveys
Busy status, the RT suppresses transmission of data words that would
3 BUSY R/W 0
normally accompany status for transmit commands. For messages
transacted with Busy status, the WASBSY flag is asserted in the stored
Message Information Word. If INTBUSY bit 2 is set in the “Extended
Configuration Register (0x004D)”, the WASBUSY bit 9 is also enabled in
the RT Interrupt Information Word.
Note: Busy status alone is not an interrupt event. See “Extended
Configuration Register (0x004D)” on page 44.
Subsystem Fail status bit.
2 SSYSF R/W 0 The host maintains this read-write bit. This register bit is logically ORed
with the RTSSF input pin. If either SSYSF register bit or RTSSF pin is
asserted, the SSYSF Subsystem Flag status bit is set.
Dynamic Bus Control Acceptance status bit.
1 DBCA R/W 0 The host maintains this read-write bit. If the terminal is to acknowledge a
Dynamic Bus Control, Mode Code 0 command, the host should set this
bit to a “1”.
Terminal Flag status bit.

0 TF R/W 0 The host maintains this read-write bit. When this bit is asserted, the
Terminal Flag status bit is set.
15.7. Remote Terminal Current Message Information Word Register (0x001B)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Only and is fully maintained by the device. This register is cleared after MR pin master reset,
(0x0001)”. This register contains the data buffer address (assigned in the terminal’s Descriptor Table) corresponding
to the last decoded valid command’ for the Remote Terminal.
The value in this register points to the command’s Message Information Word (or MIW) in the Descriptor Table. The
value of the current command word itself is stored in the Current Command Register.

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15.8. Remote Terminal Bus A Select Register (0x001C)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset,
(0x0001)”.
The Bus A Select register is only used when the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)”
equals 0. This AUTOBSD setting means the device automatically fulfills mode commands MC20 (decimal) “selected
transmitter shutdown” or MC21 “override selected transmitter shutdown”. “Transmitter shutdown” or “shutdown
override” can only occur for the inactive bus. If either mode command is received on Bus B, the inactive bus is Bus A.
The device compares the received mode data word to the contents of the Bus A Select register to determine whether
inactive Bus A is selected for “transmitter shutdown” or “transmitter shutdown override”. (Bus shutdown or shutdown
override can only occur for the inactive bus.) If the data word matches the value stored in the Bus A Select register
and AUTOBSD equals 0, the device automatically fulfills MC20 “transmitter shutdown” or MC21 “shutdown override”
without host assistance: If the mode command received was MC20 (bus shutdown), the Transmit Shutdown A bit in
the RT’s BIT (built-in test) Word Register is asserted. If mode command MC21 (override bus shutdown) was received,
the Transmit Shutdown A bit in the BIT Word Register is negated.
15.9. Remote Terminal Bus B Select Register (0x001D)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
(0x0001)”.
The Bus B Select register is only used when the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)”
equals 0. This AUTOBSD setting means the device automatically fulfills mode commands MC20 (decimal) “selected
transmitter shutdown” or MC21 “override selected transmitter shutdown”. “Transmitter shutdown” or “shutdown
override” can only occur for the inactive bus. If either mode command is received on Bus A, the inactive bus is Bus B.
The device compares the received mode data word to the contents of the Bus B Select register to determine whether
inactive Bus B is selected for “transmitter shutdown” or “transmitter shutdown override”. (Bus shutdown or shutdown
override can only occur for the inactive bus.) If the data word matches the value stored in the Bus B Select register
and AUTOBSD equals 0, the device automatically fulfills MC20 “transmitter shutdown” or MC21 “shutdown override”
without host assistance: If the mode command received was MC20 (bus shutdown), the Transmit Shutdown B bit in
the RT’s BIT (built-in test) Word Register is asserted. If mode command MC21 (override bus shutdown) was received,
the Transmit Shutdown B bit in the BIT Word Register is negated.

130
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15.10. Remote Terminal Built-In Test (BIT) Word Register (0x001E)
H
R SD
SD
TX SD
R D
N
RT F
BS
TF F
FA
FB
BI
T
XA
XB
User Assigned Bits
A
L
BM
EE
TX
LB
LB
P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Bits 11-4 in this 16-bit register is read-write; the remaining bits are read-only. The ten assigned bits are written by the
device when predetermined events occur. The host may overwrite the device-written bits 5 and 4. After MR pin master
reset, bits 13-12, 5-4 and 0 are reset. Bits 15-14 will be set if the corresponding TXINHA or TXINHB input pins are
high. Bits 3-1 will be set if RT address parity error, or post-MR memory test failure or auto-initialization failure occurred.
These registers are not affected by assertion of RTRESET remote terminal software reset in the “Master Status and
If the ALTBITW option bit in the “Remote Terminal Configuration Register (0x0017)” is zero when a valid “transmit BIT
word” mode command (MC19) is received, the current value in this register is transmitted as the mode data word in
the terminal response. The value is also copied to the Remote Terminal’s assigned data buffer for MC19, after mode
command fulfillment.
Transmit Bus A Shutdown.

Transmit Bus B Shutdown.
These read-only bits are set when the corresponding bus transmitter
15 TXASD was disabled by assertion of the bus TXINHA or TXINHB input pin,
R 0
14 TXBSD or by fulfillment of a “transmitter shutdown” mode command, either
MC4 or MC20. Refer to the description for the BSDTXO bit in the
“Master Configuration Register 1 (0x0000)” and the description for the
AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)”
for further information.
Receive Bus A Shutdown.
Receive Bus B Shutdown.
13 RXASD These read-only bits are set when the corresponding bus receiver was
R 0 disabled concurrently with a bus transmitter by a “transmitter shutdown”
12 RXBSD mode command MC4 or MC20. Refer to the description for the BSDTXO
bit in the “Master Configuration Register 1 (0x0000)” and the description
for the AUTOBSD bit in the “Remote Terminal Configuration Register
(0x0017)” for further information.
11 − 6 ---------- R/W 0 User assigned bits.
Bus A Loopback Fail.
5 LBFA Bus B Loopback Fail.

R/W 0
4 LBFB These bits are set if Bus A or Bus B loopback failure occurs during self-
test (see Section “21.2.1. Self-Test Control Register (0x0028)” on page
205).

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BIST Memory Test Fail.
3 BMTF R 0 This bit is set if error occurs during built-in self-test for device Random
Access Memory (RAM) (see Section “21.2.1. Self-Test Control Register
(0x0028)” on page 205).
RT Address Parity Fail.

This bit is asserted when “Remote Terminal Operational Status Register
(0x0018)” bits 15:10 reflect parity error. After MR master reset, bits 15:10
2 RTAPF R 0 in the RT’s Operational Status Register reflect input pin states, but will
be overwritten if subsequent auto-initialization is performed (if AUTOEN
pin is high) and the initialization EEPROM contains different data for RT
Operational Status Register bits 15:10.
Auto-Initialization EEPROM Load Fail.

This bit only applies when auto-initialization is enabled (AUTOEN input
1 EELF R 0 pin state equals 1). This bit is set if, after MR master reset, failure
occurs when copying serial EEPROM to registers and RAM. When this
occurs, bit 0 or bit 1 will be set in the “Master Status and Reset Register
(0x0001)” to indicate type of failure.
This bit is set when the Terminal Flag status bit is disabled while fulfilling
an “inhibit terminal flag bit” mode code command (MC6). This bit is reset
0 TFBINH R 0
if terminal flag status bit disablement is cancelled later by an “override
inhibit terminal flag bit” mode code command (MC7).
15.11. Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
It is not affected by assertion of RTRESET remote terminal software reset in the “Master Status and Reset Register
(0x0001)”. If the ALTBITW option bit in the “Remote Terminal Configuration Register (0x0017)” equals one when a
valid “transmit BIT word” mode command (MC19) is received, the current value in this register is transmitted as the
mode data word in the terminal response. The value is also copied to the assigned data buffer for MC19, after mode
command fulfillment.
15.12. Remote Terminal Time Tag Counter Register (0x0049)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This register is read-only and is cleared after MR pin Master Reset or assertion of RTRESET remote terminal software
reset in the “Master Status and Reset Register (0x0001)”. Reads to this register address return the current value of the
free running 16-bit Time Tag counter. Counter resolution is programmed by the TTCK2:0 bits in the “Time Tag Counter

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Configuration Register (0x0039)”. Options are: 2, 4, 8, 16, 32 and 64µs, or externally provided clock. The same clock
source is shared by the RT and BC.
The device automatically resets the Time-Tag Counter when a “synchronize” mode command without data (MC1) is
received. In addition, the host can reset, load or capture the Time Tag count at any time by asserting action bits in the
“Time Tag Counter Configuration Register (0x0039)”. Load and capture operations utilize the “Remote Terminal Time
Tag Utility Register (0x004A)”, described below.
The MC17OP1:0 bits in the “Remote Terminal Configuration Register (0x0017)” allows automatic loading of Time-Tag
count using the data word received with a “synchronize with data” mode command, MC17. If both of these bits equal
one, the data word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the
Time-Tag counter. For non-broadcast MC17 commands, the counter load occurs before status word transmission. If
both MC17OP1 and MC17OP0 bits equal 0, the external host assumes responsibility for actions needed to perform
“synchronize” duties upon reception of the valid MC17 “synchronize” command, but status transmission occurs
automatically.
The binary 01 and 10 combinations of these bits support certain extended subaddressing schemes. If the MC17OP1:0
bits equal 01, the received data word is automatically loaded into the Time-Tag counter if the low order bit of the
received data word (bit 0) equals 0. If the MC17OP1:0 bits equal 10, the received data word is automatically loaded
into the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. For non-broadcast MC17
commands, the counter is loaded before status word transmission.
15.13. Remote Terminal Time Tag Utility Register (0x004A)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
but is not affected by assertion of RTRESET remote terminal software reset in the “Master Status and Reset Register
(0x0001)”. This register has two functions associated with the two free-running Remote Terminal Time Tag Counters:
15.13.1. RT Time Tag Counter Loading

When the RTTTA1-0 bits 9-8 in “Time Tag Counter Configuration Register (0x0039)” are written to 1-0, the value
contained in the “Remote Terminal Time Tag Utility Register (0x004A)” is loaded into the “Remote Terminal Time Tag
Counter Register (0x0049)”.
15.13.2. RT Time Tag Count Match Interrupts

If the RTTTM interrupt is enabled in the “Hardware Interrupt Enable Register (0x000F)”, then time tag “count match”
interrupts are enabled. When enabled, the hardware RTTTM interrupt occurs when the free running “Remote Terminal
Time Tag Counter Register (0x0049)” matches the value contained in the “Remote Terminal Time Tag Utility Register
(0x004A)”.

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15.14. Remote Terminal Interrupt Registers and Their Use

Interrupt Log Buffer and the Interrupt Count & Log Address Register to manage interrupts. Three additional registers
are dedicated to the RT interrupts. Comparable to the Hardware Interrupt register triplet, the RT has
• A “Remote Terminal (RT) Interrupt Enable Register (0x0012)” to enable and disable interrupts
• A “Remote Terminal (RT) Pending Interrupt Register (0x0009)” to capture the occurrence of enabled interrupts
• A “Remote Terminal (RT) Interrupt Output Enable Register (0x0016)” to enable IRQ output to host, for pending
enabled interrupts
Each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt
condition is enabled. Numerous interrupt options are available. At initialization, bits are set in the “Remote Terminal
(RT) Interrupt Enable Register (0x0012)” to identify the interrupt-causing events which are heeded by the device.
Most RT applications only use a subset of available interrupt options. Interrupt-causing events are ignored when their
corresponding bits are reset in the “Remote Terminal (RT) Interrupt Enable Register (0x0012)”. Setting an Interrupt
Enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
Whenever a RT interrupt event occurs (and the corresponding bit is already set in the “Remote Terminal (RT) Interrupt
Enable Register (0x0012)”), these actions occur:
• A bit corresponding to the interrupt type is set in the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”.
The type bit is logically-ORed with the preexisting register value, retaining bits for prior, unserviced RT interrupts.
• RT Interrupt Pending (RTIP) bit 1 is set in the “Hardware Pending Interrupt Register (0x0006)”. The RTIP bit
is logically-ORed with the preexisting register value, retaining bits for unserviced hardware interrupts and the
preexisting status of the BCIP and MTIP (Bus Controller and MT) interrupt pending bits.
• If the matching bit is already set in the “Remote Terminal (RT) Interrupt Output Enable Register (0x0016)”, an
IRQ output occurs.
If the matching bit in the “Remote Terminal (RT) Interrupt Output Enable Register (0x0016)” was not already set (i.e.,
low priority polled interrupt), the host can poll the “Remote Terminal (RT) Pending Interrupt Register (0x0009)” to
detect the occurrence of interrupts, indicated by non-zero value. Reading the “Remote Terminal (RT) Pending Interrupt
Register (0x0009)” automatically clears it to 0x0000.
Output Enable registers (hardware, BC, RT and SMT). Multiple interrupt-causing events can occur simultaneously, so
“Hardware Pending Interrupt Register (0x0006)” to indicate when BC, RT and SMT interrupts occur. When RT Interrupt
Pending (RTIP) bit 1 is set in the “Hardware Pending Interrupt Register (0x0006)”, the “Remote Terminal (RT) Pending
Interrupt Register (0x0009)” contains a nonzero value and may be read next to identify the specific RT interrupt
Buffer. Section 9.5 has a detailed description.

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15.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012)
es d
es d
es d
es d
es d
es d
es d
TM d
es d
d
R rve
R rve
R rve
R rve
R rve
R ve
R rve
R rve
R rve
ve
IX C8
IB D
IL Z
IW R
er
er
EQ
M
e
e
e
e
e
e
ER
A
es
es
R
C
M
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
15.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009)

es d
es d
es d
es d
es d
es d
es d
TM d
es d
d
R rve
R rve
R rve
R rve
R rve
R ve
R rve
R rve
R rve
ve
IX C8
IB D
IL Z
IW R
er
er
EQ
M
e
e
e
e
e
e
ER
A
es
es
R
C
M
R
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
15.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016)

es d
es d
es d
es d
es d
es d
es d
TM d
es d
d
R rve
R rve
R rve
R rve
R rve
R ve
R rve
R rve
R rve
ve
IX C8
IB D
IL Z
IW R
er
er
EQ
M
e
e
e
e
e
e
ER
A
es
es
R
C
M
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Three registers govern RT interrupt behavior: the RT Interrupt Enable Register, the RT Pending Interrupt Register and
the RT Interrupt Output Enable Register. When a bit is set in the RT Interrupt Enable Register, the corresponding RT
interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded.
Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero.
When an enabled RT interrupt event occurs, the corresponding bit is set in the RT Pending Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, RTIP bit 2 in the “Hardware Pending Interrupt Register
(0x0006)” is also set whenever a message sets at least one bit in the RT Pending Interrupt Register.
If the corresponding bit is set in the RT Interrupt Output Enable Register, the IRQ output is asserted at message
completion. The RT Interrupt Output Enable Register establishes two priority levels: high priority interrupts generate
an IRQ output while low priority interrupts do not. Both priority levels update the Pending Interrupt Register and
Interrupt Log Buffer. The host can detect low priority (masked) interrupts by polling Pending Interrupt registers. When
the IRQOFF bit 0 is set in “Extended Configuration Register (0x004D)” on page 44, IRQ pin assertion for enabled
RT interrupt-causing events is suppressed when the command is illegal (Message Error response) or results in RT
busy status.
When one or more bits are set in the RT Interrupt Enable Register, occurrence of an enabled RT interrupt-causing
event triggers an “Interrupt Log Buffer” update. The Interrupt Identification Word (written to the “Interrupt Log Buffer”
on page 37 for RT events) mirrors the RT Pending Interrupt register. NOTE: While bit 9 is reserved (always 0) in
the RT Pending Interrupt register, bit 9 in the written log buffer Interrupt Identification Word (IIW) has a defined function
(when INTBUSY bit 2 in “Extended Configuration Register (0x004D)” on page 44 is set, RT IIW bit 9 serves as
WASBUSY status flag, asserted if the RT was Busy when the RT interrupt event occurred. RT Busy status is not an
interrupt-causing event.).

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The following table describes the shared bit descriptions used by all three RT interrupt registers:
15 − 10 Reserved These bits are not used.
9 Reserved Bit 9 cannot be written and reads back logic 0.
RT Mode Code 8 Command Interrupt.

Remote terminal processed a valid MIL-STD-1553 “reset remote terminal” mode code
command. An RTMC8 interrupt notifies the host when the Bus Controller commands
remote terminal reset.
If the RTMC8 bit is reset in the “Remote Terminal (RT) Interrupt Enable Register
8 RTMC8 (0x0012)” when the RT decodes a valid “reset remote terminal” mode command, bit 0
in the “Remote Terminal Configuration Register (0x0017)” dictates whether the reset
response is automatic, or host controlled. The event does not affect the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)”, the Interrupt Log or the IRQ output,
but the RTMC8 output pin is asserted to indicate that the RT needs reset. In the case of
a broadcast command to RT31, RTMC8 output pin will also be asserted.
RT Index Equals Zero Interrupt.

Index counts are used in multi-message bulk data transfers. “Index equals zero” occurs
when the last expected message was transacted.
7 IXEQZ
Defined IXEQZ interrupt events comprise: (a) subaddresses using indexed buffer mode
when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes
when the pre-determined number of messages has been transacted.
RT Illegal Command Interrupt.

The Remote Terminal encountered a valid illegal message, as defined in the RT Illegal
Command Table.
Illegal commands are detected when a new valid command word is decoded and the
RT Illegalization Table bit corresponding to the received command is logic 1. (Table bits
are logic 0 for legal commands.) The RT Illegalization Table contains nonzero values
6 ILCMD only when “illegal command detection” is being applied. When illegal commands are
received, the RT responds by transmitting a status word with ME “message error” flag
set; no data words are transmitted.
If the ILCMD bit is reset in the “Remote Terminal (RT) Interrupt Enable Register
(0x0012)” when a valid illegal command is decoded, the event does not affect the
“Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the Interrupt Log or the
IRQ output.
RT Broadcast Command Received Interrupt.

5 IBR Broadcast commands are enabled for the RT and the terminal encountered a valid
command addressed to RT31, the broadcast command address.
RT Message Error Status Interrupt.
4 MERR The Remote Terminal set its Message Error status flag while processing a valid MIL-
STD-1553 message. Message errors are caused by Manchester encoding problems or
protocol errors.

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RT Interrupt When Accessed.
3 IWA The Remote Terminal processed a valid MIL-STD-1553 command having the IWA
interrupt enabled in its RT Descriptor Table entry. IWA interrupts are used to notify the
host each time certain command words are encountered.

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16. REMOTE TERMINAL CONFIGURATION AND OPERATION
16.1. Command Responses

A brief review of MIL-STD-1553 commands and responses is appropriate here to establish terminology used in the
rest of this data sheet. Shown in Figure 9, each command word is comprised of a sync field, three 5-bit data fields, a
single bit denoting Transmit / Receive direction and ends with a parity bit. The hardware decoder uses the sync field
to determine word type (command vs. data). Word validity is based on proper sync encoding, Manchester II encoding,
correct bit count and correct odd parity for the 16 data bits. Once a valid word with command sync is found, the sync
and parity are stripped before the command’s 16 data bits are stored for further processing.
Command T/R Word Count

Sync Bit Field *
Terminal Subaddress Parity

Address (SA) Field Bit
Field
* Word Count field is replaced by Mode Code
field when the SA field equals 0x00 or 0x1F
Figure 9. MIL-STD-1553 Command Word Structure

A “valid command” can be specifically addressed to the individual terminal (the command word’s embedded Terminal
Address field matches the terminal address latched in the Operational Status register) or can be a “broadcast command”
addressed to all terminals. Broadcast commands are always addressed to RT address 31 (0x1F). In systems where
broadcast commands are disallowed, RT31 is not used as a conventional terminal address. When set, the BCSTINV bit
in the “Remote Terminal Configuration Register (0x0017)” renders RT31 commands as “invalid”: broadcast commands
are indistinguishable from commands addressed to other terminals. Invalid commands are simply disregarded.
When the command word’s 5-bit SA (subaddress) field is in the range of 1 to 30 (0x01 to 0x1E) the command is con-
sidered a “subaddress command”. The terminal will either receive or transmit data words, and “direction” is specified
by the command’s T/R bit. The number of data words transacted is specified in the 5-bit word count field, ranging from
1 to 32 words. Thirty-two data words is represented when the word count field equals 0x00.
When the command’s 5-bit subaddress field equals 0 or 31 (0x1F) a “mode code” command is indicated; the low order
five bits no longer specify a word count, instead they convey a mode code value. This data sheet refers to mode code
commands by the mode code number. For example, a mode command with 5-bit mode code field of 0x10 is called
MC16, and the full range of mode code values is MC0 through MC31 (decimal).
Mode codes MC16 through MC31 (0x10 through 0x1F) have a single associated data word. When the command T/R
bit equals 0, the data word is contiguous with the command word and received by the RT. When the command’s T/R
bit equals 1, the data word is transmitted by the RT, following the terminal’s transmitted status word.
Mode codes MC0 through MC15 (0x0F) do not have associated data words. For these 16 commands, the command
T/R bit does not specify “direction”. These commands must be transmitted with T/R bit equal to 1. If the T/R bit is 0,
the mode command is “undefined”.
Twenty-two mode commands are “undefined mode commands ” in MIL-STD-1553B:
Mode Codes 0 through 15 with T/R bit = 0

Mode Codes16, 18 and19 with T/R bit = 0
Mode Codes 17, 20 and 21 with T/R bit = 1
The UMCINV bit in the “Remote Terminal Configuration Register (0x0017)” determines how these undefined mode

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commands are handled by the device. If the UMCINV configuration bit equals 1, the undefined mode commands are
treated as invalid. They are not recognized by the device. There is no terminal response and status is not updated.
If the UMCINV configuration bit equals 0, the 22 undefined mode commands are considered valid; this is the default
condition following reset. For this case, terminal response depends on whether or not the application uses “illegal
command detection.”
If illegal command detection is not used, all Illegalization Table entries should be logic 0, including the 22 entries for
these undefined commands. (The Illegalization Table is fully described in Section 16.2 on page 140. After MR reset,
all entries equal logic 0.) The terminal responds “in form”, transmitting clear status (and a single mode data word if the
command is MC17, MC20 or MC21 with T/R bit = 1). Terminal status is updated.
If illegal command detection applies, the Illegalization Table entries for these 22 undefined commands should be
initialized to logic 1. In this case, the terminal will respond with status word only, with Message Error bit set. No mode
data word is transmitted. Terminal status is updated.
Twenty-seven mode codes are considered “reserved” in MIL-STD-1553B:

Treatment of these reserved mode commands depends on their respective Illegalization Table entries. As described
above for undefined mode commands, response depends on whether or not illegal command detection applies.
Any mode commands not implemented in the terminal should be treated the same as reserved mode commands.
The important point is that “illegal command detection” should be universally applied (or not applied) when setting up
a Remote Terminal application. Here are the two options:
Not using Illegal command detection. The Illegalization Table is left in its default state (all locations equal to MR
post-reset 0x0000). The terminal responds “in form” to all valid commands, whether legal or illegal.
Using illegal command detection. The Illegalization Table is initialized by the host to implement “illegal command
detection”. The host sets bits for all illegal commands. This generally includes the reserved and unimplemented mode
commands, unimplemented subaddresses (or specific word counts, T/R bit states, and/or broadcast vs. non-broadcast
status within subaddresses). Treatment for the undefined mode commands depends on UMCINV bit.
The host defines terminal response for all individual commands by initializing the Descriptor Table, fully described later.
At this point, a few comments about the Descriptor Table are appropriate.
The command SA (subaddress) field has a range of 0 to 31 (0x1F). When SA is in the range 1 to 30 (0x1E), the com-
mand is a transmit or receive “subaddress command”. The number of data words transmitted or received is expressed
in the low order 5 bits. When SA equals 0 or 31 (0x1F) the command is a mode command and the mode code value
is expressed in the low order 5 bits.
For each subaddress, separate table “descriptor blocks” for transmit and receive commands permit different data buff-
ering to be applied. The host initializes the table so each transmit-subaddress and each receive-subaddress uses one
of four methods for storing message data. During table initialization, memory is allocated in shared RAM for storing
message data according to the application requirements. Each transmit-subaddress and receive-subaddress has one
or more data pointers (depending on buffer method) addressing its reserved data buffer(s).
Each mode command also has its own table “descriptor block”. Mode commands have either one data word or no as-
sociated data words. Descriptor words used as data pointers by “subaddress commands” are instead used for direct
storage of transacted mode data words. Mode commands that transmit or receive mode data words have a dedicated
storage address range in shared RAM, eliminating the need for descriptor table data pointers.
Each mode command with mode data word has its own fixed address for data storage. This includes reserved mode
codes with data word. Thus the device can respond consistently for all mode commands; transmitted data values for

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“in form” responses (when “illegal command detection” is not used) can be predetermined, even for the reserved mode
commands.
16.1.1. RT to RT Commands.
The MIL-STD-1553 standard allows for data word transmission from a specified transmitting terminal to a different
receiving terminal. When broadcast commands are allowed, data transmission can be addressed to the broadcast
terminal address, RT31. If broadcast is allowed, the host should initialize the BCSTINV (broadcast invalid) bit in the
“Remote Terminal Configuration Register (0x0017)”.
All RT to RT commands are characterized by a pair of contiguous command words: Command Word 1 is a receive
command addressed to the intended receiving terminal, then Command Word 2 is a transmit command addressed to
a single transmitting terminal. Command Word 2 cannot be broadcast address RT31. The device automatically detects
and handles RT to RT commands, except when either command word contains a subaddress field equal to 0x0 or
0x1F. Either subaddress value indicates a mode code command; the device treats RT to RT commands with mode
code as invalid. If either RT-RT command word is addressed to the terminal but contains subaddress 0x0 or 0x1F, the
command is not recognized; there is no RT command response, and no status updating for the benefit of following
“transmit status” or “transmit last command” mode commands.
When either RT-RT command word (with subaddress field not equal to 0x0 or 0x1F) is addressed to the terminal, but
the other command word contains subaddress 0x0 or 0x1F, the RT-RT command is not recognized as valid. There
is no RT command response, and no status updating for the benefit of following “transmit status” or “transmit last
command” mode commands.
An RT-RT command pair where Command Word 1 is addressed to the terminal and Command Word 2 is addressed
to a different terminal is considered an “RT-RT receive” command. When the message is transacted, the device sets
the RTRT bit in the Receive Subaddress Message Information Word in the subaddress data buffer.
An RT-RT command pair where Command Word 2 is solely addressed to the terminal (not RT31) is considered an
“RT-RT transmit” command. The Message Information Word does not distinguish the RT to RT transmit message from
an ordinary RT to BC transmit command.
16.2. Command Illegalization Table

The following pages describe various structures residing in the RAM shared between the host and command processing
logic. The host initializes these structures to control the terminal’s response to received commands. The first structure
described is the command Illegalization Table used for “illegal command detection”.
Illegal command detection is an optional process. When illegal command detection is not used, the terminal “responds
in form” to all valid commands: it sends Clear Status and transacts the number of data words defined in the received
command. When illegal command detection is not used, the bus controller cannot tell whether the command is legal
or illegal, from the terminal’s transmitted response.
If illegal command detection is used, the terminal responds differently when an illegal command is detected. The termi-
nal responds to illegal commands with “message error” status, transmitting only status word. Data word transmission
is suppressed if the command type inherently includes transmitted data words. The terminal responds to each legal
command with clear status and transacts the number of data words defined in the type of command received.
For consistency, apply illegal command detection to all illegal and unimplemented commands, and to all reserved or
undefined mode code commands, or “respond in form” to all of these commands (illegal command detection disabled)
by leaving the Illegalization Table in the all-cleared default state after MR master reset
The device uses a 256-word “Illegalization Table” in shared RAM to distinguish between legal and illegal commands.
After the (MR) master reset input is negated, the device performs internal self test including a shared RAM test which
leaves all memory locations fully reset. Once self test is complete, the READY output goes high to indicate readiness
for host initialization. At this point, all entries in the Illegalization Table read logic 0, so by default, illegal command

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detection is not applied.
To apply illegal command detection, the host (or auto-initialization) writes the Illegalization Table to set bits for all illegal
command combinations. This typically includes any unimplemented subaddresses and/or word counts, undefined
mode commands, reserved mode commands and any mode commands not implemented in the terminal design. Host
initialization of the table can be replaced by auto-initialization.
Once RTSTEX is set in the “Master Configuration Register 1 (0x0000)”, terminal execution begins. Each time a valid
command is received, a 1-bit entry (indexed using command word data bits) is fetched from the Illegalization Table:
If fetched Illegalization Table bit equals logic 0, the command is “legal”; the terminal responds “in form”, transmit-
ting clear status and transacting the number of data words defined for the message type. Terminal status is updated.
If fetched Illegalization Table bit equals logic 1, the command is “illegal”; the terminal responds with status word
only, with Message Error bit set. No data words are transmitted. Terminal status is updated.
When illegal command detection is not applied, all table entries should read logic 0; the terminal responds “in form” to
all valid commands.
The illegalization scheme allows any subset of command T/R bit, broadcast vs. non-broadcast status, subaddress
and word count (or mode code number), for a total of 4,096 legal/illegal command combinations. Commands may be
illegalized down to the word count level. For example, 10-word receive commands to a given subaddress may be legal,
while 9-word receive commands to the same subaddress are illegal.
Broadcast receive commands are illegalized separately from non-broadcast receive commands. Transmit and receive
commands for the same subaddress are illegalized separately. For mode commands, any combination of mode code
number, T/R bit and broadcast/non-broadcast status can be legal or illegal.
The Illegalization Table is located in shared RAM within the fixed address range of 0x0200 to 0x02FF. See Figure 10.
The table is comprised of 256 16-bit words. To cover the full range of 1 to 32 data words, each subaddress uses a
pair of illegalization registers. The lower register (even memory address) covers word counts 0 to 15, using one bit
per word count. As in command encoding, “0” denotes 32 data words. Bit 0 corresponds to 32 data words, bit 1 cor-
responds to 1 data word and bit 15 corresponds to 15 data words. The upper register (odd memory address) similarly
covers word counts 16 to 31, using one bit per word count. Bit 0 corresponds to 16 data words, while bit 15 corre-
sponds to 31 data words.
When a command’s subaddress field equals 0 or 31 (0x1F), the command is a mode command. Table entries for mode
commands use bits to represent mode code numbers, not word counts. The lower register (even memory address)
covers mode codes 0 to 15, using one bit per mode code. Bit 0 corresponds to mode code 0, bit 15 corresponds to
mode code 15. The upper register (odd memory address) similarly covers mode codes 16 to 31, using one bit per
mode code. Bit 0 corresponds to mode code 16, bit 15 corresponds to mode code 31. There is no functional difference
between SA0 mode commands and SA31 mode commands. Since either subaddress indicates a mode command, the
subaddress 0 table words should match the subaddress 31 table words in each quadrant.
Table entries from 0x0242 to 0x027D do not have to be programmed. These correspond to broadcast transmit
subaddress commands (undefined by MIL-STD-1553B) and are always invalid. There is no terminal response.
Addressing for the Illegalization Table is derived from the command word T/R bit, subaddress field, MSB of the Word
Count (Mode Code) field and the command’s broadcast vs. non-broadcast status as shown below in Figure 10.

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Bit Fields Comprise Each Received Command Word

Terminal Word Count
Command Address T/R Subaddress (Mode Code)
Sync TA4:0 Bit SA4:0 WC4:0
P
“0” if
TA4:0 = 11111
else “1”
Table
0 0 0 0 0 0 1 0 Address
SA1
SA2
SA4
WC4
SA0
SA3
T/R
Figure 10. Deriving the Illegalization Table Address From the Received Command Word
Figure 12 on page 144 shows individual bit locations in the Illegalization Table for broadcast and non-broadcast vari-
ants of all mode commands defined by MIL-STD-1553B. Locations are also identified for reserved mode codes and
undefined mode code commands.
The following examples illustrate how the Illegalization Table is initialized to distinguish between legal and illegal com-
mands when “illegal command detection” is being used. Remember: If the terminal does not use illegal command
detection, the table is left in its post-MR reset state, with all table locations reset to 0x0000. In this case, all command
responses are “in form”.
For “subaddress commands” (ordinary receive commands or transmit commands) individual table bits correspond
to word counts specified in the received command word. If a bit is 0, the corresponding word count is legal. If a bit is
1, the corresponding word count is illegal.
For example, transmit commands to RT subaddress 1 are controlled by the words at 0x02C2 and 0x02C3. In Figure
11, these words are located in the “RT Address Transmit” block. The word stored at 0x02C3 controls subaddress 1
transmit commands having word counts 16 to 31. The word stored at 0x02C2 controls subaddress 1 transmit com-
mands having word counts 1 to 15 or 32. (Reminder: In MIL-STD-1553B, zero corresponds to 32 words.)
Word at 0x02C3 (Tx Subaddr 1) 31 to 16 words
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Word at 0x02C2 (Tx Subaddr 1) 15 to 1 & 32 words

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32
If the word stored at 0x02C3 = 0xFFFF and the word stored at 0x02C2 = 0xFF0F, then commands with 4, 5, 6, or 7
data words are the only legal transmit commands for subaddress 1 and all other word counts are illegal. Receive com-
mands and broadcast receive commands for Subaddresses1 through 30 are encoded similarly.
For “mode code commands” (characterized by command word subaddress field equal to 00000 or 11111 binary)
individual table bits correspond to individual mode code values. Here “transmit” and “receive” simply indicate the state
of the command word T/R bit. (For mode codes 0-15, the T/R bit does not indicate data direction since data is not
transacted when fulfilling these commands).

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0x02FF Tx Subaddress 31 Block (mode codes) RT Address Tx Mode Codes 31 - 16 0x02FF
Tx Subaddress 30 Block RT Address Tx Mode Codes 15 - 0 0x02FE
RT Addr Tx SA30 Word Counts 31 - 16 0x02FD

RT Address Transmit Quadrant
32 subaddress blocks RT Addr Tx SA30 Word Counts 15 - 0 * 0x02FC
of 2 words each * Word Count = 0
denotes 32 words
Tx Subaddress 1 Block RT Address Tx Mode Codes 31 - 16 0x02C1
0x02C0 Tx Subaddress 0 Block (mode codes) RT Address Tx Mode Codes 15 - 0 0x02C0
0x02BF Rx Subaddress 31 Block (mode codes) RT Address Rx Mode Codes 31 - 16 0x02BF
Rx Subaddress 30 Block RT Address Rx Mode Codes 15 - 0 0x02BE
RT Addr Rx SA30 Word Counts 31 - 16 0x02BD

RT Address Receive Quadrant
32 subaddress blocks RT Addr Rx SA30 Word Counts 15 - 0 * 0x02BC
denotes 32 words
Rx Subaddress 1 Block RT Address Rx Mode Codes 31 - 16 0x0281
0x0280 Rx Subaddress 0 Block (mode codes) RT Address Rx Mode Codes 15 - 0 0x0280
0x027F Command
Tx Subaddress 31 Block (mode codes) Broadcast Tx Mode Codes 31 - 16 0x027F
Sync
Tx Subaddress 30 Block Broadcast Tx Mode Codes 15 - 0 0x027E
Broadcast Transmit Quadrant Broadcast Tx SA30 Word Counts 31 - 16 0x027D

32 subaddress blocks
Broadcast Tx SA30 Word Counts 15 - 0 * 0x027C
of 2 words each
SA1 to SA30 are illegal * Word Count = 0
broadcast transmit! denotes 32 words
Tx Subaddress 1 Block Broadcast Tx Mode Codes 31 - 16 0x0241
Tx Subaddress 0 Block (mode codes) Broadcast Tx Mode Codes 15 - 0 0x0240

0x0240
0x023F
Rx Subaddress 31 Block (mode codes) Broadcast Rx Mode Codes 31 - 16 0x023F
Rx Subaddress 30 Block Broadcast Rx Mode Codes 15 - 0 0x023E
Broadcast Rx SA30 Word Counts 31 - 16 0x023D

Broadcast Receive Quadrant
32 subaddress blocks Broadcast Rx SA30 Word Counts 15 - 0 * 0x023C
denotes 32 words
Rx Subaddress 1 Block Broadcast Rx Mode Codes 31 - 16 0x0201
0x0200 Rx Subaddress 0 Block (mode codes) Broadcast Rx Mode Codes 15 - 0 0x0200
Illegalization Table Comprised of Example Subaddress Blocks

32 2-word Blocks per Quadrant from Each Table Quadrant
Figure 11. Address Mapping for Illegalization Table

Note: Default start address is 0x0200.

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Figure 12 summarizes the 16 Illegalization Table locations for mode commands. These locations are scattered
throughout the overall Illegalization Table shown in Figure 13. Remember: the host must initialize all table locations
corresponding to both subaddress 0 and subaddress 31 (11111 binary).
Consider an example in which all reserved and all undefined mode commands are illegal. If all RT defined transmit
mode commands are legal except MC0 (”dynamic bus control”) the eight table entries for transmit mode commands
would be:
0x02FF and 0x02C1 = 1111 1111 1111 0010 = 0xFFF2 Tx MC with data
0x02FE and 0x02C0 = 1111 1110 0000 0001 = 0xFE01 Tx MC without data
0x027F and 0x0241 = 1111 1111 1111 1111 = 0xFFFF Br.Tx MC with data (all illegal)
0x027E and 0x0240 = 1111 1110 0000 0101 = 0xFE05 Br.Tx MC without data
The receive mode command words are encoded similarly. Continuing the same example where all reserved and all
undefined mode commands are illegal: If all RT defined receive mode commands are legal, the eight table entries for
receive mode commands would be:
0x02BF and 0x0281 = 1111 1111 1100 1101 = 0xFFCD Rx MC with data
0x02BE and 0x0280 = 1111 1111 1111 1111 = 0xFFFF Rx MC without data (all illegal)
0x023F and 0x0201 = 1111 1111 1100 1101 = 0xFFCD Br.Rx MC with data
0x023E and 0x0200 = 1111 1111 1111 1111 = 0xFFFF Br.Rx MC without data (all illegal)
Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x02FF Transmit MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
and Tx MC31 - MC16 Mode Commands
0x02C1 With Data Status R R R R R R R R R R U U D D U D
0x02FE Transmit MC # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
and Tx MC15 - MC0 Mode Commands
0x02C0 Without Data Status R R R R R R R D D D D D D D D D
0x02BF Receive MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
and Rx MC31 - MC16 Mode Commands
0x0281 With Data Status R R R R R R R R R R D D U U D U
0x02BE Receive MC # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
and Rx MC15 - MC0 Mode Commands
0x0280 Without Data Status U U U U U U U U U U U U U U U U
0x027F Broadcast Transmit
and Br.Tx MC31 - MC16 Mode Commands MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x0241 With Data Status NB NB NB NB NB NB NB NB NB NB U U NB NB U NB
0x027E Broadcast Transmit
and Br.Tx MC15 - MC0 Mode Commands MC # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0240 Without Data Status R R R R R R R D D D D D D NB D NB
0x023F Broadcast Receive
and Br.Rx MC31 - MC16 Mode Commands MC # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x0201 With Data Status R R R R R R R R R R D D U U D U
0x023E Broadcast Receive
and Br.Rx MC15 - MC0 Mode Commands MC # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0200 Without Data Status U U U U U U U U U U U U U U U U
RAM
Address
LEGEND
D = Defined Mode Command R = Reserved Mode Code
U = Undefined Mode Command NB = Broadcast Not Allowed
Figure 12. Summary of RT Illegalization Table Addresses for Mode Code Commands

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16.3. Temporary Receive Data Buffer

The 32-word temporary receive data buffer resides in shared RAM in address space 0x01C0 to 0x01DF. The device
optionally uses this buffer for temporary storage of receive data words until successful message completion. To enable
the buffer, the host asserts the TRXDC bit in the “Remote Terminal Configuration Register (0x0017)”.
When enabled, the terminal stores received data words in the 32-word buffer during message processing. Upon error-
free message completion, all buffered words are written in a burst to the data buffer memory assigned to the specific
subaddress in the RT Descriptor Table.
When the TRXDB bit in the “Remote Terminal Configuration Register (0x0017)” is negated, the temporary receive
data buffer is disabled. At 20us intervals, the terminal writes received data words to assigned subaddress data buffer
memory as each word is received. If message error occurs during data reception, data integrity is lost; valid data from
the prior receive message may be partially overwritten by data from a message ending in error. MIL-STD-1553 states
that all received data from messages ending in error should be disregarded.
In a typical application, the temporary buffer is not directly accessed by the host, although there is no restriction pre-
venting host data access. The host should never write data into the temporary buffer space.
16.4. Descriptor Table

The Descriptor Table, resides in shared RAM, at default address ranges 0x0400 to 0x05FF. This table is initialized
by the host (or auto-initialization) to define how the terminal processes valid commands. Descriptor Table settings for
each command specify where message data is stored, how data is stored, whether host interrupts are generated, and
other aspects essential to command processing. Before initializing the RAM Descriptor Table, the RTENA bit must
be set in the “Master Configuration Register 1 (0x0000)”. Terminal execution does not begin until the RTSTEX bit
is set in “Master Configuration Register 1 (0x0000)”.
Shown in Figure 13, the table consists of 128 consecutive “descriptor blocks”, each comprised of four 16-bit words.
The table is organized into four quadrants.
The Receive Subaddress and Transmit Subaddress quadrants define response for commands having a subaddress
field ranging from 1 to 30 (0x1E). These are simple N-data word receive or transmit commands, where N can range
from 1 to 32 words. When the command T/R bit equals 0, the receive command quadrant applies. When the T/R bit
equals 1, the transmit command quadrant applies.
Both subaddress quadrants are padded at top and bottom with unused Descriptor Blocks for subaddresses 0 and 31
(0x1F). The word space reserved for SA0 and SA31 aligns the table addressing, but values stored in these eight loca-
tions is not used. Command subaddresses 0 and 31 indicate mode commands. The response for commands contain-
ing either SA value is defined in the two mode command table quadrants. The Receive Mode Command quadrant
applies when the command word T/R bit equals 0, while the Transmit Mode Command quadrants applies when T/R
equals 1.
The term “Transmit Mode Command” is misleading. All defined mode commands with mode code less than 0x0F
haveT/R bit equal to 1, yet none of these mode commands transmits a data word. They transmit only the terminal sta-
tus word, just like receive commands. However, the RT responds to transmit mode commands with mode code 0x10
to 0x1F by transmitting a mode data word. Just three such transmit mode commands are defined.
Within the Receive and Transmit Mode Command quadrants, block addressing is based on the low order 5 bits in the
command word, containing the mode code value. This is fundamentally different from the Subaddress quadrants in
which block addressing is based on the 5-bit subaddress field. Figure 14 shows how to derive Control Word address
from the received Command Word. The Control Word address for the last valid command can also be found in the
“Remote Terminal Current Control Word Address Register (0x0003)”.
All 128 4-word Descriptor Blocks start with a Control Word. There are four Control Word variants based on command
type: receive vs. transmit and mode vs. non-mode commands. All descriptor Control Words are initialized by the host
(or auto-initialization) to define basic command response. Each Control Word specifies the data buffer method and

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host interrupt for a specific subaddress or mode command.
Each subaddress has both a Receive Subaddress block and a Transmit Subaddress block. Receive and transmit
commands to the same subaddress can be programmed to respond differently.
The function of the three remaining descriptor words (in each 4-word block) depends on which of the 4 data buffer
methods are specified in the Control Word.
Indexed (or Single Buffer) Method where a predetermined number of messages is transacted using a single data
buffer in shared RAM. Several host interrupt options are offered, including an interrupt generated when all N messages
are successfully completed.
Double (or Ping-Pong) Buffer Method where successive messages alternate between two data buffers in shared
RAM. Several host interrupt options are offered.
Circular Buffer Mode 1 where buffer boundaries determine when the bulk transfer is complete and message informa-
tion and time-tag words are stored with message data in a common buffer. Several host interrupt options are offered,
including an interrupt generated when the allocated data buffer is full.
Circular Buffer Mode 2 where the number of messages transacted defines bulk transfer progress, and message data
words are stored contiguously in one buffer while message information and time-tag words are stored in a separate
buffer. Several host interrupt options are offered, including an interrupt generated when all N messages are success-
fully completed.
The 4-word Descriptor Table entry for each command (its descriptor block) begins with a Control Word. There are four
types of descriptor Control Word:
• Receive Subaddress Control Word

• Transmit Subaddress Control Word
• Receive Mode Command Control Word
• Transmit Mode Command Control Word
The descriptor Control Word is initialized by the host to select data buffer method and interrupt options. After a
command is processed by the terminal, the device updates the command’s descriptor Control Word. Updates will
differ based on the chosen data buffer method. Reading the descriptor table can differ from other RAM accesses. See
Sections 22.6 and 22.8.

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32 4-Word Blocks per Quadrant

Descriptor Word 4 for Tx MC30 0x05FB
0x05FF Mode Code 31 Block
Descriptor Word 3 for Tx MC30 0x05FA
Mode Code 30 Block
Descriptor Word 2 for Tx MC30 0x05F9
Transmit Mode Code Quadrant Control Word for Tx MC30 0x05F8

(Mode Codes with T/R bit = 1)
32 Descriptor Blocks
of 4 words each
Mode Code 1 Block
Mode Code 0 Block

0x0580
Descriptor Word 4 for Rx MC30 0x057B
0x057F
Mode Code 31 Block
Descriptor Word 3 for Rx MC30 0x057A
Mode Code 30 Block
Descriptor Word 2 for Rx MC30 0x0579
Receive Mode Code Quadrant Control Word for Rx MC30 0x0578

(Mode Codes with T/R bit = 0)
of 4 words each
Example 4-Word Descriptor Blocks
from Each Table Quadrant
Mode Code 1 Block
0x0500 Mode Code 0 Block

Descriptor Word 4 for Tx SA30 0x04FB
0x04FF Subaddress 31 Block See Note.
Descriptor Word 3 for Tx SA30 0x04FA
Subaddress 30 Block
Descriptor Word 2 for Tx SA30 0x04F9
Control Word for Tx SA30 0x04F8

Transmit Subaddress Quadrant
of 4 words each
Subaddress 1 Block
0x0480 Subaddress 0 Block See Note.

Descriptor Word 4 for Rx SA30 0x047B
0x047F Subaddress 31 Block See Note.
Descriptor Word 3 for Rx SA30 0x047A
Subaddress 30 Block
Descriptor Word 2 for Rx SA30 0x0479
Control Word for Rx SA30 0x0478

Receive Subaddress Quadrant
of 4 words each
NOTE:
Subaddress 1 Block SA0 and SA31 indicate mode codes, so
are not valid Receive or Transmit Subaddresses.
0x0400 Subaddress 0 Block See Note.
Figure 13. Address Mapping for RT Descriptor Table

Note: Assumes default table base address = 0x0400.
Before initializing the RT Descriptor Table, the RTENA bit must be set in Master Configuration Register 0x0000.

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Command RT Addr T/R Subaddress Word Count Command RT Addr T/R Subaddress Mode Code
Sync TA4:0 Bit SA4:0 WC4:0 Sync TA4:0 Bit SA4:0 MC4:0
P P
Descriptor Address Format

Depends On
0x04
Command Word’s Subaddress 0x05
0 0 0 0 0 1 00 0 0 0 0 0 0 0 1 01 0 0
SA1
MC1
MC2
SA2
SA4
SA0
MC4
MC0
SA3
MC3
T/R
T/R
Descriptor Table Address Descriptor Table Address
for Subaddress Commands for Mode Code Commands
SA4:0 equals 00001 to 11110 SA4:0 equals 00000 or 11111
Figure 14. Deriving a Descriptor Table Control Word Address From Command Word
(assumes table base address = 0x0400)
16.4.1. Receive Subaddress Control Word

Receive Subaddress Control Words apply when a valid command word T/R bit equals zero (receive) and the subaddress
field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response
and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution
begins. If using ping-pong data buffers, Control Words should only be written when the RTENA bit is set in the “Master
Configuration Register 1 (0x0000)”. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when
PPEN bit 2 is set, and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the
host; these bits are updated by the device during terminal execution, that is, when the “Master Configuration Register
1 (0x0000)” RTSTEX bit equals 1. The host can write bits 0-2 and 4-7 only when RSTEX equals zero; bits 3 and 12-
15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just
the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset.
H Bit maintained by host

BA SY
IR 1
IR N3
IR 2
O 0
C EN
N
C ZN
C 2ZN
ST 2ZN
PP PP
PP ST
IW Z
1E
2Z
U
N
D C
C N
EQ
2
KB
O
PB
E
A
IR
IR
IR
R
BC
Bit maintained by device

IX
IB
M
D
C
C
D
H H H H D1 D D D H H H H H H H H
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB D1 Bit set by device, reset by host read cycle
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is
unchanged unless specifically indicated by an “SR” value.

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Interrupt When Index Equals Zero.

If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ
bit is high, assertion of this bit enables generation of an interrupt for (a)
subaddresses using indexed buffer mode when the INDX value decrements
15 IXEQZ R/W 0 from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-
determined number of messages has been transacted. If enabled, upon
completion of command processing that results in index = 0, an IXEQZ
interrupt is entered in the “Remote Terminal (RT) Pending Interrupt Register
(0x0009)”, output pin INT is asserted, and the interrupt is registered in the
Interrupt Log.
Interrupt When Accessed.

If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IWA bit is
high, assertion of this bit enables interrupt generation when the subaddress
14 IWA R/W 0 receives any valid receive command. If enabled, upon completion of command
processing, an IWA interrupt is entered in the “Remote Terminal (RT) Pending
Interrupt Register (0x0009)”, output pin INT is asserted, and the interrupt is
registered in the Interrupt Log.
Interrupt Broadcast Received.

If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IBR bit is
receives a valid broadcast command. If enabled, upon completion of message
13 IBR R/W 0 processing an IBR interrupt is entered in the “Remote Terminal (RT) Pending
Interrupt Register (0x0009)”, output pin INT is asserted, and the interrupt is
registered in the Interrupt Log. This bit has no function if the BCSTINV bit is
high in the “Remote Terminal Configuration Register (0x0017)”. In this case,
commands to RT address 31 are not recognized as valid by the device.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this receive subaddress. This bit is an alternative to globally applying Busy
12 MKBUSY R/W 0 status for all valid commands, enabled from the “Remote Terminal MIL-
STD-1553 Status Word Bits Register (0x001A)”. See that register description
for additional information. When Busy is asserted, received data words are not
stored and the DPB bit does not toggle after message completion.
Descriptor Block Accessed.
0 Internal device logic asserts the DBAC bit upon completion of message
11 DBAC R SR = 0 processing. The host may poll this bit to detect subaddress activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.

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Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong
buffer mode. This bit indicates the buffer to be used for the next occurring
receive command to this subaddress. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message uses
Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-
0 free message completion. To also ensure the DPB bit is not altered after
10 DPB R SR = 0 illegal commands or messages ending with Busy status, the DPBTOFF
bit should be set in the “Extended Configuration Register (0x004D)”
on page 44. This ensures unsuccessful messages are not stored in the
data buffer and are overwritten by subsequent successful messages. (see
also “Ping-Pong Enable / Disable Handshake” on page 171). The DBP bit is
reset to logic 0 by MR master reset or SRST software reset; therefore the first
message received after either reset will use Buffer A. This bit is “don’t care” for
indexed single-buffer mode or either circular buffer mode.
Broadcast Command.
Device logic sets this bit when a valid broadcast receive command is received
at this subaddress. If IBR bit 13 and “Remote Terminal (RT) Interrupt Enable
9 BCAST R 0 Register (0x0012)” IBR bit are both set, the output pin INT is asserted. This bit
SR = 0 has no function if the BCSTINV bit is asserted in the “Remote Terminal Con-
figuration Register (0x0017)”; in this case commands to RT address 31 are not
recognized as valid by the device. This bit is reset to logic 0 by MR master
reset or SRST software reset.
Ping-Pong Enable Acknowledge.

This bit is controlled by the device and cannot be written by the host. It only
applies if PPEN bit 2 was initialized to logic one by the host after reset, en-
abling ping-pong buffer mode for this subaddress. Device logic asserts this bit
when it recognizes ping-pong is active for this subaddress. Before off-loading
the receive data buffer for this subaddress, the host can ask the device to
temporarily disable ping-pong by asserting STOPP bit 3. The device acknowl-
8 PPON R/W 0 edges ping-pong is disabled by negating PPON. The host can safely off-load
the buffer without data collision while PPON is negated. After buffer servicing,
the host asks the device to re-enable ping-pong by negating STOPP bit 3. The
device acknowledges ping-pong is re-enabled by asserting PPON.
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for
this subaddress, ping-pong is disabled. Each new message overwrites exist-
ing data in the buffer specified by DPB bit 10, and the DPB bit does not toggle
after command completion.
Circular Mode 2 Zero Number.
7-4 CIR2ZN R/W 0 Used only in circular buffer mode 2, this 4-bit field is initialized with the number
of trailing zeros in the initialized MIBA address. This is explained in Section
17.6, which fully describes circular buffer mode 2.
Stop Ping-Pong Request.

The host asserts this bit to suspend ping-pong buffering for this subaddress.
3 STOPP R/W 0 The host resets this bit to ask the device to re-enable ping-pong. The device
confirms recognition of ping-pong enable or disable status by writing PPON bit
8. Refer to Section 17.3, which fully describes ping-pong mode.

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Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable.

The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select buffer
mode. The table below summarizes how buffer mode selection is encoded.
In the case of ping-pong, the host initializes the PPEN bit to logic one after
reset to enable ping-pong buffering for this subaddress. The host asserts
STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating
2 PPEN R/W 0 the STOPP bit asks the device to re-enable ping-pong. The device confirms
1 CIR2EN R/W 0 ping-pong enable or disable state changes by writing the PPON bit. PPEN bit
2 should only be initialized or otherwise written when the RTENA bit is also set
0 CIR1EN R/W 0 in the “Master Configuration Register 1 (0x0000)”.
PPEN CIR2EN CIR1EN Buffer Mode
1 Don’t Care Don’t Care Ping-Pong
0 1 Don’t Care Circular Mode 2
0 0 1 Circular Mode 1
Indexed Single
0 0 0
Buffer
16.4.2. Transmit Subaddress Control Word

Transmit Subaddress Control Words apply when a valid command word T/R bit equals one (transmit) and the
subaddress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command
response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal
execution begins. If using ping-pong data buffers, Control Words should only be written when the applicable RTENA
bit is set in the “Master Configuration Register 1 (0x0000)”. Failure to meet this requirement prevents automatic
assertion of PPON bit 8 when PPEN bit 2 is set, and successive messages will repeatedly use the same buffer. Bits
8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when the
“Master Configuration Register 1 (0x0000)” RTSTEX bit equals 1. The host can write bits 0-2 and 4-7 only when
RTSTEX equals zero; bits 3,12 and 14-15 can be written anytime. This register is cleared to 0x0000 by MR master
reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any host read cycle to the
Control Word address, the DBAC bit is reset.

BA SY
IR 1
IR 3
IR 2
O 0
C EN
N
C ZN
C ZN
C 2ZN
ST 2ZN
PP PP
PP ST
IW Z
1E
U
C N
D C
C N
EQ
2
2
2
KB
O
PB
E
A
IR
IR
IR
BC

IX
M
D
D
H H X H D1 D D D H H H H H H H H
X Bit is not used, may be logic 0 or 1
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.

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If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ bit
is high, assertion of this bit enables generation of an interrupt for (a) subad-
dresses using indexed buffer mode when the INDX value decrements from
15 IXEQZ R/W 0 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-deter-
mined number of messages has been transacted. If enabled, upon comple-
tion of command processing that results in index = 0, an IXEQZ interrupt is
entered in the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”,
output pin INT is asserted, and the interrupt is registered in the Interrupt Log.

14 IWA R/W 0 receives any valid transmit command. If enabled, upon completion of com-
mand processing, an IWA interrupt is entered in the “Remote Terminal (RT)
Pending Interrupt Register (0x0009)”, output pin INT is asserted, and the
interrupt is registered in the Interrupt Log.
13 ----- ----- 0 Not Used
Make Busy.
to this transmit subaddress. This bit is an alternative to globally applying
12 MKBUSY R/W 0 Busy status for all valid commands, enabled from the “Remote Terminal MIL-
STD-1553 Status Word Bits Register (0x001A)”. See that register description
for additional information. When Busy is asserted, data words are not trans-
mitted and the DPB bit does not toggle after message completion.
0 Internal device logic asserts the DBAC bit upon completion of message
11 DBAC R SR = 0 processing. The host may poll this bit to detect subaddress activity, instead of
using host interrupts. This bit is reset to logic zero by MR master reset, SRST
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong buf-
fer mode. This bit indicates the buffer to be used for the next occurring trans-
mit command to this subaddress. When the DPB bit is logic 0, the next mes-
sage will use Data Pointer A; when DPB is logic 1, the next message uses
Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-
0 free message completion. To also ensure the DPB bit is not altered after
10 DPB R SR = 0 illegal commands or messages ending with Busy status, the DPBTOFF
bit should be set in the “Extended Configuration Register (0x004D)”
on page 44. This ensures unsuccessful messages are not stored in the
data buffer and are overwritten by subsequent successful messages. (see
also “Ping-Pong Enable / Disable Handshake” on page 171). The DBP bit is
reset to logic 0 by MR master reset or SRST software reset; therefore the first
message received after either reset will use Buffer A. This bit is “don’t care”
for indexed single-buffer mode or either circular buffer mode.

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Broadcast Received.
The device sets this bit when a broadcast-transmit command is received
for this subaddress. Because non-mode broadcast-transmit commands are
always illegal, the assertion of this bit in the Control Word by the device indi-
9 BCAST R 0 cates an illegal command was received. Terminal response varies, depending
SR = 0 on whether or not illegal command detection applies (any bits set in Illegal-
ization Table). This bit has no function if the BCSTINV bit is asserted in the
“Remote Terminal Configuration Register (0x0017)”; in this case commands
to RT address 31 are not recognized as valid by the device. This bit is reset
to logic 0 by MR master reset or SRST software reset.

This bit is controlled by the device and should not be written by the host. It
only applies if PPEN bit 2 was initialized to logic one by the host after reset,
enabling ping-pong buffer mode for this subaddress. The RT asserts this
bit when it recognizes ping-pong is active for this subaddress. Before load-
ing the transmit data buffer for this subaddress, the host can ask the RT to
temporarily disable ping-pong by asserting STOPP bit 3. The RT acknowl-
8 PPON R/W 0 edges ping-pong is disabled by negating PPON. The host can safely load the
buffer without data collision while PPON is negated. After buffer servicing, the
host asks the RT to re-enable ping-pong by negating STOPP bit 3. The RT
acknowledges ping-pong is re-enabled by asserting PPON.
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for
this subaddress, ping-pong is disabled. Each new message transmits data
from the same buffer, specified by DPB bit 10, and the DPB bit does not
toggle after command completion.
Circular Mode 2 Zero Number.
7-4 CIR2ZN R/W 0 Used only in circular buffer mode 2, this 4-bit field is initialized with the
number of trailing zeros in the initialized MIBA address. This is explained in
Section 17.6, which fully describes circular buffer mode 2.

The host asserts this bit to suspend ping-pong buffering for this subaddress.
3 STOPP R/W 0 The host resets this bit to ask the RT to re-enable ping-pong. The RT con-
firms recognition of ping-pong enable or disable status by writing PPON bit 8.
Refer to Section 17.3, which describes ping-pong mode in detail.

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HI-6138
Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable.

The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select
buffer mode. The table below summarizes how buffer mode selection is
encoded.
In the case of ping-pong, the host initializes the PPEN bit to logic one after
reset to enable ping-pong buffering for this subaddress. The host asserts
STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the
2 PPEN R/W 0
STOPP bit asks the device to re-enable ping-pong. The device confirms ping-
1 CIR2EN R/W 0 pong enable or disable state changes by writing the PPON bit. PPEN bit 2
0 CIR1EN R/W 0 should only be initialized or otherwise written when the RTENA bit is also set
in the “Master Configuration Register 1 (0x0000)”.
PPEN CIR2EN CIR1EN Buffer Mode
1 Don’t Care Don’t Care Ping-Pong

0 1 Don’t Care Circular Mode 2
0 0 1 Circular Mode 1
Indexed Single
0 0 0
Buffer
16.4.3. Data Buffer Options for Mode Code Commands

Data buffer options for mode code commands differ from options offered for subaddress commands. Mode commands
cannot use either circular data buffer method, but may use double (ping-pong) buffering or single (indexed) buffering.
Single message Index mode (INDX = 0) is suitable in many applications (see Section 17.4.1). An alternative called
Simplified Mode Command Processing (SMCP) may be globally applied for all mode code commands (see Section
18.5).
To use single (indexed) buffer or double (ping-pong) buffer for mode commands, the SMCP bit in the “Remote Terminal
Configuration Register (0x0017)” is logic 0. The Control Word PPEN bit for each mode command determines whether
ping-pong or indexed buffering is used.
To use Simplified Mode Command Processing, the SMCP bit in the “Remote Terminal Configuration Register (0x0017)”
is set to logic 1. The Control Word PPEN bit for mode commands is “don’t care” (no longer specifies index or ping-pong
buffer mode) because Simplified Mode Command Processing stores mode command data and message information
words directly within each mode command’s redefined Descriptor Table block. When SMCP is enabled, mode code
command descriptor blocks (in the Descriptor Table) do not contain data pointers to reserved buffers elsewhere in the
shared RAM. Instead, each 4-word descriptor block itself contains the message information word, the time-tag word
and the data word transacted for each mode command (for mode codes 16-31 decimal).
When Simplified Mode Command Processing is used, the range of active bits is reduced in each receive or transmit
mode command Control Word. Interrupt control and response is not affected by the SMCP option. Simplified Mode
Command Processing is fully presented in the later data sheet section 18.5.

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16.4.4. Receive Mode Control Word

Receive Mode Control Words apply when the command word T/R bit equals zero (receive) and the subaddress field
has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior,
and conveys activity status to the host. It is initialized by the host before terminal execution begins. If using ping-pong
data buffers, Control Words should only be written when the RTENA bit is set in the “Master Configuration Register
1 (0x0000)”. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2 is set,
and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these bits are
updated by the device during terminal execution, that is, when the “Master Configuration Register 1 (0x0000)” RTSTEX
bit equals 1. The host can write bit 2 only when RTSTEX equals zero; bits 3 and 12-15 can be written anytime. This
register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits.
Following any read cycle to the Control Word address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code
Processing), the receive mode Control Word looks like this:

BA Y
D US
PP PP
PP ST
IW Z
N
D C
EN
EQ
KB
O
PB
O
A
R
BC
ST
IB

IX
D
H H H H D1 D D D X X X X H H X X
When SMCP applies, the number of active mode Control Word bits is reduced:

SY
PP ST
IW Z
N
C
EQ
KB
O
BA
A
A
R
BC
IB

IX
M
D
D
H H H H D1 X D D X X X X X X X X

is high, assertion of this bit enables generation of an interrupt for mode code
15 IXEQZ R/W 0 commands using indexed buffer mode when the INDX value decrements
from 1 to 0. Upon completion of command processing that results in INDX =
0, when IXEQZ interrupts are enabled, an IXEQZ interrupt is entered in the
“Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the INT output
pin is asserted, and the interrupt is registered in the Interrupt Log.

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HI-6138

high, assertion of this bit enables interrupt generation at each instance of
14 IWA R/W 0 a valid mode code command. Upon completion of command processing,
when IWA interrupts are enabled, an IWA interrupt is entered in the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)”, the INT output pin is
asserted, and the interrupt is registered in the Interrupt Log.

high, assertion of this bit enables interrupt generation at each instance of a
valid broadcast receive mode code command. Upon completion of command
13 IBR R/W 0 processing, when IBR interrupts are enabled, an IBR interrupt is entered in
the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the INT
output pin is asserted, and the interrupt is registered in the Interrupt Log.
This bit has no function if the BCSTINV bit is high in the “Remote Terminal
Configuration Register (0x0017)”. In this case, commands to RT address 31
are not recognized as valid by the device.
Make Busy.
to this mode code. This bit is an alternative to globally applying Busy status
12 MKBUSY R/W 0 for all valid commands, enabled from the “Remote Terminal MIL-STD-1553
Status Word Bits Register (0x001A)”. See that register description for ad-
ditional information. When Busy is asserted, mode data words received with
MC16-MC31 are not stored and the DPB bit does not toggle after message
completion.
0 Internal device logic asserts the DBAC bit upon completion of message pro-
11 DBAC R SR = 0 cessing. The host may poll this bit to detect mode command activity, instead
Data Pointer B.
This status bit is maintained by the device and only applies for mode com-
mands using ping-pong buffer mode. This bit indicates the buffer to be used
for the next occurring mode command. When the DPB bit is logic 0, the
next message will use Data Pointer A; when DPB is logic 1, the next mes-
sage uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after
0 each error-free message completion. To also ensure the DPB bit is not
10 DPB R SR = 0 altered after illegal commands or messages ending with Busy status,
the DPBTOFF bit should be set in the “Extended Configuration Regis-
ter (0x004D)” on page 44. This ensures unsuccessful messages are not
stored in the data buffer and are overwritten by subsequent successful mes-
sages. (see also “Ping-Pong Enable / Disable Handshake” on page 171).
The DBP bit is reset to logic 0 by MR master reset or SRST software reset;
therefore the first message received after either reset will use Buffer A. This
bit is “don’t care” for indexed single-buffer mode.

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Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
9 BCAST R 0 having T/R bit = 0. This bit has no function if the BCSTINV bit is asserted
SR = 0 in the “Remote Terminal Configuration Register (0x0017)”. In this case, RT
address 31 commands are not recognized as valid by the device. This bit is
reset to logic 0 by MR master reset or SRST software reset.

This bit is read only and only applies for mode commands using ping-pong
mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The
device asserts this bit when it recognizes ping-pong is active for this mode
code. Before off-loading the receive data buffer for this mode code, the host
can ask the device to temporarily disable ping-pong by asserting STOPP
bit 3. The device acknowledges ping-pong is disabled by negating PPON.
8 PPON R/W 0 The host can safely load or off-load the buffer without data collision while
PPON is negated. After buffer servicing, the host asks the device to re-enable
ping-pong by negating STOPP bit 3. The device acknowledges ping-pong is
re-enabled by asserting PPON.
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive
for this subaddress, ping-pong is disabled. Each new message overwrites
existing data in the buffer specified by DPB bit 10, and the DPB bit does not
toggle after command completion.
7-4 ----- ----- 0 Not Used

The host asserts this bit to suspend ping-pong buffering for this mode code.
confirms recognition of ping-pong enable or disable status by writing PPON
bit 8.
Ping-Pong Buffer Enable.

The PPEN bit is initialized by the host to select buffer mode. If this bit is high,
ping-pong buffering is selected. If this bit is low, indexed single buffering is
selected.
After reset, the host initializes this bit to logic 1 to enable ping-pong buffering
2 PPEN R/W 0
for this mode code. The host asserts STOPP bit 3 to ask the device to
temporarily disable ping-pong. Negating the STOPP bit asks the device to
re-enable ping-pong. The device confirms ping-pong enable or disable state
changes by writing the PPON bit 8. PPEN bit 2 should only be initialized or
otherwise written when the RTENA bit is also set in the “Master Configuration
Register 1 (0x0000)”.
1,0 ----- ----- 0 Not Used.

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16.4.5. Transmit Mode Control Word

Transmit Mode Control Words apply when the command word T/R bit equals one (transmit) and the subaddress field
has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior,
and conveys activity status to the host. It is initialized by the host before terminal execution begins. If using ping-
pong data buffers, Control Words should only be written when the RTENA bit is also set in the “Master Configuration
Register 1 (0x0000)”. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when PPEN bit 2
is set, and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the host; these
bits are updated by the device during terminal execution, that is, when the “Master Configuration Register 1 (0x0000)”
RTSTEX bit equals 1. The host can write bit 2 only when RTSTEX equals zero; bits 3 and 12-15 can be written
anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB
and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code
Processing), the transmit mode Control Word looks like this:

BA Y
D US
PP PP
PP ST
IW Z
N
D C
EN
EQ
KB
O
PB
O
A
R
BC
ST
IB

IX
D
H H H H D1 D D D X X X X H H X X
When SMCP applies, the number of active mode Control Word bits is reduced:

SY
PP ST
IW Z
N
C
EQ
KB
O
BA
A
A
R
BC
IB

IX
M
D
D
H H H H D1 X D D X X X X X X X X

is high, assertion of this bit enables generation of an interrupt for mode code
15 IXEQZ R/W 0 commands using indexed buffer mode when the INDX value decrements
from 1 to 0. Upon completion of command processing that results in INDX =
0, when IXEQZ interrupts are enabled, an IXEQZ interrupt is entered in the
“Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the INT output
pin is asserted, and the interrupt is registered in the Interrupt Log.

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high, assertion of this bit enables interrupt generation at each instance of
14 IWA R/W 0 a valid mode code command. Upon completion of command processing,
when IWA interrupts are enabled, an IWA interrupt is entered in the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)”, the INT output pin is
asserted, and the interrupt is registered in the Interrupt Log.

high, assertion of this bit enables interrupt generation at each instance of a
valid broadcast transmit mode code command. Upon completion of command
13 IBR R/W 0 processing, when IBR interrupts are enabled, an IBR interrupt is entered in
the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the INT
output pin is asserted, and the interrupt is registered in the Interrupt Log.
This bit has no function if the BCSTINV bit is high in the “Remote Terminal
Configuration Register (0x0017)”. In this case, commands to RT address 31
are not recognized as valid by the device.
Make Busy.
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the “Remote Terminal MIL-STD-1553
12 MKBUSY R/W 0 Status Word Bits Register (0x001A)”. See that register description for addi-
tional information. When Busy is asserted, mode data words are not transmit-
ted with MC16-MC31, and the DPB bit does not toggle after message com-
pletion. The MKBUSY bit is not heeded if set in the Control Word for mode
code command MC8 “reset remote terminal”. For this command only, Busy is
inhibited for the status response transmitted before the reset process begins.
0 Internal device logic asserts the DBAC bit upon completion of message pro-
11 DBAC R SR = 0 cessing. The host may poll this bit to detect mode command activity, instead
Data Pointer B.
This status bit is maintained by the device and only applies for mode
commands using ping-pong buffer mode. This bit indicates the buffer to be
used for the next occurring mode command. When the DPB bit is logic 0,
the next message will use Data Pointer A; when DPB is logic 1, the next
message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted
0 after each error-free message completion. To also ensure the DPB bit
10 DPB R SR = 0 is not altered after illegal commands or messages ending with Busy
status, the DPBTOFF bit should be set in the “Extended Configuration
Register (0x004D)” on page 44. This ensures unsuccessful messages
are not stored in the data buffer and are overwritten by subsequent
successful messages. (see also “Ping-Pong Enable / Disable Handshake”
on page 171). The DBP bit is reset to logic 0 by MR master reset or SRST
software reset; therefore the first message received after either reset will use
Buffer A. This bit is “don’t care” for indexed single-buffer mode.

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Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
9 BCAST R 0 having T/R bit = 1. This bit has no function if the BCSTINV bit is asserted
SR = 0 in the “Remote Terminal Configuration Register (0x0017)”. In this case, RT
address 31 commands are not recognized as valid by the device. This bit is
reset to logic 0 by MR master reset or SRST software reset.

This bit is read only and only applies for mode commands using ping-pong
mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The
device asserts this bit when it recognizes ping-pong is active for this mode
code. Before loading the transmit data buffer for this mode code, the host can
ask the device to temporarily disable ping-pong by asserting STOPP bit 3.
The device acknowledges ping-pong is disabled by negating PPON. The host
8 PPON R/W 0 can safely load or off-load the buffer without data collision while PPON is ne-
gated. After buffer servicing, the host asks the device to re-enable ping-pong
by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled
by asserting PPON.
If PPEN bit 2 is asserted and PPON bit 8 is negated when a new command
arrives for this mode code, ping-pong disable handshake is in effect: The
device applies single-buffer index mode using Data Pointer A or Data Pointer
B, per DPB bit 10. The DPB bit does not toggle after command completion.
7-4 ----- ----- 0 Not Used

The host asserts this bit to suspend ping-pong buffering for this mode code.
confirms recognition of ping-pong enable or disable status by writing PPON
bit 8.
Ping-Pong Buffer Enable.

The PPEN bit is initialized by the host to select buffer mode. If this bit is high,
ping-pong buffering is selected. If this bit is low, indexed single buffering is
selected.
After reset, the host initializes this bit to logic 1 to enable ping-pong buffering
2 PPEN R/W 0
for this mode code. The host asserts STOPP bit 3 to ask the device to
temporarily disable ping-pong. Negating the STOPP bit asks the device to
re-enable ping-pong. The device confirms ping-pong enable or disable state
changes by writing the PPON bit 8. PPEN bit 2 should only be initialized or
otherwise written when the RTENA bit is also set in the “Master Configuration
1,0 ----- ----- 0 Not Used.

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17. REMOTE TERMINAL MESSAGE DATA BUFFERS

The memory structures described up to this point comprise not more than 2K words of the lower memory address
space. The remaining memory is allocated by the host for message data storage, to fulfill application requirements.
This section describes the remaining data structures in shared RAM that control (and result from) command process-
ing.
By initializing the RT Descriptor Table, the host allocates memory space for storing data for each subaddress used in
the Remote Terminal application. Each legal Receive Subaddress and each legal Transmit Subaddress are usually
assigned unique buffer memory spaces. (Exception: To comply with the requirements for MIL-STD-1553 data wrap-
around, it is convenient to assign the data wrap-around subaddress to use the same buffer space for both receive and
transmit commands.)
As an option, data from broadcast receive commands can be stored separately from data resulting from non-broadcast
receive commands. Each subaddress buffer can use any of four data storage methods offered.
Subaddress (non-mode) commands are transacted with one to 32 data words. These are stored in a data buffer in
shared RAM. For receive commands, the device stores data received during message processing in the shared RAM
buffer. Later, the host retrieves these data words from the buffer. In the case of transmit commands, the host has
previously stored transmit data words in the transmit subaddress buffer. The device retrieves these data words for
transmission while processing the transmit command.
For each complete message processed, the message data stored in the buffer is comprised of these elements:
1. Message Information Word.
2. Time-Tag Word.
3. One to 32 Data Words transmitted or received during message transaction ( except no data word for mode code
commands 0 - 15 decimal).
The Message Information word and Time-Tag word are generated by the device and stored in assigned buffer space
to aid the host in further message processing. The Message Information word contains message type, word count and
message error information. The 16-bit Time-Tag word contains the value in the device internal Time-Tag counter when
the command is validated.
The host initializes the Descriptor Table entry for each subaddress or mode command to select one of four data buffer-
ing methods.
1. Indexed (Single Buffer) Method (see 17.4).

A predetermined number of messages (N) is transacted using a single data buffer in shared RAM. Several host in-
terrupt options are offered, including host interrupt when all N messages are successfully completed. This method
also supports single-message mode when N is purposely initialized to zero.
2. Double (or Ping-Pong) Buffer Method (see 17.3).

Successive messages alternate between two 34-word data buffers in shared RAM. Several host interrupt options
are offered.
3. Circular Buffer Mode 1 (see 17.5).

Buffer boundaries determine when the bulk transfer is complete. Message information and time-tag words are
stored in the same buffer with data words. Several host interrupt options are offered, including host interrupt when
the allocated data buffer is full.
4. Circular Buffer Mode 2 (see 17.6).

The number of messages transacted defines bulk transfer progress. Message data words are stored contiguously
in one buffer while message information and time-tag words are stored in a separate buffer. Several host interrupt
options are offered, including host interrupt when all N messages are completed.

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The data buffer options are summarized in Table 12.
Simplified Mode Command Processing.

This is a global option that applies for all mode code commands, when enabled. Mode commands have either one data
word, or no data word. Instead of using data buffers for storing this limited mode command data, the message data is
stored directly within the Descriptor Table. This option for mode commands is described in section 18.5.
Broadcast Data Separation

When the NOTICE2 option is enabled, data words resulting from broadcast receive commands will be stored separate-
ly from data resulting from non-broadcast receive commands when using indexed or ping-pong buffer modes. When
NOTICE2 applies, all subaddresses using indexed or ping-pong modes must have an assigned 34-word broadcast
data buffer in addition to the primary buffers listed above.
When using circular buffers with Notice 2, the user is responsible for separating buffer data stored by broadcast and
non-broadcast messages. To make this possible, an option is offered that provides a BCAST status bit in the data
buffer Message Information Word (MIW), saved in the data buffer each time a message is received. By examining the
MIWs stored in the circular buffer, the host can differentiate broadcast from non-broadcast messages. See description
of option bit 3 in the “Extended Configuration Register (0x004D)”, as well as Section 20.1 below.
Table 12. Summary of Data Buffer Modes.
Buffer Data Buffer(s) Message Info Suitable for

Primary Application
Mode Number and Size Word Mode Codes?
One. Host defines Stored in same Yes, only single For transacting N (multiple) messages
Indexed
size for N messages buffer as data message mode with optional host interrupt when done
Two 34-word buffers, Stored in same For transacting single messages,

Ping-Pong Yes
one message each buffer as data alternating between A and B buffers
One. Host defines Stored in same For transacting messages until buffer is
Circular 1 No
size for N words buffer as data full / empty, optional interrupt when done
One. Host defines Stored in For transacting N (multiple) messages

Circular 2 size for N messages, separate buffer No with optional host interrupt when done.
plus Msg Info Block (Msg info block) Data buffer holds contiguous pure data.
17.1. Subaddress Message Information Words
17.1.1. Receive Subaddress Command

For receive subaddress commands, the device stores the received data words plus two additional words. The device
adds a receive subaddress Message Information Word and a Time-Tag Word to the received data words. The device
stores the Message Information and Time-Tag words ahead of the data words associated with the receive command,
as shown below. If message error occurs, the RT stores only the receive subaddress Message Information Word and
Time-Tag Word. Once a message error is detected, the device sets the MERR bit in the receive subaddress Message
Information Word. When this occurs, all data words are considered invalid. Whenever the receive subaddress Message
Information Word MERR bit is set, the host should disregard the record’s data word(s).
Here is an example data structure for a 3-word receive command. Notice that the receive subaddress Data Pointer
points to the data structure starting address, not the first data word. The data pointer is located in the receive subad-
dress command’s Descriptor Block, fully described later:

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Data Buffer
Word Description Device Writes Word ...
Hex Address
Data pointer equals 0x1500 → 0x1500 Message Information Word After message completion
0x1501 Time-Tag Word “ “ “
0x1502 Data Word 1 After message completion (See Note)
0x1503 Data Word 2 “ “ “ “ “
0x1504 Data Word 3 “ “ “ “ “
Note: The data words are written

after message completion when the
RT Configuration Register bit TRXDB
is 1, otherwise written when received.
SY ER ST
R RR
C A
N R
D R
C Y
ER R
AP R
W /BC
IL BS
IW ER
M ER
G ER
RT TE
TX D
W ID
W R
BU T
M
T
AS
4
O
3
2
1
0
S
R
C
C
C
C
C
TM
W
W
W
W
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
The following bits comprise the receive subaddress Message Information Word:
Time-Out Error.
15 TMOERR This bit is asserted for RT-RT receive messages when the transmitting terminal fails to
start its status word and data transmission before time-out occurs, per RTTO[1:0] bits in
the “Remote Terminal Configuration Register (0x0017)”.
Invalid Word Error.

14 IWDERR Assertion of this bit indicates Manchester error or parity error was observed in a received
data word.
Gap Error / Broadcast Flag.

When “Extended Configuration Register (0x004D)” on page 44 bit 3 is 0, this bit is a
Gap Error flag. Assertion of this bit indicates bus activity was detected immediately after
GAP/
13 the last expected receive data word or that a gap occurred before all expected data words
BCAST
were received.
Broadcast flag, asserted when the received message was broadcast.
Word Count Error.
12 WCTERR This bit is asserted if command is received with less data words than the command word
specifies. For example, a receive command for three data words is received with two
contiguous data words.
Sync Error.
11 SYNERR This bit is asserted when an incorrect (command/status) sync type occurs in received data
words.

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Message Error.
10 MERR This bit is asserted when message error status change occurs during command process-
ing. See bits 7 and 11-15 for details.
Was Busy.
This bit is asserted when the terminal responds to the receive command with BUSY
9 WASBSY status, due to global BUSY bit set in “Remote Terminal MIL-STD-1553 Status Word Bits
Register (0x001A)”, or command-specific MKBUSY bit set in the descriptor table Control
Word. Received data words were buffered normally.
Illegal Command Received.
8 ILCMD This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal
command detection” is being applied. See Section 16.2 for further information.
RT-RT Transmit Remote Terminal Error.

This bit is set when the terminal decodes a valid RT-RT receive command, but one of four
potential errors is detected in the second command word, CW2: (1) CW2 is addressed
to broadcast address RT31. (2) the CW2 T/R bit equals 0, (3) the CW2 subaddress is a
7 TXRTERR mode command indicator, 00000 or 11111, or (4) CW2 has same non-broadcast terminal
address as receive command word CW1.
The TXRTERR bit is also set when status word received from the transmitting terminal
is invalid (e.g., parity error) or bits 15:11 in the status word reflect the wrong RT address
(does not match CW2).
Remote Terminal to Remote Terminal Transfer.

6 RTRT
Assertion of this bit indicates the receive command was an error-free RT-to-RT transfer.
Bus Identification.
5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans-
acted on Bus B.
Word Count.
4-0 WC4:0 This 5-bit field contains the word count extracted from the command word. Zero indicates
32 words.
17.1.2. Transmit Subaddress Command

The external host is responsible for organizing the data packet (i.e., storing N data words) in shared RAM and initializ-
ing the applicable data pointer. The host must allocate two memory locations at the starting address of the data record
for device storage of the transmit subaddress Message Information Word and Time-Tag Word.
Here is an example data structure for a 3-word transmit command. Notice that the Data Pointer points to the data
structure starting address, not the first data word. The data pointer is located in the transmit subaddress command’s
Descriptor Block.

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Data Buffer
Word Description Word is Written By ...
Hex Address
Data pointer equals 0x1500 → 0x1500 Message Information Word Device, after message completion
0x1501 Time-Tag Word “ “ “ “
0x1502 Data Word 1 Host, prior to terminal’s data transmit
0x1503 Data Word 2 “ “ “ “ “ “
0x1504 Data Word 3 “ “ “ “ “ “
R T
TE S
C A
R
C Y
W /BC
IL BS
D
W ID
W R
BU T
M
AS
ER
AP
S
R
1
3
2
0
RT
W
W
W
W
M
G
X X X X
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
The following bits comprise the transmit subaddress Message Information Word.
15,14 ----- Not Used.

GAP/ Gap Error flag. Assertion of this bit indicates bus activity was detected immediately after
13
BCAST the transmit command word, when a gap was expected.
Word Count Error.

12 WCTERR
This bit is asserted if command is received with unexpected data word(s).
11 ----- Not Used.
Message Error.
ing. See bits 12 and 13 for details.
Was Busy Status.

This bit is asserted when the terminal responds to the transmit command with BUSY
9 WASBSY status, due to global BUSY bit set in “Remote Terminal MIL-STD-1553 Status Word Bits
Word. No data words were transmitted.
mand equals one. The Illegalization Table should only contain nonzero values when “il-
legal command detection” is being applied. See Section 16.2 for further information.
7 ----- Not Used.
Remote Terminal to Remote Terminal Transfer.

6 RTRT
Assertion of this bit indicates the transmit command was an error-free RT-to-RT transfer.

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Bus Identification.
acted on Bus B.
Word Count.
4-0 WC4:0 This 5-bit field contains the word count extracted from the command word. Zero indicates
32 words.
17.2. Mode Command Message Information Words

Mode command data structures in shared RAM are similar to those for subaddresses. Mode codes 0 through 15
(0x0F) do not have an associated data word, so data structures for these mode code values have just a Message
Information Word and Time-Tag Word. The Message Information Word is stored at the memory address specified by
the descriptor table Data Pointer. Mode codes 16 through 31 (0x10 through 0x1F) have one associated data word.
The Message Information Word is stored at the memory address specified by the descriptor table Data Pointer, and
the Time-Tag Word is stored in the following location. The data word is stored at the memory address specified by the
Data Pointer plus two locations.
17.2.1. Receive Mode Command

The receive mode command data structure contains a Message Information Word, a Time-Tag Word and may con-
tain one Data Word. If a receive mode command has a data word, the device may apply the data as defined by MIL-
STD-1553, plus store the received single mode data word at the address specified by the Data Pointer, plus two
locations. Refer to the Mode Code Command Summary in Table 14.
Here is an example data structure for a receive mode command with data (mode code values 0x10 through 0x1F).
Notice that the Data Pointer points to the data structure starting address, not the mode data word. The data pointer is
located in the receive mode command’s Descriptor Block, fully described later:
Data Buffer
Hex Address
0x1502 Mode Data Word “ “ “ “
Three receive mode commands with data are not defined under MIL-STD-1553B. These are MC16, MC18 and MC19
(mode codes 0x10, 0x12 and 0x13 respectively). However the device responds “in form” if illegal command detection
is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the “Remote Terminal
Configuration Register (0x0017)” is logic 0.
For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag
Word.
Here is an example data structure for a receive mode command without data (mode code values 0x00 through 0x0F).
Note: None of these receive mode commands are defined under MIL-STD-1553B but the device responds “in form” if
illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the
“Remote Terminal Configuration Register (0x0017)” is logic 0. Notice that the data pointer points to the data structure
starting address, the message information word. The data pointer is located in the receive mode command’s Descrip-
tor Block, fully described later:

166
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Data Buffer
Hex Address
SY ER ST
R RR
C A
N R
D R
C Y
ER R
AP R
W /BC
IL BS
IW ER
M ER
G ER
RT TE
TX D
W ID
W R
BU T
M
T
AS
4
O
3
2
1
0
S
R
C
C
C
C
C
TM
W
W
W
W
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
The following bits comprise the receive mode Message Information Word:
15 ----- Not Used.
Invalid Word Error.

14 IWDERR Assertion of this bit indicates Manchester error or parity error was observed in a received
data word.

GAP/ Gap Error flag. Assertion of this bit indicates bus activity was detected immediately after a
13
BCAST received mode data word or that a gap occurred before the data word was received.
Word Count Error

12 WCTERR This bit is asserted if the command is received without expected mode data word, or with
extra word.
Sync Error.
11 SYNERR This bit is asserted when incorrect (command/status) sync type occurs in received mode
data word.
Message Error.
ing. See bits 11- 14 for details.
Was Busy Status.

This bit is asserted when the terminal responds to the mode command with BUSY status,
9 WASBSY due to global BUSY bit set in the “Remote Terminal MIL-STD-1553 Status Word Bits
Word.

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mand equals one. The Illegalization Table should only contain nonzero values when “il-
legal command detection” is being applied. See Section 16.2 for further information.
7,6 ----- Not Used.
Bus Identification.
acted on Bus B.
Mode Code.
4-0 MC4:0
This 5-bit field contains the mode code extracted from the command word.
17.2.2. Transmit Mode Command

The transmit mode command data structure contains a Message Information Word, a Time-Tag word and may contain
one Data Word. For mode commands with associated data word (mode codes 16-31 decimal) the host is responsible
for loading the Mode Command Data Table before transmit mode commands are received (e.g., Transmit Vector Word
mode code). Two mode codes have internally generated data words: MC18 “Transmit Last Command” and MC19
“Transmit BIT Word”. For these, the device automatically transmits the data word then copies the transmitted data
value to the stored data structure.
Here is an example data structure for a transmit mode command with data (mode code values 0x10 through 0x1F).
This applies to MC16 “Transmit Vector Word”. Notice that the data pointer points to the data structure starting address,
not the mode data word. The data pointer is located in the transmit mode command’s Descriptor Block, fully described
later:
Data Buffer
Hex Address
0x1502 Mode Data Word Host, prior to terminal’s data transmit
(except MC18, MC19 are written by
the device after completion)
Three transmit mode commands with data are not defined under MIL-STD-1553B. These are MC17, MC20 and
MC21 (mode codes 0x11, 0x14 and 0x15 respectively). However the device responds “in form” if illegal command
detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in the “Remote
Terminal Configuration Register (0x0017)” is logic 0.
For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag
Word. Here is an example data structure for a transmit mode command without data (mode code values 0x00 through
0x0F). Again, the data pointer points to the data structure starting address. The data pointer is located in the transmit
mode command’s Descriptor Block, fully described later:

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Data Buffer
Hex Address
R T
TE S
C A
R
C Y
W /BC
IL BS
D
M ID
W R
M
AS
ER
AP
1
3
2
0
S
C
C
C
C
C
BU
M
M
M
M
M
G
X X X X X
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
The following bits comprise the mode transmit Message Information Word:
15,14 ----- Not Used.

GAP/ Gap Error flag. This bit is high when bus activity was detected immediately after the mode
13
BCAST command word, when a gap was expected.
Word Count Error

12 WCTERR
This bit is asserted if command is received with unexpected data word(s).
11 ----- Not Used.
Message Error.
ing. See bits 12-13 for details.
Was Busy Status.

This bit is asserted when the terminal responds to the mode command with BUSY status,
9 WASBSY due to global BUSY bit set in “Remote Terminal MIL-STD-1553 Status Word Bits Register
(0x001A)”, or command-specific MKBUSY bit set in the descriptor table Control Word. No
mode data word was transmitted.
mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal
command detection” is being applied. See Section 16.2 for further information.
7,6 ----- Not Used.
Bus Identification.
acted on Bus B.
Mode Code.
4-0 MC4:0
This 5-bit field contains the mode code extracted from the command word.

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17.3. Ping-Pong Data Buffering
17.3.1. Double Buffered (Ping-Pong) Mode

Ping-pong buffer mode is a method for storing message and time-tag information and data associated with messages.
Each unique MIL-STD-1553 subaddress and mode code is assigned a pair of data buffers for transmit commands and
a pair of data buffers for receive commands. The device retrieves buffer data for transmit commands, or stores buffer
data for receive commands. During ping-pong operation, the device alternates message storage between Data Buffer
A and Data Buffer B, on a message-by-message basis.
When a subaddress or mode command uses ping-pong data buffer mode, its 4-word descriptor block in the Descriptor
Table is defined as follows:
Descriptor Word 1 Control Word
Descriptor Word 2 Data Pointer A
Descriptor Word 3 Data Pointer B
Descriptor Word 4 Broadcast Data Pointer
If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two
words are stored at addresses N+2 and N+3.
Prior to starting terminal operation, enable ping-pong buffering for any subaddress (or mode code) by asserting the
PPEN bit and negating the STOPP bit in the descriptor Control Word. When the device detects ping-pong is selected
(PPEN = 1) and enabled (STOPP = 0), it asserts the Control Word PPON bit to confirm ping-pong is active.
During ping-pong operation, the RT determines the active data buffer at the beginning of message processing. The
Control Word DPB bit indicates the data pointer to be used by the next command. DPB equals logic 0 means Data
Pointer A is used next; DPB equals logic 1 means Data Pointer B is used next. For ping-pong, Data Pointers A and
B are static values pointing to the first address in each buffer. At the conclusion of error-free message processing,
the Control Word DPB bit is inverted so the next command “ping-pongs” to the other data buffer. Each new message
to the subaddress or mode code overwrites message data and information words written previously. To assure data
integrity, the DPB pointer should only toggle after completion of error-free messages. To cover the full set of conditions,
set DPBTOFF bit 1 in “Extended Configuration Register (0x004D)” on page 44. When option bit DPBTOFF = 1,
DPB pointer toggle is prevented after incomplete messages, illegal commands, and messages resulting in BUSY
or MESSAGE ERROR status. (When option bit DPBTOFF = 0, the illegal and BUSY cases still cause DPB pointer
toggle.)
Please note that a subaddress may contain both legal and illegal word counts. When DPBTOFF = 1, DPB pointer
toggle only occurs for the expected (legal) word count(s).
Figure 15 is a general illustration of ping-pong buffer mode. Figure 16 shows a specific example.
The primary benefit of using the DPBTOFF = 1 option is always knowing where to find the most-recent valid data. When
DPBTOFF = 1, the complemented DPB pointer always indicates the last-transacted “good” data set. For example, if
DPB is logic 0, the last successful message used Data Buffer B.
(Exception: immediately following Master Reset, the entire memory range is cleared to zero, so neither buffer contains
message data. After reset, the host typically initializes outgoing data for the first message occurring on each transmit
subaddress, Buffer A. The Message Information and Time Tag Words will read 0x0000 until the first message is
transacted. After reset, the first-used Buffer A for each receive subaddress will contain 0x0000 for the Message
Information and Time Tag Words and all data locations, until the first message is transacted).

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17.3.2. Ping-Pong Enable / Disable Handshake

Because ping-pong messages and host buffer servicing are asynchronous, there is potential for “data collision”. Here
is a data collision example: The host reads data from an earlier message while the device simultaneously writes new
message data to the same buffer. The host reads a mix of new and old message data. Collisions can occur for both
transmit and receive messages.
A handshake scheme lets the external host asynchronously service ping-pong data buffers without data collision. To
off-load or load a subaddress (or mode code) buffer, the application software performs the following sequence:
a. Host asserts the Control Word STOPP bit to suspend ping-pong operation for the subaddress. When the device
recognizes STOPP bit assertion, it negates the PPON bit to acknowledge ping-pong is disabled. While PPON
remains low, the last written (or read) data buffer is protected against device updates. During this time, new
messages use the active buffer indicated by the Control Word DPA bit. Recurring messages repeatedly use the
same buffer until ping-pong resumes.
b. Host services the last-used data buffer. If the Control Word DPB bit equals logic 1, the last command used
Buffer A. The host application software off-loads or loads inactive Buffer A while the remote terminal uses
active Buffer B for new message(s). If the DPB bit equals logic 0, the last command used Buffer B. The host
application software off-loads or loads inactive Buffer B while the remote terminal uses active Buffer A for any
new messages. Each new receive message overwrites buffer contents from the last receive message. To avoid
possible data loss, host buffer servicing should be timed for completion before a second message can occur.
c. Host negates the Control Word STOPP bit to resume ping-pong operation for the subaddress. When the RT
recognizes the STOPP bit is reset, it sets the PPON bit to acknowledge ping-pong is again active. As long as
PPON remains set, the device alternates between data buffers A and B for new messages.

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Data Word 32
Data Words 2-31
Data Word 1
Broadcast Message Time-Tag Word Data Word 32
(if NOTICE2 is asserted)
Message Info Word Data Words 2-31
Data Word 1
Subaddress
Buffer Space Message #2 Time-Tag Word
for Broadcast Message #4
(optional) Message #6 Message Info Word
etc.
Assigned
Subaddress
Data Buffer B
B’cast Data Pointer
Increasing Data Pointer B
Memory
Address Data Pointer A
Data Word 32
Control Word
Data Words 2-31
Data Word 1
Descriptor Block
Time-Tag Word
for Subaddress
Message #1 Message Info Word
Message #3
Message #5
etc. Assigned
Memory Address for the Applicable Subaddress
Subaddress Block is Derived From Data Buffer A
the Decoded Command Word
Message processing alternates between Data Buffers A and B. Upon sucessful message completion, the DPB
bit in Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every
other message.
Separate buffer for broadcast messages is optional. There is no alternate buffer for successive
broadcast messages.
Figure 15. Illustration of Ping-Pong Buffer Mode

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17.3.3. Broadcast Message Handling in Ping-Pong Mode

For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast mes-
sages separately from non-broadcast message data. Some applications may not include this requirement. The stan-
dard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the
device provides alternative strategies.
When the NOTICE2 bit in the “Remote Terminal Configuration Register (0x0017)” is 1 and the BCSTINV bit is 0,
ping-pong mode subaddresses (or mode codes) will buffer data words from broadcast and non-broadcast messages
separately. Broadcast message information and data are stored in the broadcast data buffer; non-broadcast message
information and data are stored in ping-pong buffers A and B. Since there is just one broadcast data buffer, the
NOTICE2 option treats broadcast messages as exceptions to normal ping-pong mode. When using the NOTICE2
option, broadcast data buffer servicing should have high priority, because a closely following broadcast message will
overwrite the broadcast buffer.
Every mode command and subaddress (including transmit subaddresses) must have an assigned valid
broadcast data pointer when NOTICE2 is asserted. When the NOTICE2 bit in the “Remote Terminal Configuration
Register (0x0017)” is 1 and the BCSTINV bit is 0, reception of a broadcast-transmit message updates the Message
Information and Time-Tag Words for the assigned broadcast buffer, but no data is transmitted on the bus. Since
broadcast-transmit is not allowed, multiple transmit subaddresses may share a common “bit bucket” broadcast buffer.
A two word buffer is sufficient for storing the MIW and Time-Tag Word.
When using ping-pong mode, there are two ways to handle broadcast messages, when broadcast is enabled:
Option 1 for Ping-Pong Mode Broadcast Messages:

This option isolates broadcast message information in the broadcast data buffer. If the descriptor Control Word IBR bit
and “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IBR bit are both set, reception of broadcast messages
generates an INT host interrupt. To prevent data loss, the broadcast data buffer must be serviced before the next
broadcast message occurs. Broadcast messages do not affect non-broadcast message ping-pong; the Control Word
DPB bit does not toggle after broadcast message completion.
Option 1 Setup: At initialization, host asserts the NOTICE2 bit in the “Remote Terminal Configuration Register
(0x0017)” and sets the IBR (Interrupt Broadcast Received) bit in descriptor Control Word(s). The IBR bit is asserted in
the “Remote Terminal (RT) Interrupt Enable Register (0x0012)”.
When a broadcast command is received, message information and data is stored in the broadcast data buffer and
an INT interrupt is generated. The host must read the Interrupt Log to determine the originating subaddress (or mode
code), then service the broadcast data buffer for that subaddress (or mode code) before another broadcast message
to the same subaddress (or mode code) arrives.
Option 2 for Ping-Pong Mode Broadcast Messages:

The second alternative stores both broadcast and non-broadcast message information in the ping-pong data buffers
A and B. IWA interrupts can signal arrival of any new message. The RT handles broadcast messages just like non-
broadcast messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages
during host buffer servicing. All messages toggle the Control Word DPB bit in message post-processing. For Notice II
compliance, separation of broadcast and non-broadcast data occurs within the host.
Option 2 Setup: At initialization, host negates the NOTICE2 bit in the “Remote Terminal Configuration Register
(0x0017)”. If IWA interrupts are used, the host asserts the descriptor Control Word IWA (Interrupt When Accessed) bit
14 and the corresponding bit is asserted in the “Remote Terminal (RT) Interrupt Enable Register (0x0012)”. Using this
option, the IBR interrupt is probably not used.
The host typically services the ping-pong data buffers A and B whenever a message is transacted. Using the setup
above, this occurs whenever the subaddress IWA interrupt generates an INT interrupt output for the host. The host
must read the Interrupt Log to determine the originating subaddress or mode code. The applicable data buffer is
indicated by the DPB bit in the Receive Control Word. The Message Information Word BCAST bit is asserted if the
message was broadcast.

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Data Word 32 0x1565 Device sets Control Word BCAST

bit (DPB bit remains static)
Data Words 2-31 0x1547 - 0x1564 IBR interrupt is generated
Assigned Data Word 1 0x1546

Subaddress
Broadcast Time-Tag Word BC 0x1545
Data Buffer Receive Message #3
Msg Info Word BC 0x1544
Broadcast, 32 Data Words
Data Word 32 0x1543 Device resets Control Word
DPB and BCAST bits
Data Words 2-31 0x1525 - 0x1542
Assigned Data Word 1 0x1524

Subaddress 0x1523
Time-Tag Word B
Data Buffer B
Receive Message #2
Msg Info Word B 0x1522
Non-Broadcast, 32 Data Words
Data Word 32 0x1521 Device resets Control Word
DPB bit
Data Words 2-31 0x1503 - 0x1520
Data Word 1 0x1502

Assigned
Subaddress Time-Tag Word A 0x1501
Data Buffer A Receive Message #1
Msg Info Word A 0x1500
Non-Broadcast, 32 Data Words
RAM
Address Message #4 also uses
this buffer, if not broadcast
Increasing
Memory
Address
B’cast Data Pointer Broadcast Data Pointer = 0x1544 start address in RAM
Data Pointer B Data Pointer B = 0x1522 Buffer B start address in RAM
Data Pointer A Data Pointer A = 0x1500 Buffer A start address in RAM
Control Word Control Word = 0x2010 Ping-Pong Mode, IBR Interrupt
Initialized Descriptor Values
Descriptor Block
for a
Receive Subaddress
Following reset (which resets Control Word DPB bit), the subaddress transacts 4 commands of 32 data words each.
The NOTICE 2 option is enabled so the device segregates data from broadcast and non-broadcast messages.
Message #3 is a broadcast command, while the other three messages are non-broadcast. Notice that the broadcast
message does not affect DPB bit, but the following message resets BCAST bit. The interspersed broadcast command
does not affect alternation between Buffer A and Buffer B.
Figure 16. Ping-Pong Buffer Mode Example for a Receive Subaddress

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17.4. Indexed Data Buffer Mode

Also called “single buffer mode”, indexed buffering is one method for storing message and time-tag information and
data associated with messages. Buffer mode is selected for each subaddress or mode code in the Descriptor Table
Control Words. Indexed mode is enabled when Control Word PPEN, CIR1EN and CIR2EN bits are all zero.
When a subaddress or mode command uses the indexed data buffer mode, its 4-word descriptor block in the Descrip-
tor Table is defined as follows:

Descriptor Word 2 Data Pointer A
Descriptor Word 3 INDX Index Word
Descriptor Word 4 Broadcast Data Pointer
As the name implies, all message information and data is stored in a single buffer, indexed by descriptor word Data
Pointer A. The descriptor Control Word DPB bit is “don’t care”. The host initializes the desired message count in de-
scriptor INDX word. During message processing, the device retrieves or stores data words from the address specified
by descriptor Data Pointer A, automatically incrementing the pointer address as words are read or stored. Data Pointer
A is updated during command post-processing with the current buffer address unless the message index count in de-
scriptor INDX (word 3 of descriptor block) decrements to zero upon completion of the message. Figure 17 is a general
illustration of indexed single buffer mode. Figure 18 shows a specific example.
To set up a terminal subaddress to buffer multiple messages, the host writes the desired index count (INDX) to subad-
dress descriptor word 3. The initial INDX value ranges from zero to 3FF hex (1023) messages. The device decrements
the INDX count each time an error-free message is transacted, and the data pointer is updated to the first memory
address to be used for the next message. If INDX decrements from one to zero and Control Word IXEQZ bit 15 is as-
serted, the IXEQZ bit is set in the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”. If the corresponding
bit in the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” is asserted, an INT interrupt is generated when
INDX decrements from one to zero.
INDX counter decrement does not occur if the command was illegalized or if INDX already equals zero. Once INDX
equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not up-
dated after successful message completion.
When using Index Mode with a non-zero INDX value, the host must remember the initial Data Pointer A address. The
Data Pointer A word is not automatically reinitialized to the buffer start address when INDX decrements from 1 to 0.
17.4.1. Single Message Mode

When Index Mode is initialized with an INDX value of zero, the subaddress or mode code is operating in “Single
Message Mode”. Here, the same data block is repeatedly over-read (for transmit data) or overwritten (for receive or
broadcast data). The DPA pointer is not updated at the end of each message. The chief advantage of single message
mode is simplicity. In comparison to other data buffering options, the single message buffer uses an absolute minimum
amount of memory space. The IXEQZ interrupt cannot be used for this scheme (INDX is always zero) but IWA inter-
rupts may be used. Single message mode is best suited to synchronous data transfer where the host processor can
reliably read or write new message data prior to the start of the next message to the same subaddress or mode code.
17.4.2. Broadcast Message Handling in Index Mode

For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast mes-
sages separately from non-broadcast message data. Some applications may not include this requirement. The stan-
dard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the
device supports alternative strategies.

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When the NOTICE2 bit is logic 1 in the “Remote Terminal Configuration Register (0x0017)”, broadcast message data
is stored in a broadcast data buffer assigned for the subaddress or mode command. Each subaddress or mode com-
mand must have an assigned, valid non-zero broadcast buffer address. Non-broadcast message data is stored in Data
Buffer A.
There are two ways to deal with broadcast messages in indexed buffer mode:
Option 1 for Index Mode Broadcast Messages:

The first alternative isolates broadcast message information in the broadcast data buffer. If the descriptor Control
Word IBR bit and “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IBR bit are both set, reception of broad-
cast messages generates an INT interrupt to the host. The broadcast data buffer must be processed before another
broadcast message arrives to prevent loss of data. Broadcast messages do not decrement the INDX register, and
Data Pointer A is not updated in message post-processing. This scheme may be well suited for Single Message Mode
(INDX = 0) when the host can reliably service either the broadcast data buffer or data buffer A before the next receive
message arrives for the same subaddress (or mode code).
Option 1 Setup: At initialization, host asserts NOTICE2 bit in the “Remote Terminal Configuration Register (0x0017)”
and sets the Control Word IBR (Interrupt Broadcast Received) bit for each index mode descriptor block. The IBR bit is
also asserted in the “Remote Terminal (RT) Interrupt Enable Register (0x0012)”.
When a broadcast command is received, message information and data are stored in the broadcast data buffer. If
descriptor Control Word IBR bit is set, an INT interrupt is generated. The host must read the Interrupt Log to determine
the originating subaddress (or mode code) then service the broadcast data buffer for that subaddress (or mode code)
before the next broadcast message to the same subaddress (or mode code) arrives.
Option 2 for Index Mode Broadcast Messages:

The second alternative stores both broadcast and non-broadcast message information in data buffer A. Optional IBR
interrupts can signal arrival of broadcast messages. The RT handles broadcast messages just like non-broadcast
messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages during host
buffer servicing. All messages decrement the INDX register and Data Pointer A is updated in message post-process-
ing. This scheme is compatible with Single Message Mode or conventional N-message indexing. For Notice II compli-
ance, separation of broadcast and non-broadcast data occurs within the host.
Option 2 Setup: At initialization, host negates the NOTICE2 bit in the “Remote Terminal Configuration Register
(0x0017)”. If broadcast interrupts are used, the Control Word IBR (Interrupt Broadcast Received) bit is asserted at
each desired index mode descriptor block. The IBR bit is also asserted in the “Remote Terminal (RT) Interrupt Enable
Using option 2, the host has several options for servicing data buffer A: (a) when INDX decrements from one to zero
(using the IXEQZ interrupt), (b) when a broadcast message occurs (using the IBR interrupt) or (c) when any message
arrives (using the IWA interrupt).

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Data Word N
Data Word(s)
Data Word 1
Increasing
Data Word N Memory Time-Tag Word
Next
Address
Data Word(s) Message Message Info Word
Data Word 1 Data Word N
Time-Tag Word Data Word(s)

Broadcast
Message Info Word B’cast Data Pointer Data Word 1
Message
(if NOTICE2 INDX Index Count Time-Tag Word
Subaddress is asserted)
Current
Buffer Space Data Pointer A Message Info Word
Message
for Broadcast
(optional) Control Word Data Word N
Data Word(s)
Descriptor Block
for Subaddress Data Word 1
Time-Tag Word
Preceding
Message Message Info Word
Assigned
Memory Address for the Applicable Subaddress
Subaddress Block is Derived From Buffer Space
Upon successful message completion, if non-zero the INDX count in Descriptor Word 3 is decremented.
If decremented result is non-zero, Data Pointer A is adjusted so next message is stored above
just-completed message. If decremented INDX is zero, Data Pointer A remains static
and IXEQZ interrupt occurs if enabled in Control Word.
Figure 17. Illustration of Indexed Buffer Mode

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For Message #2,

Index decrements to zero.
Data Pointer A = 0x1505 (static)
IXEQZ Interrupt is generated
Data Word 4 0x150A
Data Word 3 0x1509 For Message #3 and beyond,

the data buffer is overwritten.
Data Word 2 0x1508 Index remains zero (static)
Data Pointer A = 0x1505 (static)
Data Word 1 0x1507 and no IXEQZ interrupt occurs.
Time-Tag Word 1 0x1506
Messages #2, #3, etc
Receive 4 Words Msg Info Word 1 0x1505
Index decrements to one
Data Word 3 0x1504
Data Pointer A = 0x1505
Data Word 2 0x1503
Data Word 1 0x1502

Messages #1
Receive 3 Words Msg Info Word 1 0x1500 Index equals two
RAM
Assigned Address
Receive
Subaddress
Buffer
Increasing
Memory
Address
B’cast Data Pointer Broadcast Data Pointer = 0xXXXX Don’t Care
INDX Index Count Index = 0x0002 Initialize index for 2 messages
Data Pointer A Data Pointer A = 0x1500 Buffer Start Address in RAM
Control Word Control Word = 0x8000 Index Mode, IXEQZ Interrupt

Descriptor Block
for a
Receive Subaddress
Figure 18. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled)

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17.5. Circular Buffer Mode 1

The device offers two circular data buffer modes as alternatives to ping-pong and indexed buffering. These circular
buffer options only apply for subaddress commands, not mode code commands. Circular buffering simplifies software
servicing of the remote terminal when implementing bulk data transfers. A circular buffer mode can be selected for
any subaddress by properly initializing its descriptor Control Word. Circular Buffer Mode 1 is selected when descriptor
Control Word PPEN and CIR2EN bits are both 0, and the CIR1EN bit is logic 1.
When a subaddress uses circular buffer mode 1, its four word block in the Descriptor Table is defined as follows:

Descriptor Word 2 SA (Buffer Start Address)
Descriptor Word 3 CA (Buffer Current Address)
Descriptor Word 4 EA (Buffer End Address)
Figure 19 provides a generalized illustration of Circular Buffer Mode 1, while Figure 20 shows a specific example.
Circular Buffer Mode 1 uses a single user-defined buffer that merges all transmit or receive data, along with message
information. Two words (Message Information and Time-Tag) are stored at the beginning of the block for each mes-
sage, followed by the message data word(s). The Mode 1 buffer pointers roll over (are reset to their base addresses)
when the allocated data buffer memory is full.
For each valid receive message, the device enters a Message Information word, Time-Tag word and data word(s)
into the circular receive buffer. For each valid transmit message, the device enters a Message Information word and
a Time-Tag word into reserved memory locations within the circular transmit buffer. The device automatically controls
the wrap around of circular buffers.
Two pointers define circular buffer length: start of buffer (lowest address) and end of buffer (highest address). User
specifies the start of buffer (SA) by writing the lowest address value into the second word of a unique subaddress
descriptor block. The user defines the end of the buffer (EA) by writing the highest address value to the fourth word of
that unique descriptor block. Both SA and EA remain static during message processing. The third word in the descrip-
tor block identifies the current address CA (i.e., last accessed address plus one). The circular buffer wraps to the start
address after completing a message that results in CA being greater than or equal to EA. If CA increments past EA
during message processing, the device will access memory addresses greater than the EA value. Reserve 33 address
locations past the EA address to accommodate a worst-case 32 data word message with a record starting at address
= EA minus 1.
Each receive subaddress and transmit subaddress may have a unique circular buffer assignment. The RT decodes the
command word T/R bit, subaddress field and word count / mode code field to select the unique command descriptor
block containing the Control Word, SA pointer, CA pointer and EA pointer.
For receive messages, the device stores the Message Information word to the address specified by CA, the Time-Tag
word into CA+1 and the data into the next “N” locations starting with CA+2. For transmit messages, the device stores
the Message Information word to the address specified by CA and the Time-Tag word into CA+1. Retrieval of data for
transmission starts at address CA+2. When entering multiple transmit command data packets into the circular buffer,
delimit each data packet with two reserved memory locations. The device stores the Message Information word and
Time-Tag word into the reserved locations when processing the command.
Message processing for all commands begins with the device reading the unique descriptor block for the subaddress
or mode code specified by the T/R bit, subaddress and word count fields in the received command word.
For receive messages, the device stores “N” received data words in the circular data buffer. The first data word re-
ceived is stored at the location specified by the CA pointer +2. After message completion, the device stores the Mes-
sage Information word and Time-Tag words to addresses CA and CA+1 respectively. If no errors were detected, the

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device updates descriptor CA register. If the next address location (last stored data word +1) is less than or equal to
EA, CA is updated to (last stored address +1). If the next address location (last stored data word +1) is greater than
EA, the data buffer is full (or empty); CA is updated to the SA value. If descriptor Control Word IXEQZ bit is asserted
(and if “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ bit is asserted) the device generates an
interrupt to indicate full receive buffer by asserting the INT interrupt output.
Although all messages store Message Information and Time-Tag words, no data is stored if the message ended with
error, or if the Busy status bit was set or if the command was illegal (example: illegalized word count). Such messages
do not update CA, so the next message overwrites the same buffer space.
For transmit commands, the device begins transmission of data retrieving the first data word stored at address CA+2.
(Reminder: addresses CA and CA+1 are reserved for the Message Information and Time-Tag words.) When message
processing is complete, the device writes the Message Information and Time-Tag words into the buffer. If no errors
were detected, the device updates descriptor CA register. If the next address location (last retrieved data word +1) is
less than or equal to EA, CA is updated to (last retrieved address +1). If the next address location (last retrieved data
word +1) is greater than EA, the transmit data buffer is empty; CA is updated to the SA value. If the descriptor Control
Word IXEQZ bit is asserted (and if the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ bit is as-
serted) the device indicates “transmit buffer empty” by asserting the INT interrupt output.
Device hardware does not segregate broadcast and non-broadcast data for this circular buffer mode, even when the
NOTICE2 bit is set in the “Remote Terminal Configuration Register (0x0017)”. Data words from broadcast receive
commands are stored in the same buffer with data from non-broadcast receive commands. However Notice 2 for MIL-
STD-1553 does not state where data segregation should occur. It is acceptable for the host to separate broadcast
and non-broadcast data when offloading the circular buffer. To choose this option, set bit 3 in “Extended Configuration
Register (0x004D)”. This enables the BCAST (broadcast status) bit in the Message Information Word stored for each
message. This flag reflects broadcast or non-broadcast status for each message in the buffer.
For transmit subaddresses using Circular Buffer Mode 1, occurrences of broadcast-transmit commands to RT31 do
not result in bus transmission. However these messages update the Message Information Word addressed by the
Current Address (CA) pointer (and following Time-Tag Word) but afterwards, the CA pointer remains unchanged. The
next transmit command to the same subaddress, whether broadcast or not, overwrites the Message Information and
Time-Tag Word locations written by the previous broadcast transmit command.

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End
Data Word N Address
Data Word(s)
Data Word 1
Time-Tag Word
Last Message
in Data Block Message Info Word
More Messages
in Data Block
Data Word N
Data Word(s)
Data Word 1
End Address Time-Tag Word

Current Current
Current Address Message Info Word
Message Address
Start Address More Messages
in Data Block
Control Word
Descriptor Block Data Word N

for Subaddress
Data Word(s)
Data Word 1
Time-Tag Word
Memory Address for the Applicable
FirstMessage Start
Subaddress Block is Derived From Message Info Word Address
in Data Block
Assigned
Subaddress
Increasing
Circular Buffer
Memory
Address
Descriptor block is initialized so Current Address equals buffer Start Address. After each successful
message transaction, Current Address is adjusted to point past last data word accessed. If adjusted
Current Address points past End Address, the Current Address is reinitialized to match Start Address
and an optional interrupt is generated to notify host that the pre-determined data block
was fully transacted.
Figure 19. Illustration of Circular Buffer Mode 1

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Data Word 32 0x1565 (1 + Data Word 32 address) ≥ End Address.

Device updates Current Address to
Data Words 2-31 0x1547 - 0x1564 equal the Start Address, 0x1500.
Buffer End IXEQZ interrupt is generated.
Data Word 1 0x1546
Address
Receive Message #3
Msg Info Word 3 0x1544
32 Data Words
Data Word 32 0x1543 (1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x1544.
Data Words 2-31 0x1525 - 0x1542
Data Word 1 0x1524

Receive Message #2
32 Data Words
Data Word 32 0x1521 (1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x1522.
Data Words 2-31 0x1503 - 0x1520
Data Word 1 0x1502

Buffer Start Receive Message #1
Address 32 Data Words
RAM
Address Unless serviced by host
after Message #3 Interrupt,
Message #4 will overwrite
buffer, starting at 0x1500
Increasing End Address End Address = 0x1545 Buffer end address in RAM
Memory Current Address Current Address = 0x1500 Buffer current address in RAM
Address
Start Address Start Address = 0x1500 Buffer start address in RAM
Control Word Control Word = 0x8001 Circular Mode 1, IXEQZ Interrupt

Descriptor Block
for a
Receive Subaddress
Unlike Indexed mode, Data Block completion is based on Buffer Full / Buffer Empty, not number of messages.
Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior.
The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss.
Figure 20. Circular Buffer Mode 1 Example for a Receive Subaddress

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17.6. Circular Buffer Mode 2

Circular Buffer Mode 2 segregates message data and message information in separate host-defined buffers. Separat-
ing data from message information simplifies the host software that loads or unloads the data to or from the buffer.
After a predetermined number of messages has been transacted, buffer address pointers for data and message infor-
mation are automatically reset to their base addresses. Figure 21 is a generalized illustration of Circular Buffer Mode
2, while Figure 22 shows a specific example.
Circular Buffer Mode 2 is selected when the Control Word PPEN bit is zero and the CIR2EN bit is logic 1. When the
CIR2EN bit is high, the CIR1EN bit is don’t care. The descriptor Control Word DPB bit is not used.
Any receive subaddress using circular buffer mode 2 has two circular buffers: a data storage buffer and a message
information buffer. A separate buffer pair may be used for transmit commands to the same subaddress, if it also uses
circular buffer mode 2. Each transmit and receive subaddress using circular buffer mode 2 may have unique data
buffer and message info buffer assignments. Careful management (involving the bus controller) may allow buffer shar-
ing, as long as multiple message sequences to a given subaddress are not interrupted by messages to other subad-
dresses that use the same buffer space.
When a subaddress uses circular buffer mode 2, its Descriptor Table 4-word block is defined as follows:

Descriptor Word 2 SA (Buffer Start Address)
Descriptor Word 3 CA (Buffer Current Address)
Descriptor Word 4 MIBA (Message Info Buffer Addr)
words are stored at addresses N+2 and N+3. The first word in the descriptor block is the Control Word. The second
and third words in the descriptor are the Start Address (SA) and Current Address (CA) pointers. The Message Informa-
tion Buffer Address (MIBA) points to the storage location for the Message Information Word from the next occurring
message.
Each time a message is completed, the device writes a new Message Information Word and Time-Tag Word in the
MIB (Message Information Buffer) at the MIBA address and following location, respectively. The MIBA pointer is not
updated if message error occurred, if the Busy status bit was set, or if the command was illegalized (for example an
illegal word count expressed in the command word.) For these situations, the Message Information and Time-Tag
words are still written, but MIB updates for the following message will overwrite the just-written Message Information
and Time-Tag word addresses.
For error-free receive messages, received data words are stored in the data buffer after message completion, starting
at the CA address value. The CA value is then updated for next-message readiness.
After writing the two MIB words, the device updates the MIBA value to show the buffer address to be used by the next
message. Until the predetermined number of error-free messages is transacted, the MIBA value is double-increment-
ed at each update. Before updating the MIBA in Descriptor Word 4, the pre-existing MIBA value is incremented once
then checked for ‘full count,” occurring when all N low-order address bits initialized to zero (explained below) become
N “one” bits. Full count means the predetermined number of successful messages was completed. When this occurs,
the CA and MIB pointers are automatically written to their initialized values by the device.
To preserve data integrity, the TRXDB bit should be set in the “Remote Terminal Configuration Register (0x0017)”
to avoid storing incomplete data from messages resulting in error. With TRXDB asserted, the host is not bothered
by message retries caused by errors. The Buffer Empty/Full interrupt (if enabled) is generated only upon successful
transaction of the entire N-message data block.
To initialize Circular Buffer Mode 2, the host must know the number of messages to be transacted, always a power of
two: 1, 2, 4, 8, 16, 32, 64 or 128 messages. The host writes descriptor Control Word bits 7:4 with an encoded 4-bit
value to set the fixed number of messages to be transacted. This is illustrated in Table 13. The host initializes the de-

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scriptor block MIBA pointer with a Message Information Buffer starting address. Because the MIB stores two words for
each message, the allocated MIB space should equal 2x the number of messages.
The initially-loaded MIB base address value is restricted. Some lower bits of the starting address must be zero so the
device can restore the MIBA pointer to the initial MIB base address after the predetermined message count is transact-
ed. As illustrated in Table 13, the required number of logic-0 bits depends on the message count. Initializing the MIBA
base address with more trailing zeros than indicated is acceptable; initializing less trailing zeros will cause malfunction.
Allocated space in the data buffer (see column 3, Table 13) assumes each message has the maximum 32 data words.
If messages contain less than 32 words, the data buffer size can be reduced. Since Circular Buffer Mode 2 counts
messages, values in all remaining Table 13 columns remain valid when message word count is reduced.
The host may read the MIBA value to determine the number of messages that have occurred since initialization. By
reading the initially-zeroed lower bits of the MIB Address, the host may determine the number of the next occurring
message.
From Table 13, a block of 128 messages requires 8 trailing zeros in the initial MIBA address, for example, 0x0F00.
After each message is completed, the MIBA value is updated (0x0F02, 0x0F04, etc.) The device detects message
block completion when all required initially-zero trailing address bits equal 1 after MIBA is incremented once. In our
example, MIBA would increment from 0x0FFE to 0x0FFF. When “full count” occurs, the device updates MIBA to the
original value (e.g., 0x0F00) and copies the SA starting address value to CA current address register, ready for buffer
service by the host. The device optionally generates a “buffer empty-full” interrupt for the host when block transfer is
completed.
During block transfer, the host can read the MIBA value to determine the number of additional messages needed be-
fore the N-message data block is complete.
Message processing for all commands begins with the RT reading the unique descriptor block for the subaddress
specified by the T/R bit, subaddress and word count fields in the received command word.
Table 13. Circular Buffer Mode 2 (Initialization factors based on message block size)
Control Word Required Data Required Initial Binary MIBA Value,

Number of
Bits 7:4 Space if 32 MIB Space, 2 Showing the Required Leading
Messages
CIR2ZN Field Words / Msg Words / Msg and Trailing Zeros
2 0010 (2) 64 4 000xxxxxxxxxxx00
4 0011 (3) 128 8 000xxxxxxxxxx000
8 0100 (4) 256 16 000xxxxxxxxx0000
16 0101 (5) 512 32 000xxxxxxxx00000
32 0110 (6) 1,024 64 000xxxxxxx000000
64 0111 (7) 2,048 128 000xxxxxx0000000
128 1000 (8) 4,096 256 000xxxxx00000000

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For receive subaddresses using Circular Buffer Mode 2, the device stores received data words in the circular data
buffer. The first data word received for each message is stored at the location indicated by the CA pointer. After
the correct number of words is received (as specified in the command word) the device writes Message Information
and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address and MIBA
Message Information pointers for next-message readiness. If the predetermined total number of messages has not
yet been transacted, MIBA points to the next location in the message information buffer and CA points to the next
location in the data buffer. If the completed message is the last message in the block, the CA current (data) address
and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4 tell the
device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the “Remote
Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ bit is asserted) the device generates a Buffer Full / Empty
interrupt, asserting the INT interrupt output.
For transmit subaddresses using Circular Buffer Mode 2, the device transmits data from the assigned RAM buffer,
starting at the location specified by the CA pointer. The first data word transmitted is stored at the location specified by
the CA pointer. After all data words are transmitted (as specified in the command word) the device writes Message In-
formation and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address and
MIBA Message Information pointers for next-message readiness. If the predetermined total number of messages has
not yet been transacted, MIBA points to the next location in the message information buffer and CA points to the next
location in the data buffer. If the completed message is the last message in the block, the CA current (data) address
and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4 tell the
device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the “Remote
Terminal (RT) Interrupt Enable Register (0x0012)” IXEQZ bit is asserted) the device generates a Buffer Full / Empty
interrupt, asserting the INT interrupt output.
Device hardware does not segregate broadcast and non-broadcast data for this circular buffer mode, even when the
NOTICE2 bit is set in the “Remote Terminal Configuration Register (0x0017)”. Data words from broadcast receive
commands are stored in the same buffer with data from non-broadcast receive commands. However Notice 2 for MIL-
STD-1553 does not state where data segregation should occur. It is acceptable for the host to separate broadcast
and non-broadcast data when offloading the circular buffer. To choose this option, set bit 3 in “Extended Configuration
Register (0x004D)”. This enables the BCAST (broadcast status) bit in the Message Information Word stored for each
message. This flag reflects broadcast or non-broadcast status for each message in the buffer.
For transmit subaddresses using Circular Buffer Mode 2, occurrences of broadcast-transmit commands to RT31 do
not result in bus transmission. However these messages update the Message Information Word addressed by the
Message Information Block (MIB) pointer (and the following Time-Tag Word) but afterwards, the MIB and CA pointers
remain unchanged. The next transmit command to the same subaddress, whether broadcast or not, overwrites the
Message Information and Time-Tag Word locations written by the previous broadcast transmit command.

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Data Word N
Time-Tag Word Last Message Data Word(s)

Last Message
in Data Block in Data Block
Message Info Word Increasing Data Word 1
Memory
Address
Time-Tag Word Data Word N

Current
Message Info Word MIB Address Data Word(s)
Message
Current Current
Current Address Data Word 1
Message Address
Start Address
Time-Tag Word Control Word
Message Info Word Data Word N
FirstMessage Descriptor Block
in Data Block for Subaddress Data Word(s)
Assigned
Start
Subaddress FirstMessage Data Word 1
Address
Message Info Buffer in Data Block
(MIB) Assigned
Subaddress
Memory Address for the Applicable Circular Data
Subaddress Block is Derived From Buffer
Segregated storage for data and message information simplifies host loading / offloading of buffered data.
Descriptor MIB Address tracks number of messages. Full count occurs when N initialized 0-bits become N 1-bits.
When full number of messages in block is transacted, an optional interrupt is generated to notify host.
Figure 21. Illustration of Circular Buffer Mode 2

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Msg Count increments to 4,

full count, data block complete.
Device updates CA to equal
buffer Start Address 0x1500.
Device updates MIBA to equal
Data Word 32 0x157F MIB Start Address 0x1600.
Data Words 2-31 IXEQZ interrupt is generated.
0x1561 - 0x157E
Receive Message #4
Data Word 1 0x1560 32 Data Words
Data Word 32 0x155F Msg Count increments to 3.
Device updates CA to 0x1560
Time-Tag Word 4 0x1607 Data Words 2-31 0x1541 - 0x155E and updates MIBA to 0x1606.
Receive Message #3
Msg Info Word 4 0x1606 Data Word 1 0x1540
32 Data Words
Time-Tag Word 3 0x1605 Data Word 32 0x153F Msg Count increments to 2.
Msg Info Word 3 0x1604 Data Words 2-31 0x1521 - 0x153E and updates MIBA to 0x1604.
Receive Message #2
Time-Tag Word 2 0x1603 Data Word 1 0x1520
32 Data Words
Msg Info Word 2 0x1602 Data Word 32 0x151F Msg Count increments to 1.
Time-Tag Word 1 0x1601 Data Words 2-31 0x1501 - 0x151E and updates MIBA to 0x1602.
Msg Info Word 1 0x1600 0x1500 Receive Message #1

Data Word 1
32 Data Words
RAM RAM
Address Address
Message Data Word
Information Buffer
Buffer (MIB)
MIB Address MIB Address = 0x1600 MIB start address in RAM
Current Address Current Address = 0x1500 Buffer current address in RAM
Increasing Start Address Start Address = 0x1500 Buffer start address in RAM
Memory
Address Control Word Control Word = 0x8042 Circular Mode 2, 4 messages, IXEQZ Interrupt
Descriptor Block
for a
Receive Subaddress
Data Block completion is based on number of messages, not Buffer Full or Buffer Empty.
Example is set to successfully transact four 32 data word receive messages, then generate IXEQZ interrupt for host.
The data buffer requires minimal processing by host because message information words are stored separately in MIB.
Figure 22. Circular Buffer Mode 2 Example for a Receive Subaddress

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18. REMOTE TERMINAL MODE COMMAND PROCESSING
18.1. General Considerations

The device provides decoding for all mode code combinations, consistent with MIL-STD-1553B requirements. Several
mode command options are provided to suit any application requirement:
In the “Remote Terminal Configuration Register (0x0017)”, the option bit UMCINV (Undefined Mode Codes Invalid)
globally defines whether undefined mode code commands are treated as valid (default) or invalid commands. This bit
applies only to the following 22 mode code commands that are undefined in MIL-STD-1553B:

Mode Codes16, 18 and19 withT/R bit = 0
Mode Codes 17, 20 and 21 with T/R bit = 1
If the UMCINV bit is low (default after MR reset) undefined mode code commands are considered valid and RT re-
sponse is based on individual mode command settings in the Illegalization Table: If the command’s illegalization table
bit equals 0, the mode command is legal; the RT responds “in form” and updates status. If the command’s illegalization
table bit equals 1 the mode command is illegal, the RT asserts Message Error status and (if non-broadcast) transmits
only its Status Word without associated data word. Table 14 describes explicit terminal response for each mode code
value and command T/R bit state, based on various option settings.
If UMCINV is asserted, the 22 undefined mode code commands are treated as invalid: There is no terminal recognition
of the command. No command response occurs and status remains unchanged for the benefit of following “transmit
status” or “transmit last command” mode commands.
If UMCINV is low, the device determines legal vs. illegal status of commands from the Illegalization Table. If the termi-
nal does not use illegal command detection, the Illegalization Table should be left in its post-reset default state, all val-
ues equal logic 0. In this case, the terminal provides “in form” response to all valid commands. The terminal responds
with clear status and a transmitted mode data word for mode commands 16-31 with T/R bit equals 1. Assigned data
buffer locations can be initialized to provide predictable “in form” responses for all transmit mode codes 16-31. (If UM-
CINV is asserted, the terminal will not respond or update status for received mode codes 17, 20 and 21 with T/R = 1.)
To use illegal command detection, the host modifies the Illegalization Table to make illegal any combination subad-
dress and mode code commands. This may include undefined mode codes, reserved mode codes, and/or mode
codes not implemented in the application.
18.2. Mode Command Interrupts

For mode commands, interrupt generation is programmed by the top three bits in the descriptor table Control Word.
Notice that broadcast-transmit interrupts can be enabled for mode code values in the range of 0 - 15, but broadcast-
transmit mode codes 16 - 31 are not allowed. When a mode command is received and the IWA interrupt bit is asserted
in its descriptor Control Word, that command will generate a host interrupt if the IWA bit is high in the “Remote Termi-
nal (RT) Interrupt Enable Register (0x0012)”. The IWA bit is asserted in the “Remote Terminal (RT) Pending Interrupt
Register (0x0009)” and the INT interrupt output is asserted.
Before INT interrupt assertion, the device updates the Interrupt Log buffer, writing a new IIW Interrupt Information
Word and a new IAW Interrupt Address Word. The IWA (interrupt when accessed) bit is asserted in the new IIW to
indicate interrupt type. The IAW contains the Descriptor Table address for the mode command’s Control Word, based
on mode code value and command word T/R bit state. The host reads the IAW to determine the command that caused
the interrupt.

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18.3. Mode Command Data Words

Mode commands having mode code values from 0 through 15 (decimal) do not have an associated data word. These
are received as Command Word only, never having a contiguous data word. The terminal response to valid mode com-
mands 0-15 always consists of Status Word only, assuming command was not broadcast.
Mode commands having mode code values from 16 through 31 (decimal) always have an associated data word. When
the command word T/R bit equals 0, the terminal receives a data word, contiguously following the Command Word.
When valid legal mode commands 16-31 arrive with T/R bit equal to 1, the terminal responds by transmitting its status
word with a single data word.
When the SMCP option bit in the “Remote Terminal Configuration Register (0x0017)” is zero, individual data words for
mode codes 16-31 decimal are stored in an indexed or ping-pong buffer assigned by the mode command’s Descriptor
Table entry. Circular buffer methods are not available for mode code commands.
When the SMCP option bit in the “Remote Terminal Configuration Register (0x0017)” is asserted, individual data words
for mode codes 16-31 decimal are stored within the Descriptor Table itself. This is explained next.
Table 14. Mode Code Command Summary
Mode Code
Command Associated Broadcast See
MIL-STD-1553 Defined Function
T/R bit Data Word Allowed Note
Binary Dec.
00000 0
Undefined mode commands 0 - 15 when
0 to to No No (1)
T/R bit = 0
01111 15
1 00000 0 Dynamic Bus Control No No
1 00001 1 Synchronize (without data) No Yes
1 00010 2 Transmit Status Word No No
1 00011 3 Initiate Self-Test No Yes
1 00100 4 Transmitter Shutdown No Yes
1 00101 5 Override Transmitter Shutdown No Yes
1 00110 6 Inhibit Terminal Flag No Yes
1 00111 7 Override Inhibit Terminal Flag No Yes
1 01000 8 Reset Remote Terminal No Yes
01001 9
Reserved Mode Commands 9 - 15 with
1 to to No Yes (2)
T/R bit = 1
01111 15
0 10000 16 Undefined Mode Command Yes No (1)
1 10000 16 Transmit Vector Word Yes No
0 10001 17 Synchronize With Data Yes Yes

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Mode Code
Command Associated Broadcast See
MIL-STD-1553 Defined Function
T/R bit Data Word Allowed Note
Binary Dec.
1 10010 18 Transmit Last Command Yes No
1 10011 19 Transmit Built-In Test Word Yes No
0 10100 20 Selected Transmitter Shutdown Yes Yes
0 10101 21 Override Selected Transmitter Shutdown Yes Yes
01001 22
0 to to Yes Yes (2)
T/R bit = 0
01111 31
01001 22
1 to to Yes No (2)
T/R bit = 1
01111 31
NOTES:
1. The 22 undefined mode commands can be rendered invalid by setting the UMCINV (undefined mode codes in-
valid) option bit in “Remote Terminal Configuration Register (0x0017)”. If UMCINV is asserted, there is no recogni-
tion of the undefined command by the terminal. If UMCINV is zero, the commands are considered valid. Terminal
response when UMCINV equals 0 is wholly determined by the Illegalization Table:
a. If a command’s bit in the Illegalization Table equals zero, the terminal responds “in form” with Clear Status.
Mode commands 17, 20 and 21 are undefined when T/R bit equals one, but will transmit a contiguous data
word. Mode commands 16, 18 or 19 are undefined when T/R bit equals 0, but will receive a contiguous data
word.
b. If a command’s bit in the Illegalization Table equals one, the command is considered illegal. The Message
Error (ME) status bit is asserted and the terminal transmits status without data word. Illegal mode commands
16-31 will not transmit or receive a mode data word.
2. Response to the reserved mode commands is fully defined by Illegalization Table settings. As described in (a) and
(b) above, the terminal illegalizes any reserved mode command having Illegalization Table bit equal to 1, and re-
sponds “in form” when the Table bit equals zero. The “in form” response for reserved mode commands 16 through
31 transacts a received or transmitted data word.

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18.4. Standard Mode Command Processing

Data buffer options for mode commands differ from buffer options for subaddress commands. Mode commands can
use ping-pong buffering or indexed buffering. When mode commands use indexed buffers, “single message mode”
(INDX = 0) is recommended. When using indexed or ping-pong buffers for mode commands:
• For mode commands without associated data word (mode codes 0-15 decimal), only the Message Information
and Time-Tag words are updated in the mode command’s assigned data buffer in RAM.
• For mode commands 16-31 (decimal) that receive a data word, indexed and ping-pong buffer methods copy the
received mode data word to the mode command’s assigned data buffer in shared RAM, after the message is
transacted. The Message Information and Time-Tag words are also updated.
• For most mode commands 16-31 (decimal) that transmit a data word, the device reads the data word for transmit
from the buffer location assigned in the Descriptor Table. Exceptions occur for MC18 “transmit last command”
and for MC19 “transmit BIT word.” The MC18 data word is automatically provided by the device, based on recent
command transactions. The MC19 data word comes from register 0x1E or 0x1F, selected by the ALTBITW option
in the “Remote Terminal Configuration Register (0x0017)”. For both MC18 and MC19, the transmitted data word
is automatically recorded in the mode command’s assigned data buffer in RAM, after message completion. The
Message Information and Time-Tag words are also updated.
18.5. Simplified Mode Command Processing

Mode commands have a buffer alternative that is unavailable for subaddress commands. The SMCP bit in the “Remote
Terminal Configuration Register (0x0017)” selects Simplified Mode Command Processing, a global option applying to
all mode commands. When the SMCP bit is high, mode command descriptor blocks (in the Descriptor Table) do not
contain data pointers to reserved buffers elsewhere in the shared RAM. Instead, each 4-word descriptor block itself
contains the message information word, the time-tag word and the data from the most recent occurrence of each mode
command:
Descriptor Word 1 Mode Command Control Word

Descriptor Word 2 Message Information Word
Descriptor Word 3 Time-Tag Word
Descriptor Word 4 Mode Data Word
Descriptor Word 1 contains the receive or transmit mode command Control Word. When SMCP is used, just two
Control Word bits are used: DBAC (descriptor block accessed) and BCAST (broadcast).
When SMCP is enabled, the host need not initialize the mode code command segments in the Descriptor Table. When
Simplified Mode Command Processing is selected, the host does not write Descriptor Words 2-3 in the Descriptor
Table entries for mode commands. For mode code values 0 to 15 decimal, the Descriptor Word 4 serves no function
because these mode codes do not have an associated data word. For transmit mode code values 16 to 31, the host
may initialize Descriptor Word 4. The default transmit value is 0x0000. Mode command MC16 “transmit vector word”
is one of the three defined mode commands that transmit a data word: MC16, MC18 and MC19. Its Descriptor Word 4
should be initialized if a value other than 0x0000 is needed. MC18 and MC19 are discussed below.
• For mode commands without associated data word (mode codes 0-15 decimal), Simplified Mode Command
Processing updates the Message Information and Time-Tag words in Descriptor Words 2 and 3, and Descriptor
Word 1 (bits 9,11). For these commands, SMCP does not update Descriptor Word 4, which may be non-zero if
written earlier by the host.
• For receive mode commands 16-31 (decimal) that receive a data word, Simplified Mode Command Processing
copies the received mode data word to Descriptor Word 4. The Message Information and Time-Tag words in
Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated.
• For most transmit mode codes 16-31 (decimal), the device reads the data word for transmission from each
command’s Descriptor Word 4. Exceptions occur for MC18 “transmit last command” and for MC19 “transmit
built-in test word”. The MC18 data word is automatically provided, based on the last command transacted. The

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MC19 data word comes from register 0x1E or 0x1F, selected by the ALTBITW option in the “Remote Terminal
Configuration Register (0x0017)”. For MC18 and MC19, the transmitted data value is automatically copied to the
mode command’s Descriptor Word 4 after message completion. The Message Information and Time-Tag words
in Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated.
“Appendix: RT messages responses, options & exceptions” on page 223 shows terminal response to all possible
subaddress and mode code command combinations. The table summarizes terminal response for the full range of
message conditions, including errors, incomplete messages, etc. The table explicitly describes terminal response and
impact on terminal Status Word, Descriptor Control Words and data buffer Message Information Words. The table
includes effects for all pertinent setup options and identifies all interrupt options available. Bold text blocks indicate
error-free messages or “in form” Clear Status responses when the terminal is not using “illegal command detection”.

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19. SERIAL EEPROM PROGRAMMING UTILITY

The HI-6138 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-initialization
events. The device copies host-configured registers and RAM (configuration tables and possibly data buffers) to serial
EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in SPI modes 0 or 3 and have 128-byte pages. The serial SPI
data is clocked at 8.3 MHz SCK frequency. A 2K x 8 EEPROM can restore the lower 1K x 16 device address space. A
16K x 8 EEPROM retains the entire 8K x 16 register/RAM address space. The external EEPROM must support as a
minimum the instruction set outlined in Table 15 below.
Table 15. External EEPROM minimum instruction set.
Mnemonic Holt SPI OPCODE Function

WRITE 0x02 Write Data to Memory Array
READ 0x03 Read Data from Memory Array
RDSR 0x05 Read Status Register
WREN 0x06 Set Write Enable Latch
19.1. Writing the Auto-Initialization EEPROM

A deliberate series of events initiates copy of data from registers and RAM to serial EEPROM. This reduces the likelihood
of accidental EEPROM overwrites. Note: The RT address must have correct (odd) parity before EEPROM read or
write can occur. The following series of events must occur to initiate programming:
1. Using a fresh host initialization immediately following MR master reset as the basis for EEPROM copy
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN, TXINHA and TXINHB pins in logic
0 state, apply MR master reset and wait for READY output assertion. Verify that the IRQ interrupt output does
not pulse low at READY assertion, indicating likely RT address parity error at the RTA4:0 and RTAP pins. Using
known good parameters, the host initializes device registers, the RAM descriptor table and transmit data buffers
(if necessary).
• If auto-initialization will be used to configure the Bus Controller, the BCENA bit 12 in “Master Configuration
Register 1 (0x0000)” should be logic 1, but BCSTRT register bit 13 must remain in the post-reset logic 0 state.
• If auto-initialization will be used to configure the Bus Monitor, the MTENA bit 8 in “Master Configuration Register
1 (0x0000)” should be logic 0. Until EEPROM programming is complete, the terminal should be disconnected
from MIL-STD-1553 buses (or other measures taken) to prevent bus activity detection by the monitor.
• If auto-initialization will be used to configure the Remote Terminal, the RTENA bit 6 in “Master Configuration
Register 1 (0x0000)” should be logic 1, but RTSTEX register bit 4 must remain in the post-reset logic 0 state.
Skip to step 3.
2. Using the existing EEPROM configuration as the baseline for a new EEPROM configuration
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN pin in logic 1 state and the TXINHA
and TXINHB pins in logic 0 state, apply and release MR master reset and wait for READY output assertion. Verify
that the IRQ output does not pulse low (or go and remain low) at READY assertion. Confirm that the EECKE and
RAMIF bits are logic 0 in the “Master Status and Reset Register (0x0001)”. If register bit 4 (RTSTEX) in “Master
Configuration Register 1 (0x0000)” was set by auto-initialization, reset it now. Modify register and RAM values to
reflect the new changes.

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3. Do not assert BCSTRT bit 13 in “Master Configuration Register 1 (0x0000)”.
EEPROM programming is locked out at step 4 for the following conditions:

• ACTIVE output pin assertion occurs after MR master reset.
• RAMIF / EECKE assertion in “Master Status and Reset Register (0x0001)”.
• RTSTEX bit 4 or MTENA bit 8 is set in “Master Configuration Register 1 (0x0000)”.
4. For EEPROM configuration, the host must use the Memory Address Pointer 1 (MAP1) Register. RAM address
0x0051 is first written to the selected MAP1 register, followed by the host writing a 2-part “unlock code”. After
writing the first unlock code the MAP register must be rewritten to address 0x0051 before the second
unlock code is written. The unlock code value selectively enables any combination of terminal devices (BC, MT,
RT) to automatically start execution, after subsequent auto-initialization sequences are performed. Programmed
here, the same combination of terminal devices is simultaneously enabled after every initialization. Unlock words
are encoded as shown in Table 16.
Warning: Do not write to registers during the EEPROM programming process.
Table 16. Terminal Unlock Word Encoding
Word 1 Word 2 Initialize RT 2 Initialize MT 3 Initialize BC 4

0xA00A 0x5FF5 No auto init. 1 No auto init. No auto init.
0xA03A 0x5FC5 X
0xA0CA 0x5F35
0xA0FA 0x5F05 X
0xA30A 0x5CF5 X
0xA33A 0x5CC5 X X
0xA3CA 0x5C35 X
0xA3FA 0x5C05 X X
0xAC0A 0x53F5 X
0xAC3A 0x53C5 X X
0xACCA 0x5335 X
0xACFA 0x5305 X X
0xAF0A 0x50F5 X X
0xAF3A 0x50C5 X X X
0xAFCA 0x5035 X X
0xAFFA 0x5005 X X X
Note 1: Default. No terminal devices (BC, MT, RT) are started. The host must write “Master Configuration Register 1
(0x0000)” to start terminals.
Note 2: The RTENA register bit 6 in register 0x0000 must be set before step 4. During auto-initialization events, the
AUTOEN input pin must be logic 1 before rising edge of MR master reset. After auto-initialization, RTSTEX bit 4 is
automatically set in “Master Configuration Register 1 (0x0000)”, starting Remote Terminal execution.
Note 3: The MTENA register bit 8 in register 0x0000 must be set before step 4. During auto-initialization events, the
AUTOEN input pin must be logic 1 before rising edge of MR master reset. After auto-initialization, the SMT MTENA bit
is automatically set in “Master Configuration Register 1 (0x0000)”, starting Bus Monitor execution.

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Note 4: The BCENA register bit 12 in register 0x0000 must be set before step 4. During auto-initialization events, the
AUTOEN input pin must be logic 1 before rising edge of MR master reset. After auto-initialization, BCSTRT bit 13 is
automatically pulsed in “Master Configuration Register 1 (0x0000)”, starting Bus Controller execution.
The three terminals can be automatically started (or not started) in any combination. For example, exclusive-
ORing both default unlock Words 1 and 2 with 0x0FF0 results in unlock Word 1 = 0xAFFA and Word 2 = 0x5005.
This combination automatically and simultaneously enables execution for all three terminal devices: BC, MT and
RT, at every subsequent auto-initialization from EEPROM. Individual soft resets for a single terminal device will
automatically enable that device, if enabled here.
Note 5: There is no maximum time limit (timeout) for programming the EEPROM.
5. The EECOPY input pin is driven high for at least 1 ms, then driven low. In response, the READY output goes
low while EEPROM memory is written. The unlock code at address 0x0051 is cleared. Device register and RAM
contents are written to the serial EEPROM, one byte at a time.
During programming, terminal checksums are tallied for the RT and SMT terminal devices, if used. An overall 8K
checksum is also tallied. These checksums, stored in the EEPROM, are used for error detection later, during auto-
initialization and soft reset events. There is no Bus Controller soft reset.
EEPROM location corresponds to

Checksum Type
RAM Address
Overall Checksum 0x0051
RT Checksum 0x01C0
SMT Checksum 0x005C
On the following pages, see the list of registers included in the stored overall and terminal checksums. When the
READY output goes high, EEPROM copy is complete.
6. For terminal devices selected for auto-enable by step 3 unlock word selection, the RTSTEX, MTENA and/or
BCSTRT bits are set in the 2-byte EEPROM image corresponding to “Master Configuration Register 1 (0x0000)”.
During subsequent auto-initialization events, these are the last bits written, just before READY assertion. Terminal
devices having enable bits set to logic 1 in the EEPROM image are automatically and simultaneously enabled
just before READY assertion. Terminal devices not automatically enabled (by step 4 unlock word selection) have
logic 0 enable bits RTSTEX, MTENA and/or BCSTRT in the 2-byte EEPROM image corresponding to “Master
Configuration Register 1 (0x0000)”. After auto-initialization, these terminal devices remain in standby until enabled
by host write to the “Master Configuration Register 1 (0x0000)”.

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19.2. Overall 8K Word Checksum Used by Auto-Initialization

When auto-initialization is performed, the overall checksum (stored in EEPROM by the EECOPY process) is used
for error checking. EECOPY stored this checksum value in the two 8-bit locations corresponding to RAM address
0x0051. This checksum covers the entire 8K word register and RAM address range from 0 to 0x1FFF, excluding the
following register addresses:
Table 17. Registers not included in checksum
Address Excluded Register Name

0x0001 Master Status & Reset Register
0x0002 RT Current Command Register
0x0003 RT Current Control Word Address Register
0x0007 BC Pending Interrupt Register
0x0008 MT Pending Interrupt Register
0x0009 RT Pending Interrupt Register
0x000A Interrupt Count & Log Address Register
0x000B Memory Address Pointer Register
0x000C Memory Address Pointer Register
0x000D Memory Address Pointer Register
0x000E Memory Address Pointer Register
0x0018 RT Operational Status Register
0x001E RT Built-In Test Word Register
0x0021 Reserved
0x0027 Reserved
0x0030 MT Next Message Command Buffer Address Register
0x0031 MT Last Message Command Buffer Address Register
0x0035 BC Frame Time Remaining Register
0x0036 BC Time to Next Message Register
0x0037 BC General Purpose Flag Register
0x003A MT Time Tag Counter Low Register
0x003B MT Time Tag Counter Mid Register
0x003C MT Time Tag Counter High Register
0x0043 BC Time Tag Counter Low Register
0x0044 BC Time Tag Counter High Register
0x0049 RT Time Tag Counter Register
0x004B Reserved
The overall checksum includes individual terminal checksums for RT and Bus Monitor, which the EECOPY process
stored at EEPROM locations corresponding to RAM addresses 0x01C0 and 0x005C respectively. All checksums
stored by the EECOPY process use two’s complement format. Each checksum is calculated by summing the individual
16-bit data values (ignoring carry) over the full set of included register and RAM addresses. The summation is then
complemented, then incremented (ignoring carry) to yield the stored two’s complement checksum value.
When the device performs checksum-based error checking, a new summation is tallied (ignoring carry) for the indi-
vidual 16-bit data values over the range of included register and RAM addresses. When this summation is added to
the previously stored two’s complement checksum, the result is zero when the new data summation is the same as
that tallied by EECOPY when the checksum was stored.

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The registers tallied in each of the RT and SMT terminal checksums are summarized on the next pages. These individ-
ual checksums are used for error checking during soft reset events. Soft reset occurs for RT or SMT when RTRESET
bit 10 and/or MTRESET bit 12 is set in the “Master Status and Reset Register (0x0001)”. One or two terminal reset
bits can be individually or simultaneously set, without affecting other on-chip terminals or the Bus Controller. The Bus
Controller does not have soft reset.
19.3. Fast Initialization Option using EE2K Pin

The address range copied during EEPROM programming depends on the state of the EE2K input pin when rising edge
occurs on the EECOPY input:
If EE2K is high when EECOPY is asserted, the lower 2K x 16 address range from 0x0 to 0x07FF is copied from
device registers and RAM to EEPROM. This includes all registers, all configuration tables in RAM and the primary
Descriptor Table in RAM at address 0x0400 to 0x05FF.
If EE2K is low when EECOPY is asserted, the entire 8K x 16 address range from 0x0 to 0x1FFF is copied from
device registers and RAM to EEPROM. This range covers all registers, all configuration tables in RAM and the primary
Descriptor Table in RAM at address 0x0400 to 0x05FF. As long as EE2K remains low when auto-initialization occurs,
the 8K x 16 programming option can initialize secondary Descriptor Tables above address 0x0600, if used.
The 8K x 16 programming option (EE2K equals zero) can also initialize fixed data for any subset of the 32 possible
transmit subaddress buffers, using any of the defined data buffer schemes. To enable EEPROM copy for transmit
subaddress data buffers, the buffer space must be pre-loaded with the desired data. Be sure to reserve space for
Message Information and Time-Tag Word locations, as required for the transmit subaddress buffer method.

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20. RESET AND INITIALIZATION

This section describes the software reset mechanisms. Hardware Master Reset returns the device to the uninitialized
state, requiring register and RAM initialization before terminal execution can begin. Hardware reset is initiated by
assertion of the MR Master Reset pin (200ns minimum assertion time). Software reset is individually or simultaneously
asserted for the Bus Monitor or RT by setting the corresponding bit(s) in the “Master Status and Reset Register
(0x0001)”. The Bus Controller does not have software reset. If AUTOEN is enabled, both hardware and software reset
copy initialization values from EEPROM into registers and RAM.
20.1. Hardware Master Reset and Optional Auto-Initialization

Hardware master reset is initiated by a low to high transition on the MR pin; it should be applied after power-up, but
may be used any time afterward. When asserted, the MR input pin causes immediate unconditional hardware reset for
all device terminals. Command processing is terminated and reset, the bus decoders and encoders are cleared, and
all Time Tag counters are reset. All internal logic is cleared. Registers are restored to the power up reset states shown
in Table 3. The READY, ACTIVE and IRQ output pins are negated if previously asserted. The READY pin remains low
until the entire reset process is complete. During this interval, a host read cycle to any address returns the value of the
“Master Status and Reset Register (0x0001)”.
After a low to high transition on the MR pin, these events occur:

1. After 200ns, input states for the RTA4-RTA0, RTAP and LOCK pins are latched into the “Remote Terminal
Operational Status Register (0x0018)”. The input state for the AUTOEN pin is latched into the “Master Status and
2. At master reset, there are four pin-selected combinations for RAM self-test on/off and auto-initialize on/off. For the
4 combinations, hardware MR rising edge to READY assertion times are summarized in the following table.
Table 18. READY delay times: from MR input pin rising edge to READY output pin rising edge
MTSTOFF Pin EE2K Pin AUTOEN Pin READY Delay

Combinations
State State State (μs)
No RAM test, No auto-initialize 1 0 0 164
Perform RAM test, No auto-initialize 0 0 0 737
No RAM test, auto-initialize (2K) 1 1 0 3,945
Perform RAM test, auto-initialize (2K) 0 1 0 4,025
No RAM test, auto-initialize (8K) 1 0 1 15,775
Perform RAM test, auto-initialize (8K) 0 0 1 16,100
If memory error occurs, the BMTF bits are set in the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”.
If the MTSTOFF pin is logic 1, the RAM test is bypassed. This option might be chosen if a faster reset process is
needed. Regardless of the MTSTOFF pin state, all RAM locations above address 0x004F are reset to 0x0000.
3. After internal processes are initialized, the device checks the state of the AUTOEN bit latched into the “Master
Status and Reset Register (0x0001)” at step 1:
If the AUTOEN bit in the “Master Status and Reset Register (0x0001)” is logic 0, auto initialization from EEPROM
is bypassed. After the RAM memory test is complete, the device asserts the READY output pin to indicate that the
device is ready for host initialization of registers and RAM:
• The “Master Configuration Register 1 (0x0000)” is initialized to indicate which terminal devices are enabled
(BCENA and RTENA). If using Bus Monitor, the MTRUN input pin should be logic 1 but the corresponding
MTENA register bit should remain logic 0 until initialization is completed. Likewise, the BCSTART and RTSTEX
bits remain low at this time.
• Other configuration registers are initialized by the host to define interrupt behavior and time tag counter behavior
for enabled terminal devices.

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• The following registers are initialized: the RT Configuration Register, the RT Descriptor Table Base Address
Register, the RT Bus A/B Select Register and the RT Interrupt Enable Register. In RAM, the RT Illegalization
Table and RT Descriptor Table are initialized. Initial data for assigned Transmit Subaddress Data Buffers may be
initialized at this time.
• If using the Bus Controller, the BC Configuration, BC Instruction List Start Address and BC Interrupt Enable Reg-
isters are initialized. In RAM, the BC Instruction List and BC Message Control Blocks are initialized.
• If using a Simple Bus Monitor, the MT Configuration, SMT Address List Start Address and SMT Interrupt Enable
registers are initialized. In RAM, the SMT Address List and SMT Filter Table are initialized.
• Upon completing all initialization for registers and RAM, the host writes the “Master Configuration Register
1 (0x0000)” to start operation for the enabled terminal devices. A combination of BCSTART, RTSTEX and/or
MTENA register bits are asserted to match the subset of initialized terminal devices (BC, RT and SMT). Device
operation begins.
If the AUTOEN bit in the “Master Status and Reset Register (0x0001)” is logic 1, auto initialization from EEPROM
is performed after completion of the RAM memory test. The READY output pin remains at logic 0 during the self-initial-
ization process. Initialization data is read from the previously-written external EEPROM and copied to the entire range
of registers and RAM, from address 0x0000 to address 0x1FFF. This process typically requires 16 ms (see Table 18).
During auto initialization, the written value for each register or RAM location is read back for confirmation. If the value
read fails to match the corresponding value in EEPROM, an initialization error is saved. This error results in action
taken later when the initialization process is finished.
While performing initialization a running checksum is tallied. A properly-configured serial EEPROM contains a 16-
bit checksum value stored at the EEPROM byte pair locations corresponding to RAM address 0x0051. The stored
checksum is tallied as if RAM address 0x0051 equals zero, and twenty-five register locations listed in Table 17 are
also excluded from the stored checksum value. The stored value is actually the twos complement of the 16-bit memory
checksum, (CHECKSUM + 1). As each individual register and RAM location is initialized, its written value is added to a
copy of the stored checksum value from EEPROM. If all locations match at the end, the running checksum tally added
to the twos complemented EEPROM checksum should equal zero.
After initialization, when READY is asserted, the 16-bit twos complement checksum value is copied from EEPROM to
device RAM address 0x0051.
If an initialization error occurred, the following events take place immediately after READY assertion:
• the IRQ interrupt output pin is asserted.
• The “Master Status and Reset Register (0x0001)” is written to indicate type of error. If checksum failure, the
EECKE register bit is asserted. If data mismatch between EEPROM and read back RAM value, the RAMIF
register bit is asserted.
• The EELF bit is asserted in the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”.
• If RAMIF read back error occurred, the address of the first occurring instance is written to register address
0x0024. See Section “20.3. Memory Test Fail Address Register (0x0024)” on page 201 for further information.
Additional locations beyond the saved address may have mismatch, but only the first instance is logged.
After copying the full range of register and RAM addresses, the RTSTEX and MTENA bits in the “Master Configuration
Register 1 (0x0000)” are still zero. In the same register, the BCSTART bit always reads zero, but the BCACTIVE bit in
the “Master Status and Reset Register (0x0001)” is still zero.
The EEPROM is written using methods described in Section 19.1. Each of the terminal devices can independently
be configured to self-start when error-free auto-initialization is complete, or not self-start, requiring a host write to
the “Master Configuration Register 1 (0x0000)” after READY assertion. In the EEPROM byte pair corresponding to
“Master Configuration Register 1 (0x0000)”:
• If the EEPROM RTSTEX and RTENA bits are both logic 1, and if the RTAPF bit is logic 0 in the “Remote
Terminal Operational Status Register (0x0018)”, the Remote Terminal will automatically start just before READY

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assertion. Once RT is started, the “Master Configuration Register 1 (0x0000)” RTSTEX bit will read logic 1. If the
EEPROM RTSTEX bit is logic 0, the host must write the “Master Configuration Register 1 (0x0000)” RTSTEX
bit high after READY assertion to start the RT. The RTENA register bit must be logic 1 before RTSTEX assertion.
• If the EEPROM BCTRIG bit is logic 1, the Bus Controller will automatically start just before READY assertion.
Once the BC is started, the “Master Configuration Register 1 (0x0000)” BCTRIG and BCSTART bits will continue
to read logic zero, but the BCACTIVE bit in the “Master Status and Reset Register (0x0001)” will read logic 1.
If the EEPROM BCTRIG bit is logic 0, the host must assert the “Master Configuration Register 1 (0x0000)”
BCSTART bit after READY assertion to start the Bus Controller. The BCSTART register bit self-resets, but the
BCACTIVE bit in the “Master Status and Reset Register (0x0001)” will read logic 1.
• If the EEPROM MTENA bit is logic 1, the Bus Monitor will automatically start just before READY assertion.
Once the Bus Monitor is started, the “Master Configuration Register 1 (0x0000)” MTENA will read logic 1. If the
EEPROM MTENA bit is logic 0, the host must write the “Master Configuration Register 1 (0x0000)” MTENA bit
high after READY assertion to start the Bus Monitor.
Note that automatic-self-start for RT requires the RTAPF status bit to be logic 0 in the “Remote Terminal Operational
Status Register (0x0018)”. This indicates valid odd parity for the terminal address and parity bits latched in the
RT Operational Status Register, not necessarily the state of the RT address and parity pins. Because auto-
initialization follows master reset, the mirrored pin states latched at reset is overwritten by EEPROM values if LOCK
input pin is logic 0.
• When the LOCK input pin is logic 1 at Master Reset rising edge, the “Remote Terminal Operational Status
Register (0x0018)” terminal address and parity bits reflect address input pin states 200ns after reset rising edge.
• When the LOCK input pin is logic 0 at Master Reset rising edge, the latched RT address, parity and LOCK
bit values are overwritten by values from the initialization EEPROM.
If automatic-self-start for RT was blocked due to invalid odd parity for the terminal address and parity bits latched
in the “Remote Terminal Operational Status Register (0x0018)”, the RTSTEX bit cannot be asserted in the “Master
Configuration Register 1 (0x0000)” until the parity error is corrected. The host may overwrite the “Remote Terminal
Operational Status Register (0x0018)” to correct the parity error, then assert RTSTEX in the “Master Configuration
If automatic-self-start for terminal devices was blocked due to RAMIF or EECKE auto-initialization errors, the host
can override the error condition after READY assertion by setting the RTSTEX, BCSTART and/or MTENA bits in the
“Master Configuration Register 1 (0x0000)” , providing the other operational conditions (in the 4-bullet list above) are
met.
A method for programming the initialization EEPROM from a fully conﬁgured terminal is explained in Section 19. If a
different method is used for writing the serial EEPROM, for successful self-initialization after Master Reset, the twos-
complemented checksum (described earlier) must be saved in EEPROM locations corresponding to device RAM
address 0x0051.
If a different method is used for writing the serial EEPROM, in order to perform soft resets, twos-complement check-
sum must be written for the Remote Terminal at 0x01C0 and the Monitor Terminal at 0x005C.
A compatible serial EEPROM uses a SPI interface for byte-access read and write operations. Sixteen-bit register and
RAM values are stored as upper and lower bytes in the EEPROM, in “big endian” fashion. For example, the upper byte
for register address 0x0000 is stored at EEPROM address 0x0000 while the lower byte is stored at EEPROM address
0x0001. A 16K x 8 EEPROM is required to store the entire 8K x 16 address range.
Serial EEPROM data mapping follows the device memory map shown in Figure 2. The three exceptions:
1. the two EEPROM bytes corresponding to device RAM address 0x0051 must contain the expected overall checksum
value and if software resets are expected
2. the two EEPROM bytes corresponding to device RAM address 0x01C0 must contain the expected terminal
checksum value for Remote Terminal 1
3. the two EEPROM bytes corresponding to device RAM address 0x005C must contain the expected terminal

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checksum value for the Bus Monitor.
The serial EEPROM used for auto-initialization should be fully written to cover the upper address limit of 0x1FFF.
Ideally the EEPROM image reﬂects a post-MR reset followed by fresh initialization by the host, with nothing written to
reset-cleared registers or RAM as a result of command processing.
20.2. Initialization using EE2K Pin

The address range copied during EEPROM programming depends on the state of the EE2K input pin when rising edge
occurs on the EECOPY input: A smaller memory space may be initialized faster by asserting the EE2K pin. See “Fast
Initialization Option using EE2K Pin”.
20.3. Memory Test Fail Address Register (0x0024)

MSB Memory Test Fail Address Register LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
If the AUTOEN input pin is logic 1, auto-initialization from EEPROM is enabled. When one or more initialized RAM
locations do not match their two corresponding serial EEPROM byte locations, RAMIF bit 13 is set in the “Hardware
Pending Interrupt Register (0x0006)”, as well as RAMIF bit 0 in the “Master Status and Reset Register (0x0001)”. Such
failure may occur during auto initialization, or execution of a partial reset caused by assertion of the RTRESET, or
MTRESET bits in the “Master Status and Reset Register (0x0001)”. The address of the first occurring RAM/EEPROM
mismatch is written to the Memory Test Fail Address Register, 0x0024. Additional locations beyond the saved address
may have mismatch, but just the first instance is logged and the test stops.
Once terminal operation starts, register 0x0024 has no function.

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20.4. Software Reset
20.4.1. Remote Terminal

This is initiated when RTRESET bit 10 is set in the “Master Status and Reset Register (0x0001)”. The following actions
are performed.
Table 19. RT Soft Reset Summary
Action Registers Affected

0x0000 Master Configuration Register, RTSTEX bit 4
0x0006 Hardware Pending Int Register, RTIP bit 2
Clears these individual register bits
0x0006 Hardware Pending Int Register, RTAPF bit 3
0x0009 RT Pending Int Register, RT int bits 8 – 3
0x0018 RT Operational Status Register
0x001A RT MIL-STD-1553 Status Word Bits Register
Clears these entire register addresses
0x001E RT Built-In Test Word Register
0x0049 RT Time Tag Counter
0x000F Hardware Interrupt Enable Register
0x0012 RT Interrupt Enable Register (see note)
0x0013 Hardware Interrupt Output Enable Register
Loads these registers from EEPROM 0x0016 RT Interrupt Output Enable Register (see note)
0x0017 RT Configuration Register
0x0019 RT Descriptor Table Base Address Register
These 522 locations comprise the RT 0x001C RT Bus A Select Register
Terminal Checksum stored at 0x01C0 by 0x001D RT Bus B Select Register
EECOPY process 0x001F RT Alternate BIT Word Register
0x004A RT Time Tag Utility Register
0x0200 through 0x02FF: RT Illegalization Table
0x0400 through 0x05FF: RT Descriptor Table
RT automatically starts (RTSTEX is set in register 0x0000) after soft reset completion, if these requirements are met:
• The RTENA bit 6 is logic 1 in the “Master Configuration Register 1 (0x0000)” when EECOPY created the EEPROM
image.
• The RTSTEX bit 4 is logic 1 in the EEPROM “Master Configuration Register 1 (0x0000)” image because the
EECOPY unlock codes during programming were Unlock Word 1 = 1010-XXXX-XX11-1010 and Unlock Word 2
= 0101-XXXX-XX00-0101 where X denotes “don’t care”.
To manually start RT after soft reset completion (indicated by READY signal assertion), the host must set RTSTEX bit
4 in register 0x0000, if RT auto-start was disabled or otherwise failed for one or more of these reasons:
• The RTENA bit 6 was logic 0 in the “Master Configuration Register 1 (0x0000)” when EECOPY created the
EEPROM image. A new EEPROM image is needed to allow auto-start after RT soft reset.
• The RTSTEX bit 4 is logic 0 in the EEPROM “Master Configuration Register 1 (0x0000)” image because the
unlock codes used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after RT soft
reset.

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20.4.2. Bus Monitor SMT

This is initiated when MTRESET bit 12 is set in the “Master Status and Reset Register (0x0001)”. The following actions
are performed.
Table 20. SMT Soft Reset Summary
Action Registers Affected

0x0000 Master Configuration Register, MTENA bit 8
Clears these individual register bits
0x0006 Hardware Pending Int Register, MTIP bit 1
0x0008 SMT Pending Interrupt Register
0x0030 SMT Next Message Buffer Address Pointer
0x0031 SMT Last Message Buffer Address Pointer
Clears these entire register addresses
0x003A SMT Time Tag Counter, Low
0x003B SMT Time Tag Counter, Mid
0x003C SMT Time Tag Counter, High
0x000F Hardware Interrupt Enable Register
0x0011 SMT Interrupt Enable Register
0x0013 Hardware Interrupt Output Enable Register
0x0015 SMT Interrupt Output Enable Register
Loads these registers from EEPROM 0x0029 SMT Configuration Register
0x002F SMT Buffer Address Table Start Address Register
0x003D SMT Time Tag Utility Register, Low
These 561 locations comprise the MT 0x003E SMT Time Tag Utility Register, Mid
Terminal Checksum stored at 0x005C by 0x003F SMT Time Tag Utility Register, High
EECOPY process 0x0040 SMT Time Tag Match Register, Low
0x0041 SMT Time Tag Match Register, Mid
0x0042 SMT Time Tag Match Register, High
0x00B0 through 0x00BF: SMT Buffer Address Table(s)
0x0100 through 0x017F: SMT Message Filter Table
Note: Soft reset for the Bus Monitor re-initializes the buffer address pointers, but does not clear the allocated buffer
space in the buffer(s).
The Bus Monitor automatically starts (MTENA is set in register 0x0000) after soft reset completion, if the following
requirements are met. Message recording commences when a new valid command is received:
• The MTENA bit 8 was logic 1 in the “Master Configuration Register 1 (0x0000)” when EECOPY created the
EEPROM image.
• The MTENA bit 8 is logic 1 in the EEPROM “Master Configuration Register 1 (0x0000)” image because EECOPY
used these unlock codes during EEPROM programming: Unlock Word 1 = 1010-XX11-XXXX-1010 and Unlock
Word 2 = 0101-XX00-XXXX-0101 where X denotes “don’t care”.
To manually start the Bus Monitor after soft reset completion (indicated by READY signal assertion), the host must set
MTENA bit 8 in register 0x0000, if auto-start was disabled or otherwise failed for one or more of these reasons:
• The MTENA bit 8 was logic 0 in the “Master Configuration Register 1 (0x0000)” when EECOPY created the
EEPROM image. A new EEPROM image is needed to allow auto-start after MT soft reset.
• The MTENA bit 8 is logic 0 in the EEPROM “Master Configuration Register 1 (0x0000)” image because the
unlock codes used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after Bus
Monitor soft reset.

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20.5. MIL-STD-1760: Busy Status Assertion After Power-Up

A MIL-STD-1760 RT must be able to respond on the bus within 150ms following power turn-on. Between power-on
and 150ms, it is acceptable for the RT to respond with the “Busy” bit set in the RT Status Word (see Section 15.6 on
page 128). This indicates the RT is awake but not ready to transfer data. Alternatively, the RT may respond Clear
Status with valid data.
In order to engage 1760 mode, the pin MODE1760 is asserted during a hardware reset. The pin status will be latched
200ns after the rising edge of MR Master Reset (the same time as the RT address). During 1760 mode, the device will
respond to any valid command (with matching RT address) with the BUSY bit set in the status word. No data words
will be transmitted and no interrupts or logging of data will occur. Mode 1760 operation may be confirmed by the host
by reading Mode 1760 Status bit 7 in “Master Configuration Register 2 (0x004E)”.
Within 500ms following power turn-on, the MIL-STD-1760 RT must respond with data as defined by the MIL-STD-1760
standard, with “Busy” status bit reset. The RT host processor must be fully operational at this time. After system
initialization is complete, the host can deactivate 1760 mode by writing “1” to bit 7 in “Master Configuration Register 2
(0x004E)”. Alternatively, bit 4 RTSTEX and bit 6 RTENA in “Master Configuration Register 1 (0x0000)” may be written
“1” either by the host or by EEPROM auto initialization (see “Hardware Master Reset and Optional Auto-Initialization”).

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21. SELF-TEST
The HI-6138 provides several host-directed RAM self-tests, as well as an automatic (but optional) RAM self-test
performed after Master Reset. In addition, on-line analog and off-line digital transmit/receive loopback tests are
provided, with different options for BC and RT terminal modes.
21.1. Optional RAM Self-Test after Hardware Master Reset

When the MTSTOFF input pin is logic 0, the device automatically performs RAM self-test after each hardware master
reset, following the rising edge of MR input signal. See Section “20.1. Hardware Master Reset and Optional Auto-
Initialization”. The READY output pin goes low at MR assertion. READY remains low after MR rising edge and during
RAM self-test. The RAM self-test performed is the increment/decrement (Inc/Dec) method described on page 210.
When successful RAM self-test is complete, the READY output pin goes high, indicating that device registers and
RAM can be configured for operation. The entire RAM address space from 0x0052 to 0x1FFF is cleared to 0x0000.
RAM self-test after hardware master reset is optional. If the MTSTOFF input pin is logic 1, RAM testing is skipped,
speeding up READY assertion. Table 18 on page 198 shows the reset timing options.
21.2. Host-Directed Self-Test

The device supports host-directed RAM self-test (sometimes called RAM built-in self-test, or RAM BIST) and single-
word transmit/receive loopback, which may be off-line digital or on-line analog. Host-directed self-test is configured
and operated using register read/write operations.
The host initiates self-test mode by asserting the TEST input pin to logic 1. When the TEST pin is high, four registers
are active for performing RAM self-test or RT mode loopback self-tests:
21.2.1. Self-Test Control Register (0x0028)

ST L
PA T
ot d
AL d
BS IL
BF S
BP T
LB OG
BU C
LB SE
LB AR
LB SS
BS 1
R EL0
BS 2
N se
LB Use
R MA
N AIL
R AS
R TR
IL
R EL
R EL
LB YN
R FA
FA
BS
A
BF
S
ot
FR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW R RW R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The function of this register is multiplexed by the device TEST input pin. When the TEST pin is logic 0 (normal
operating mode), register address 0x0028 has no function.
When the TEST input pin is logic 1, register address 0x0028 functions as the Self-Test Control Register, a Read-Write
register used for RAM memory testing, or analog or digital loopback tests. Bits 0, 1, 8, 9 are Read-Only. The remaining
bits in this register are Read-Write.
After test completion, the TEST input pin should be reset to logic 0, restoring all register bits to Read-Write.
Descriptions below apply when the TEST input pin is logic 1; the register is operating as the Self-Test Control Register.
This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self test (RAM BIST). Register
bits 5 - 0 are used for transceiver loopback testing (either digital loopback or analog loopback).
Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal
RAM memory after every MR pin master reset, unless the MTSTOFF input pin is logic 1. This option may be used to
speed up reset completion. Self-Test Control Register bits 15 - 8 provide a means for the host to perform RAM self-
test at other times. Register bits 13:11 select RAM test type. Then bit 10 assertion starts the selected RAM test, and
bits 9-8 report a pass/fail result after test completion. All tests are destructive, overwriting data present before test

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HI-6138
commencement.
NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset.
Full RAM Access Enable.

During normal operation, some bits in certain RAM locations (e.g., Descrip-
15 FRAMA R/W 0 tor Table Control Words) cannot be written by the host. When the FRAMA
bit is asserted, host writes to RAM are unrestricted to permit full testing.
During normal completion, this bit must be reset to logic 0.
RAM BIST Force Failure.

14 RBFFAIL R/W 0 When this bit is asserted, RAM test failure is forced to verify that RAM BIST
logic is functional.
RAM BIST Select Bits 2-0.

This 3-bit field selects the RAM BIST test mode applied when the
RBSTART bit is set:
Test
RBSEL2:0 Selected RAM Test
Time
000 Idle -
001 Pattern Test, described below 14.42ms
Write 0x0000 to RAM address range 0x0000 -

010 170μs
0x1FFF
13,12,11 RBSEL2:0 R/W 0
Read and verify 0x0000 over RAM address range
011 500μs
0x0000 - 0x1FFF
Write 0xFFFF to RAM address range 0x0000 -
100 170μs
0x1FFF
Read and verify 0xFFFF over RAM address range

101 500μs
0x0000 - 0x1FFF
Inc / Dec Test performs only steps 5 - 8 of the Pat-

110 1.32ms
tern Test below
111 Idle -

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Description of the RAM BIST “PATTERN” test selected when register

bits RBSEL2:0 = 001:
Note 1: Test read /write accesses to addresses 0x0000 - 0x0051 involve 82
RAM locations not accessible to the host. These accesses do not affect the
host-accessible registers, overlaying the same address range.
Note 2: Registers 0x4F and 0x50 are expected to be modified during the
RAM BIST but registers 0x0000-0x004e (with the exception of Self-Test
Register) retain their original values.
1. Write 0x0000 to all RAM locations, 0x0000 through 0x1FFF.
2. Repeat the following sequence for each RAM location from 0x00000
through 0x1FFF:
a. Read and verify 0x0000
b. Write then read and verify 0x5555
c. Write then read and verify 0xAAAA
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f. Write then read and verify 0x0F0F
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
i. Write then read and verify 0xFF00
13,12,11 RBSEL2:0 R/W 0 j. Write 0x0000 then increment RAM address and go to step (a)
(continued)
3. Write 0xFFFF to all RAM locations, 0x0000 through 0x1FFF
4. Repeat the following sequence for each RAM location from 0x00000
through 0x1FFF:
a. Read and verify 0xFFFF
b. Write then read and verify 0x5555
c. Write then read and verify 0xAAAA
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f. Write then read and verify 0x0F0F
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
i. Write then read and verify 0xFF00
j. Write 0xFFFFthen increment RAM address and go to step (a)
5. Write each cell’s memory address into each RAM location from 0x00020
to 0x1FFF.
6. Read each memory location from 0x00000 to 0x1FFF and verify it con-
tains its address.
7. Write 1s complement of each cell’s memory address, into each RAM
location (same addr range).
8. Read each memory location and verify it contains the 1s complement of
its address.
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register
bits RBSEL2:0. The RBSTRT bit can only be set if the TEST input pin
10 RBSTRT R/W 0 is high and if register bit 15 is already asserted. This bit is automatically
cleared upon test completion. Register bits 9:8 indicate pass / fail test
result. The user must reload MAP register with 0x28 before each register
read that polls result bits 9:8.

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RAM BIST Pass.

9 RBPASS R 0 Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when RBSTRT bit 10 is set.
RAM BIST Fail.

Device logic asserts this bit when failure occurs while performing the
selected RAM test. This bit is automatically cleared when RBSTRT bit 10
is set. When BIST failure occurs, a clue to the failing RAM address can be
read at register address 0x001B. For speed, the RAM BIST concurrently
8 RBFAIL R 0 tests 4 quadrants of the RAM address range, in parallel. If test failure
occurs, register address 0x001B contains the RAM address being tested
in the lowest RAM quadrant. Actual failure has occurred in any of these
four locations: at RAM address “ADDR” stored in register 0x001B, or
ADDR+0x2000, or ADDR+0x4000 or ADDR+0x6000. When the TEST input
pin is logic 0, register address 0x001B function reverts to the read-only
“Remote Terminal Current Message Information Word Register (0x001B)”.
7,6 ----- R 0 Not Used. These bits cannot be set. A READ will return 0-0.
Loopback Test Analog.

The device supports either digital or analog loopback testing for either bus
transceiver. When the LBALOG bit is low, digital loopback is selected and
5 LBALOG R/W 0 no data is transmitted onto the selected external MIL-STD-1553 bus. When
the LBALOG bit is high, analog loopback is selected and a test word is
transmitted onto and received from the selected external MIL-STD-1553
bus.
Loopback Test Word Sync Select.
4 LBSYNC R/W 0 When the LBSYNC bit is high, the loopback test word is transmitted with
command sync. When the LBSYNC bit is low, the loopback test word is
transmitted with data sync.
Loopback Test Bus Select.

3 LBBUSEL R/W 0 When this bit is low, loopback testing occurs on Bus A. When this bit is
high, loopback testing occurs on Bus B.
Loopback Test Start.
Writing logic 1 to this bit initiates the loopback test selected by register
2 LBSTART R/W 0 bits 3, 4 and 5. The LBSTRT bit can only be set if the external TEST pin
is already asserted, and is automatically cleared upon test completion.
Register bits 1,0 indicate pass / fail test result.
Loopback Test Pass.
1 LBPASS R 0 Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when LBSTART bit 2 is set.
Loopback Test Fail.

Device logic asserts this bit when failure occurs while performing the
0 LBFAIL R 0 selected loopback test. Failure is comprised of Manchester encoding error,
parity error, wrong sync type or data mismatch. This bit is automatically
cleared when LBSTART bit 2 is set.

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HI-6138
21.2.2. Loopback Test Transmit Data Register (0x001F)

MSB Loopback Test Transmit Data Register LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This register is cleared after MR pin master reset, but is not affected by SRST software reset. The function
of this register is multiplexed by the device TEST input pin. When TEST is logic 0 (normal operating mode), register
address 0x001F is the “Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)”.
When the TEST input pin is logic 1, register address 0x001F becomes the Loopback Test Transmit Data Register, a
Read-Write register used for analog or digital loopback tests. When a loopback test is performed, the value in this
register is transmitted, and should appear in the Loopback Test Receive Data Register 0x0002. See Section “21.2.1.
Self-Test Control Register (0x0028)” on page 205 (bits 0-5) for additional information.
After test completion, the TEST input pin should be reset to logic 0. The host should restore the desired alternate BIT
Word value for the RT at register address 0x001F.
21.2.3. Loopback Test Receive Data Register (0x0002)

MSB Loopback Test Receive Data Register LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This register is cleared after MR pin master reset, but is not affected by SRST software reset. The function of
this register is multiplexed by the device TEST input pin. When the TEST input pin is logic 0 (normal operating mode),
register address 0x0002 is the “Remote Terminal Current Command Register (0x0002)”.
When the TEST input pin is logic 1, register address 0x0002 becomes the Loopback Test Receive Data Register, a
read-only register used for analog or digital loopback tests. When loop back is performed, the value in the Loopback
Test Transmit Data Register 0x001F is transmitted and should appear in this register. See Section “21.2.1. Self-Test
Control Register (0x0028)” on page 205 (bits 0-5) for additional information.
After test completion, the TEST input pin should be reset to logic 0, reverting this register address 0x0002 to the read-
only “Remote Terminal Current Command Register (0x0002)”. The contained register value will not have meaning until
the RT receives its next valid command.
21.2.4. RAM Self-Test Fail Address Register (0x001B)

MSB RAM BIST Fail Address Register LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The function of this register is multiplexed by the device TEST input pin. When the TEST input pin is logic 0 (normal
operating mode), this register address is the “Remote Terminal Current Message Information Word Register (0x001B)”.
When the TEST input pin is logic 1, register address 0x001B becomes the RAM Self-Test Fail Address Register.
Upon test completion, Self-Test Control Register bit 9 (see Section “21.2.1. Self-Test Control Register (0x0028)” on
page 205) is set if the test passed, otherwise bit 8 is set if the test failed. If failure occurs, the first failed RAM address
is written to the RAM Self-Test Fail Address Register. (This is actually an offset value within a memory quadrant; see
the Self-Test Control Register bit 8 description.) Memory test fail also asserts the BTMF (BIST Memory Test Fail) bit 3

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HI-6138
in “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”.
At test completion, the host should clear the Self-Test Control Register 0x0028, and then reset the TEST input pin to
logic 0.
21.2.5. Host-Directed RAM Self-Test

Host-directed RAM self-test overwrites preexisting RAM contents and should only be performed when complete re-
configuration of the RAM address space will occur after RAM test completion. If the device is operational, terminal
execution should be stopped. If asserted, reset bits 4-8 and bit 12 in “9.1. Master Configuration Register 1 (0x0000)”,
stopping BC, MT, and RT. Assert the TEST pin to activate register 0x0028 as the Self-Test Control Register.
After asserting the TEST input pin, RAM self-test is configured and started by writing bits 15:10 in the Self-Test Control
Register, described on page 205. Register bits 13:11 select one of the five test protocols. Register bit 15 is usually set
to provide unrestricted RAM read/write access. Register bit 10 is then asserted to start the RAM test selected by bits
13:11. All of these bits may be written simultaneously, and bits 7:0 should be written as zeros. Test time varies based
on complexity; test times are shown in the Self-Test Control Register description.
Upon RAM test completion, “Self-Test Control Register (0x0028)” bit 9 is set if the RAM test was successful, otherwise
bit 8 is set if the test failed. If failure occurs, the first failed RAM address is written to the “RAM Self-Test Fail Address
Register (0x001B)”. The written value is actually an offset value within a memory quadrant; see “Self-Test Control
Register (0x0028)”, bit 8. Memory test fail also asserts the BTMF (BIST Memory Test Fail) bit 3 in “Remote Terminal
Built-In Test (BIT) Word Register (0x001E)”.
At RAM test completion, the host should clear the Self-Test Control Register 0x0028, reset the TEST input pin to logic
0, then re-initialize registers and RAM, and finally restart terminal execution.
21.2.6. Host-Directed RT-Mode Loopback Testing (On-Line Analog or Off-Line Digital)

RT mode loopback testing involves transmission and reception of a single Manchester-encoded word with correct parity.
On-line Analog Loopback transmits the specified test word onto the external MIL-STD-1553 bus. The internal receiver
for the same bus is totally independent from the encoder logic used for bus transmission. The bus receiver detects
and decodes the received replica of the transceiver’s own transmission. Off-line Digital Loopback does not disturb the
selected MIL-STD-1553 bus; the digital signal paths used for encoding and transmission (as well as reception and
decoding) are fully tested without involving the external MIL-STD-1553 bus; only the analog bus driver and analog
receiver are bypassed for digital loopback tests. The HI-6138 cannot be configured for loopback transmitting on one
bus and receiving on the other bus.
RT mode loopback testing requires the RT to be enabled. If the RT is not already running, set the RTENA bit in “9.1.
Master Configuration Register 1 (0x0000)”. Then set the RTSTEX bit in “Master Configuration Register 1 (0x0000)”.
Then initiate test mode by asserting the TEST input pin to logic 1. Note, prior to off-line Digital RT-Mode Loopback
testing, bit 0, BCLBK, in “Master Configuration Register 2 (0x004E)” must be asserted.
Write a 16-bit transmit value to the “Loopback Test Transmit Data Register (0x001F)”. With the TEST input set to logic
1, the host can write bits 5:3 in the Self-Test Control Register 0x0028 to select analog or digital loopback, command
sync or data sync, and select test Bus A or Bus B. Then, without modifying bits 5:3, write the Self-Test Control Register
again to set bit 2, starting loopback test. Note: Self-Test Control Register bits 5:2 can be written simultaneously; the
remaining register bits 15:6 and 1:0 should all be written as zeros.
After 50μs or so, RT loopback transmission is complete. Self-Test Control Register bit 1 is set for successful loopback
test, otherwise bit 0 is set if loopback failed. The received word has been written into the “Loopback Test Receive Data
Register (0x0002)”. It should match the value in the “Loopback Test Transmit Data Register (0x001F)”. Test failure
also asserts either the LBFA (Loopback Fail A) bit 5 or LBFB (Loopback Fail B) bit 4 in the “Remote Terminal Built-In
Test (BIT) Word Register (0x001E)”.
At RT loopback test completion, the host should clear Self-Test Control Register 0x0028, and then reset the TEST
input pin to logic 0.

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HI-6138
21.2.7. Programmed BC-Mode Digital Loopback Testing (Off-Line)

For any BC message block, off-line digital loopback self-test can be programmed. The TEST input pin should be
logic 0, normal operational state. Bit 0, BCLBK, in “Master Configuration Register 2 (0x004E)” must be asserted. BC
transmission onto the 1553 bus is inhibited for the message, but the digital transmit encoding and receive decoding
signal paths can be checked. Note, setting bit 0, BCLBK, in “Master Configuration Register 2 (0x004E)”, enables BC
to RT/MT Digital Loopback Testing. No loopback activity is transmitted to the bus, allowing the BC to communicate
internally with the RT and MT.
The BC Instruction List in RAM comprises a series of 2-word entries, an instruction Op Code Word followed by a
Parameter Word. While sequencing through the Instruction List, the BC control logic fetches and executes conditional
and unconditional instruction op codes referenced by the “Bus Controller (BC) Instruction List Pointer (0x0034)”. For
executable messages, the Parameter Word following the Op Code Word contains the starting address of a Message
Control/Status Block.
As described in Section “10.4. Bus Controller Message Control / Status Blocks” on page 67, each Message Control/
Status Block begins with a BC Control Word. When Control Word SELFTST bit 6 is set, off-line self-test is enabled,
inhibiting transmission onto the 1553 bus. Instead the output of the bus Manchester II serial encoder is routed directly
to the decoder input for the bus selected by Control Word bit 7 (USEBUSA). A validity check is performed on the
received replica of each transmitted word (sync, encoding, bit count and parity). As received, each word replica is
stored in the Loopback Word location in the Message Control/Status Block. The data value for the final word received
is also checked with the transmitted final word. If any word fails validity check (or if the final word has data mismatch)
test logic sets the LBE (loopback error) bit 8 in the Block Status Word.
After message processing, off-line self-test success or failure can be determined by reading the received Loopback
Word (stored in the Message Control/Status Block if BC is using 16-bit time base) or by reading the LBE (loopback
error) bit 8 in the Block Status Word. (Note: If the BC is using 32-bit time base, the final received loopback word in the
Loopback Word location is overwritten at the end of message post-processing when time tag bits 31:16 are written
there.)
The “BADMSG” BC condition code 0xC is updated based on the outcome of the off-line SELFTST loopback message.
BADMSG is set to logic 1 for Loopback Test error. This permits conditional execution, including jumps or subroutine
calls, based on the outcome of the message having SELFTST asserted in its Control Word.
The BADMSG condition code is also set for Format Error or No Response error, but is not affected by a Status
Set condition. For non-broadcast commands using off-line SELFTST loopback, No Response error always occurs
since the BC message processor expects an RT response. Since BC bus transmission is inhibited, off-line SELFTST
loopback should use broadcast commands. This avoids BADMSG condition codes caused by No Response error.
21.2.8. Continuous BC-Mode Analog Loopback Testing (On-Line)

The BC performs continuous analog loopback on all Bus Controller transmissions when executing normal Message
Control/Status Blocks having off-line SELFTST bit = 0 in each Control Word. The TEST input pin is logic 0, normal
operational state. For each Manchester II word transmitted by the BC, a validity check is performed on the received
replica, checking sync, encoding, bit count and parity. In the Message Control/Status Block, each received word replica
is stored in the Loopback Word location when decoded, overwriting the previous word stored there. The data value for
the final BC word received is also checked for data value. If any word fails validity check (or if the final word has data
mismatch) test logic sets the LBE (loopback error) bit 8 in the Block Status Word. (Note: If the BC is using 32-bit time
base, the final word replica in the Loopback Word location is overwritten at the end of message post-processing when
time tag bits 31:16 are written there.)
The “BADMSG” BC condition code 0xC is updated based on the outcome of continuous BC-mode analog loopback
checking. The BADMSG condition code is set for Loopback Error, Format Error or No Response error, but is not
affected by a Status Set condition. BC analog loopback failure also sets LBE loopback error bit 8 in the Block Status
Word.

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22. HOST SERIAL PERIPHERAL INTERFACE (SPI)

Internal RAM and registers occupy an 8K x 17 address space. The lowest 80 addresses access registers and the
remaining addresses access RAM locations. Timing is identical for register operations and RAM operations via the
serial interface, and read and write operations have likewise identical timing.
22.1. Serial Peripheral Interface (SPI) Basics

The device uses an SPI synchronous serial interface for host access to registers and RAM. Host serial communication
is enabled through the Chip Enable (CE) pin, and is accessed via a three-wire interface consisting of Serial Data Input
(SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All programming cycles are completely
self-timed, and no erase cycle is required before write.
The SPI (Serial Peripheral Interface) protocol specifies master and slave operation; the HI-6138 operates as an SPI
slave.
The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible “SPI Modes.” Without describing details of the SPI modes, the device operates in
the two modes where input data for each device (master and slave) is clocked on the rising edge of SCK, and output
data for each device changes on the falling edge. These are known as SPI Mode 0 (CPHA = 0, CPOL = 0) and SPI
Mode 3 (CPHA = 1, CPOL = 1). Be sure to set the host SPI logic for one of these modes.
The difference between SPI Modes 0 and 3 is the idle state for the SCK signal, which is logic 0 for Mode 0 state and
logic 1 for Mode 3 state (see Figure 23). There is no configuration setting to select SPI Mode 0 or Mode 3 because
compatibility is automatic. Beyond this point, the data sheet only shows the SPI Mode 0 SCK signal in timing diagrams.
The SPI protocol transfers serial data as 8-bit bytes. Once CE chip enable is asserted, the next 8 rising edges on
SCK latch input data into the master and slave devices, starting with each byte’s most-significant bit. The SPI can be
clocked at 40 MHz.
SCK (SPI Mode 0) 0 1 2 3 4 5 6 7
SCK (SPI Mode 3) 0 1 2 3 4 5 6 7
SI MSB LSB
High Z High Z
SO MSB LSB
CE
Figure 23. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0
and 3
Multiple bytes may be transferred when the host holds CE low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks. A rising edge on CE chip enable terminates the serial transfer and reinitializes the SPI
for the next transfer. If CE goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device
SI pin is discarded.

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HI-6138
Two byte transfers are needed for SPI exchange of 16- bit register values or RAM data. “Big endian” byte order is used
for SPI data transfers. The high order byte (bits 15:8) is transferred before the low order byte (bits 7:0).
In the general case, both master and slave simultaneously send and receive serial data (full duplex) per Figure 23.
However the device operates half duplex, maintaining high impedance on the SO output, except when actually trans-
mitting serial data. When sending data on SO during read operations, activity on its SI input is ignored. Figure 24 and
Figure 25 show actual behavior for the SO output.
22.2. SPI Commands

Each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after as-
sertion of CE. Since command byte reception is half-duplex, the host discards the dummy byte it receives while serially
transmitting the command byte.
The SPI command set uses the most significant command bit to specify whether the command is Read or Write. The
command byte MSB is zero for read commands, and one for write commands.
22.3. Fast-Access Commands for Registers 0-15

The SPI command set includes directly-addressed read commands for registers 0 through 15. The 8-bit pattern for
these read commands has the general form
0-0-R-R-R-R-0-0
where RRRR is the 4-bit register address. These fast-access read commands appear in Table 21.
22.4. Fast-Access Write Commands for Registers 0-63

The SPI command set includes directly-addressed write commands for registers 0 through 63. The 8-bit pattern for
these read commands has the general form
1-0-R-R-R-R-R-R
where RRRRRR is the 6-bit register address. The fast-access write commands appear in Table 21.
Figure 24 and Figure 25 show read and write timing as it appears for fast-access register operations. The command
byte is immediately followed by two data bytes comprising the 16-bit data word read or written. For a register read or
write, CE is negated after the 2-byte data word is transferred.
22.5. Indirect Addressing of RAM and Registers

Refer to the SPI command set shown in Table 22. All SPI commands other than fast-access use a Memory Address
Pointer register to indicate the starting address for read or write transactions. Four “Memory Address Pointers” reside
at register addresses 0x000B through 0x000E. Just one Memory Address Pointer (MAP) is active (enabled) at any
time.
The active Memory Address Pointer is selected by writing the MAPSEL bits 11-10 in the “Master Configuration Register
1 (0x0000)”. Or use the SPI instruction op codes 0xD8, 0xD9, 0xDA or 0xDB which enable MAP registers 0x000B,
0x000C, 0x000D or 0x000E respectively, by automatically writing MAPSEL bits 11-10 in the “Master Configuration

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HI-6138
The active Memory Address Pointer must be initialized before any read or write operation, other than fast-access.
To write the active MAP register, use a fast-access write op code, followed by the desired 16-bit memory address:
• Writing MAP register 0x000B uses SPI op code 0x8B followed by 16-bit address.
• Writing MAP register 0x000C uses SPI op code 0x8C followed by 16-bit address
• Writing MAP register 0x000D uses SPI op code 0x8D followed by 16-bit address.
• Writing MAP register 0x000E uses SPI op code 0x8E followed by 16-bit address.
To read the active MAP register, use a fast-access write op code. The current MAP 16-bit value is clocked out in the
next 16 sequential SCK clock cycles:
• Reading MAP register 0x000B uses SPI op code 0x2C
• Reading MAP register 0x000C uses SPI op code 0x30
• Reading MAP register 0x000D uses SPI op code 0x34
• Reading MAP register 0x000E uses SPI op code 0x38
While SPI command op codes are always 8 bits, transacted addresses and register or memory data are always 16-
bit words, transferred by the SPI as two sequential bytes. After a 2-byte read/write completion, the active Memory
Address Pointer automatically increments to the following register address. The host can extend the read or write
operation to the next register address by continuing to hold CE low while clocking SCK 16 additional times. This auto-
increment feature can be used to access one or more sequential register addresses above the command address.
Auto-increment applies (ranging to the top of the address space) as long as SCK continues to be clocked under
continuous CE assertion. Caution: When the primary address pointer is used for auto-incrementing multi-word read/
write and reaches the top of the address range (0x1FFF) the next increment rolls over the MAP value to 0x0000. The
host should avoid this situation.
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK
SPI Mode 0
MSB LSB
SI
Command Byte MSB LSB MSB LSB

High Z High Z
SO
Data Byte 0 Data Byte 1
CE
Host may continue to assert CE

here to read sequential word(s).
Each word needs 16 SCK clocks.
Figure 24. Single-Word (2-Byte) Read From RAM or a Register

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HI-6138
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK
SPI Mode 0
MSB LSB MSB LSB MSB LSB
SI
Command Byte Data Byte 0 Data Byte 1
High Z
SO
CE
Host may continue to assert CE

here to write sequential word(s).
Each word needs 16 SCK clocks.
Figure 25. Single-Word (2-Byte) Write To RAM or a Register

Three single-byte SPI commands modify the value in the active Memory Address Pointer, selected by MAPSEL bits
11-10 in the “Master Configuration Register 1 (0x0000)”:
Command Address Pointer Operation

0xD0 increment enabled Memory Address
Pointer value
0xD2 add 2 to enabled Memory Address
Pointer value
0xD4 add 4 to enabled Memory Address
Pointer value
The “Add 4” command may be useful when sequentially accessing the same word (for example, the Control Word) in
a series of 4-word Descriptor Table entries. The “Add 2” command might be useful for reading the Interrupt Log Buf-
fer, comprised of 2-word log entries. In both cases, the Add command would be probably followed by Read command
0x40 to read the location addressed by the current pointer value. Similarly, Write command 0xC0 writes the location
addressed by the current pointer value. Two command bytes cannot be “chained”; the host SPI Slave Select CE must
be negated after the Add command, then reasserted for the following Read or Write command.
The active Memory Address Pointer is not affected by fast-access read/writes to the low register addresses because
fast-access SPI commands use a separate, internal pointer not directly accessible to the host.
Two single-byte SPI commands use the current value of the enabled Memory Address Pointer without first loading or
otherwise modifying it:
Command Read Operation

0x40 read location addressed by enabled
Memory Address Pointer
Command Write Operation

0xC0 write location addressed by enabled
Memory Address Pointer
Either of these commands can be used to read or write a single location, or may be used to start a multi-word read or
write that uses the MAP pointer’s auto-increment feature.

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One single-byte SPI command increment the current value of the enabled Memory Address Pointer, then performs a
write:

add 1 to enabled Memory Address
0xC8
Pointer then write addressed location
22.6. Data Prefetch for SPI Read Cycles

Data prefetch is a technique used to speed up host multi-word read access to registers or RAM. Prefetching occurs
when logic accesses data before it is actually needed. Because register or RAM locations are often read sequentially,
performance improves when data is prefetched in address sequence order. For any SPI read cycle, the device first
fetches the addressed location, then increments the memory address pointer and prefetches the following address,
to speed up access in the likely event that the following word will be read next. The read cycle prefetch allows the SPI
host to read sequential locations back-to-back, continuing as long as the host asserts chip select and provides SPI
clock. This is described as the Memory Address Pointer “auto-increment” feature.
There is an exception: read cycle prefetch is blocked when the next RAM address is a Control Word in the RT
Descriptor Table. If allowed, pre-fetch (like any other read) resets the Control Word DBAC status bit. To preserve
DBAC status bit function, prefetch is disabled when reading Control Words within Descriptor Table address range.
The table base address (set by the value in “Remote Terminal Descriptor Table Base Address Register (0x0019)”) and
every fourth word thereafter is a Control Word. This consists of table addresses having these offsets from the table
start address: 0, 4, 8, 0xC through and including 0x1F8 and 0x1FC. See further information in Section 22.8.
These two commands can be used to read or write a single location, or may be used to start a multi-word read or write
that uses the pointer’s auto-increment feature.
22.7. Special Purpose Commands

Several other SPI commands load or otherwise modify the active Memory Address Pointer before initiating a read or
write process. These commands were tailored to the specific needs of Remote Terminal host software.
Using a single-byte SPI command, the active Memory Address Pointer can be directly loaded with the memory ad-
dress for the RT descriptor table Control Word corresponding to the last completed MIL-STD-1553 command. The
Control Word is then read.

Copy RT Current Control Word Address
register 3 into the enabled Memory
0x48
Address Pointer. Read the location
addressed by the new pointer value.
This command can be used to read just the current RT Control Word, or may be used to start a multi-word read be-
cause memory pointer auto-increment occurs after the Control Word is read.

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Six single-byte SPI commands add an offset to the current address pointer value, then read the addressed memory
location; the read value is then written to the address pointer register 15. The new pointer value is used to start a read
or write operation:

Read the location addressed by the
enabled Memory Address Pointer. Write
0x68
the value just read into the Memory
Address Pointer. Then read.
Add 1 to the enabled Memory Address
Pointer. Read value at newly addressed
0x70
location and write it into the Memory
0x78

Read the location addressed by the
enabled Memory Address Pointer. Write
0xE8
the value just read into the Memory
Address Pointer. Then write.
0xF0
0xF8
Primary use occurs when the RT Descriptor Table Control Word was just read. For example, the last op code performed
was 0x48, reading the RT Control Word for the last command. After reading the Control Word, the enabled Memory
Address Pointer automatically incremented. The host can examine flag bits contained in the just-read Control Word
to determine the applicable data buffer (e.g., Data Buffer A, Data Buffer B or the Broadcast Data Buffer) then directly
service that buffer using these op codes; the three data buffer pointers occur in the three words following the initially
read Control Word.
These six commands can be used to read or write a single location, or may be used to start a multi-word read or write
that uses the pointer’s auto-increment feature.
When some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single-
byte SPI command may be useful if polling the RT Descriptor Table for message activity. In this situation, the host may
poll a series of Descriptor Table Control Words looking for instances where the DBAC activity bit is set. The DBAC
(Descriptor Block Accessed) flag is set in the Control Word each time the corresponding command is completed. The
process of reading the Control Word automatically resets the register’s DBAC bit so the host can detect activity the
next time the DBAC flag is set by the device.

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HI-6138
Since RT Descriptor Table Control Words are spaced four words apart, this command is useful when polling a series
of descriptor table Control Words:

read addressed location then add 4 to
0x60
pointer
Primary use occurs when the address pointer initially points to the first Descriptor Table Control Word in a series of
Control Words to be polled (every fourth word).
After 8 SCK clocks for the SPI command, each instance of this command reads a single location using 16 SCK clocks.
If CS remains low after 24 clocks and SCK continues, a multi-word read begins, using the address pointer’s auto-
increment feature. The second word read is at (Control Word address + 4), the next Control Word in the table.
Another single-byte SPI command is useful when servicing interrupts. When enabled interrupts occur, two words are
written to the circular 64-word Interrupt Log Buffer, and the Interrupt Log Address register 0x000A is updated to show
the storage address where interrupt information words will be stored for the next occurring interrupt. Buffer starting
address is 0x0180 and ending address is 0x01BF. Because two words are written to the buffer for each interrupt, the
Interrupt Log Address register always contains an even value in the range of 0x0180 to 0x01BE.
When servicing an interrupt that just occurred, the host wants timely information on that interrupt. An SPI command is
provided to simplify interrupt handling:

Write enabled Memory Address Pointer
with the current bit 8:0 address value
in Interrupt Log Address register minus
1. (See note.) If address bits 8:0 equal
0x0180, then 0x1BF is written into
Memory Address Pointer. Then read
0x58
the newly-addressed RAM location,
containing the last-written Interrupt
Address Word. Then decrement the
Memory Address Pointer, which then
addresses the corresponding Interrupt
Information Word
Note: Bits 15:9 in the Interrupt Log Address register contain the interrupt count since the Log Address register was last
read. These bits are not written to the Memory Address Pointer.
This command can be used to read a single location (the last-written Interrupt Address Word), or may be used to
start a multi-word read in which the Memory Address Pointer automatically decrements after each word is read, read-
ing words stored in the Interrupt Log Buffer, in Last In First Out order. This is the only SPI op code that decrements
the Memory Address Pointer for multi-word operations. Repeated memory pointer decrements will wrap around the
0x0180 to 0x01BF Interrupt Log Buffer boundary.

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HI-6138
22.8. RT Descriptor Table Prefetch Exceptions

For the SPI-interface, the enabled Memory Address Pointer (register 0x000F) contains the address for each new word
read by the host. When starting a read access, the host usually writes the enabled Memory Address Pointer with the
address for the first word to read. The host then uses an SPI op code to initiate the read process. After the addressed
word is transferred by SPI to the host, the device continues to read and transmit words from sequential RAM memory
addresses, as long as the host continuously asserts chip select while providing SCK serial clock pulses. After fetching
each new word, the device increments the Memory Address Pointer and prefetches the data contained in the newly
addressed location. The next word is prefetched even when the host does not ultimately read the following address.
Sequential reads from the RT Descriptor Table that rely on MAP auto-increment will stop advancing when the next
address contains a RT Descriptor Table Control Word. Properly designed SPI transfers overcome this behavior.
Using SPI command op codes, the host must consider prefetch and pointer behavior when reading data from the
Descriptor Table. Applied outside the RT Descriptor Table, the following SPI sequence would read data from six
successive memory addresses. But below, applied within the table, the sequence gets stuck at the fourth word read.
Below we assume the RT Descriptor Table starts at default base address, 0x0400. The host first uses SPI op codes
0xD8 and 0x8B to enable Memory Address Pointer 0x000B then write the table start address 0x0400 into it. The
sequence then uses op code 0x40 (and MAP auto-increment) to read the first MAP-addressed location and successive
locations.
Notice: There is no MAP auto-increment or data prefetch when MAP equals 0x0403, so the final two read cycles
repeat the previous read value and address.
FROM FROM
HOST HI-6138 COMMENT
===== ======= ==========================================
0xD8 ---- SPI op enables memory address pointer (MAP) 0x000B.
0x8B ---- SPI op code writes memory address pointer (MAP).
0x0400 ---- RT Descriptor Table start address written to MAP.
0x40 ---- SPI op code to “read location addressed by MAP”
---- <data> data from 0x0400 (SCK continues afterward)
---- <data> data from 0x0403 (SCK continues afterward, Control Word next)
---- <data> data from 0x0403 (SCK continues afterward, Control Word next)
---- <data> data from 0x0403 (SCK stops and /CS is then negated)
Using a different SPI op code sequence, the host can read the entire RT Descriptor Table without getting stuck at the
first Control Word read by the multi-word transfer using op code 0x40:
FROM FROM
HOST HI-6138 COMMENT
===== ======= ==========================================
0xD8 ---- SPI op enables memory address pointer (MAP) 0x000B.
0x8B ---- op code writes memory address pointer (MAP)
0x03FF ---- decremented table start addr 0x0400 - 1 written to MAP
0xD0 ---- op code increments enabled MAP

0x40 ---- op code reads MAP-addressed location
---- <data> data from 0x0403 (SCK stops and /CS is negated)

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HI-6138
---- <data> data from 0x0407 (SCK stops and /CS is negated)

---- <data> data from 0x040A (SCK continues afterward)
---- <data> data from 0x040B (SCK stops and /CS is negated)
The host may repeat this sequence until the entire RT Descriptor Table is read. The repeating read process is not
shown, but the sequence could end like this, stopping at the upper table boundary…

---- <data> data from 0x05FC (SCK continues afterward)
---- <data> data from 0x05FD (SCK continues afterward)
---- <data> data from 0x05FE (SCK continues afterward)
---- <data> data from 0x05FF (SCK stops and /CS is negated) TABLE ENDS
In most situations, the repeating op code block (0xD0 with 8 SCK clocks and op code 0x40 with 72 SCK clocks) would
be implemented as a loop, rather than straight-line code. A total of 128 loop repetitions would be required to read the
RT Descriptor Table from start to finish.

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Table 21. Fast-Access SPI Commands for Lower Registers

Op Code Bits 5:2 Convey the 4-Bit Register Read Address.
Command Bits 5:0 Convey the 6-Bit Register Write Address.
Command Bits HEX Command Bits HEX

Fast-Access Read Fast-Access Write
7 6 5 4 3 2 1 0 Byte 7 6 5 4 3 2 1 0 Byte
0 0 0 0 0 0 0 0 0x00 Read Register 0 1 0 0 0 0 0 0 0 0x80 Write Register 0
0 0 0 0 1 1 0 0 0x0C Read Register 3 1 0 0 0 0 0 1 1 0x83 Write Register 3
0 0 0 1 1 1 0 0 0x1C Read Register 7 1 0 0 0 0 1 1 1 0x87 Write Register 7
0 0 1 0 1 0 0 0 0x28 Read Register 10 1 0 0 0 1 0 1 0 0x8A Write Register 10
0 0 1 0 1 1 0 0 0x2C Read Register 11 1 0 0 0 1 0 1 1 0x8B Write Register 11
0 0 1 1 0 0 0 0 0x30 Read Register 12 1 0 0 0 1 1 0 0 0x8C Write Register 12
0 0 1 1 0 1 0 0 0x34 Read Register 13 1 0 0 0 1 1 0 1 0x8D Write Register 13
0 0 1 1 1 0 0 0 0x38 Read Register 14 1 0 0 0 1 1 1 0 0x8E Write Register 14
0 0 1 1 1 1 0 0 0x3C Read Register 15 1 0 0 0 1 1 1 1 0x8F Write Register 15
decimal 15 1 0 0 1 0 0 0 0 0x90 Write Register 16

is end of read
address range 1 0 0 1 0 0 0 1 0x91 Write Register 17
1 0 0 1 0 0 1 0 0x92 Write Register 18
1 0 0 1 0 0 1 1 0x93 Write Register 19
1 0 0 1 0 1 0 0 0x94 Write Register 20
1 0 0 1 0 1 0 1 0x95 Write Register 21
and so on, .
to 63 decimal .
1 0 1 1 1 1 0 1 0xBD Write Register 61
1 0 1 1 1 1 1 0 0xBE Write Register 62
1 0 1 1 1 1 1 1 0xBF Write Register 63
decimal 63
is end of write
address range

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HI-6138
Table 22. SPI Commands using Memory Address Pointer
Hex Read or
Read
Byte Write
Select / Enable a Memory Address Pointer
0xD8 ------- Enable Memory Address Pointer at register 0x000B
0xD9 ------- Enable Memory Address Pointer at register 0x000C
0xDA ------- Enable Memory Address Pointer at register 0x000D
0xDB ------- Enable Memory Address Pointer at register 0x000E
Memory Address Pointer Operations (no data is written or read)
0xD0 ------- Add 1 to the current value of the enabled Memory Address Pointer
Read / Write RAM or Register Location Using Current Address Pointer Value
0x40 R Read location addressed by the current value of the enabled Memory Address Pointer
0xC0 W Write location addressed by the current value of the enabled Memory Address Pointer
Increment Address Pointer Then Write Addressed RAM or Register Location
0xC8 W Write addressed location after incrementing the enabled Memory Address Pointer
Special Purpose Commands

Copy RT current Control Word address (register 3) to enabled Memory Address Pointer, then
0x48 R
read the location addressed by the new pointer value (read the current Control Word)
0x68 R Add 0 to the current value of the enabled Memory Address Pointer. Then . . .
0x70 R Add 1 to the current value of the enabled Memory Address Pointer. Then . . .
Add 2 to the current value of the enabled Memory Address Pointer. Then copy value from
0x78 R newly addressed location to the enabled Memory Address Pointer then read newly addressed
location.
0xE8 W Add 0 to the current value of the enabled Memory Address Pointer. Then . . .
0xF0 W Add 1 to the current value of the enabled Memory Address Pointer. Then . . .
Add 2 to the current value of the enabled Memory Address Pointer. Then copy value from
0xF8 W newly addressed location to the enabled Memory Address Pointer then write newly addressed
location.
0x60 R Read then add 4 to the current value of the enabled Memory Address Pointer.
Write storage address of last-written Interrupt Address Word to the enabled Memory Address
0x58 R Pointer, then read the Interrupt Address Word from the Interrupt Log buffer.
Decrement Memory Address Pointer after read operation

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23. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS
Bits Updated
Circumstances for Terminal Response to Bits Updated in Data Interrupt
in Descriptor
Received Message Received Command Buffer Msg Info Word Options
Control Word
Invalid Command No terminal response,

No Message Info Word
Word (Manchester, the message is ignored. No change None
is written
parity or bit count error) No Status Word change.
Any valid command

No terminal response,
to RT31 (broadcast).
the message is ignored.
when the BCSTINV No Message Info Word
No Status Word change. No change None
bit in the RT is written
(Broadcast commands
Configuration
are rendered invalid.)
Register equals 1.
RT Address Parity Error For commands to the RT’s
based on RTA and own address or to broadcast RTAPF
No Message Info Word
RTAP address RT31: No terminal No change (not
is written
bits in the Operational response, message is ignored. optional)
Status Register No Status Word change.
Any valid non-mode
(subaddress 1-30) No terminal response, DBAC bit set. IWA
MERR bit set.
transmit command Set Message Error (ME) DPB bit toggles. IBR
BUSID bit updated.
to RT31 (undefined and BCR status bits. BCAST bit set. (IXEQZ)
broadcast transmit).
Any valid non-mode
Normal Status Word response Normal CS update:
(subaddress 1-30)
(Clear Status). Data words for BUSID bit updated.
transmit command DBAC bit set. IWA
transmit are read from the MERR bit reset.
except for RT31. The DPB bit toggles. IBR
RAM data buffer assigned ILCMD bit reset.
corresponding bit BCAST bit reset. (IXEQZ)
by the Descriptor Table entry RTRT bit updated.
in the Illegalization
for the transmit subaddress. (Other error bits reset).
Table equals 0.*
Any valid non-mode

(subaddress 1-30) ILCMD bit set.
Assert Message Error (ME)
transmit command DBAC bit set. BUSID bit updated.
status, then transmit ILCMD
except for RT31. The DPB bit toggles. MERR bit set.
ME Status Word IWA
corresponding bit BCAST bit reset. RTRT bit updated.
without following data words.
in the Illegalization (Other error bits reset).
Table equals 1. **
Normal Status Word response

Any valid non-mode Normal update:
(Clear Status). After message
(subaddress 1-30) BUSID bit updated.
completion, the data words DBAC bit set. IWA
receive command. MERR bit reset.
received are stored in the data DPB bit toggles. IBR
The corresponding ILCMD bit reset.
buffer RAM location assigned BCAST bit reset. (IXEQZ)
bit in the Illegalization RTRT bit updated.
by the Descriptor Table entry
Table equals 0. * (Other error bits reset).
for the receive subaddress.
* Terminal is using “illegal command detection” and command is legal

OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response).
** Terminal is using “illegal command detection” and command is illegal.

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Bits Updated
in Descriptor
Control Word
Assert Message Error (ME)

Any valid non-mode
status and set BCR if ILCMD bit set.
(subaddress 1-30) DBAC bit set. ILCMD
broadcast. BUSID bit updated.
receive command. DPB bit toggles. IWA
Any received data words are MERR bit set.
The corresponding bit BCAST bit IBR
ignored and are not saved. RTRT bit updated.
in the Illegalization updated. (IXEQZ)
When data reception stops, (Other error bits reset)
Table equals 1. **
transmit Status Word.
MERR bit set.

Valid receive
No terminal response. DBAC bit set. BUSID bit updated.
command followed MERR
Set Message Error (ME) status. BCAST bit IWDERR bit set.
by invalid data word IWA
If broadcast (RT31), also set updated. ILCMD bit reset.
(Manchester, parity IBR
the BCR status bit. DPB bit toggles. RTRT bit updated
or bit count error).
(Other error bits reset).
Valid receive command

MERR bit set.
followed by one or No terminal response. DBAC bit set.
BUSID bit updated. MERR
more Set Message Error (ME) status. BCAST bit
SYNERR bit set. IWA
good data words, then If broadcast (RT31), also set updated.
ILCMD bit reset. IBR
a data word having the BCR status bit. DPB bit toggles.
Command Sync.
MERR bit set.

BUSID bit updated.
Any valid command
No terminal response. DBAC bit set. Set WCTERR (too few)
followed by wrong MERR
Set Message Error (ME) status. BCAST bit or GAPERR (too
number of data IWA
If broadcast (RT31), also set updated. many).
words (too few or IBR
the BCR status bit. DPB bit toggles. ILCMD bit reset.
too many words)
RTRT bit updated.
RT-RT where CW1

is a valid non-mode Normal CS update:
Normal Status Word response
receive command. DBAC bit set. BUSID bit updated.
(Clear Status). If RT-RT IWA
CW2 is a non-mode BCAST bit RTRT bit set.
Command IBR
transmit command updated. RTCWERR bit reset.
Word 1 is broadcast (RT31) (IXEQZ)
valid for different RT. DPB bit toggles. ILCMD bit reset.
set the BCR status bit.
(Normal RT-RT (All error bits reset).
receive message)
RT-RT where CW1

is a valid non-mode
receive command. MERR bit set.
No terminal response.
Transmit command DBAC bit set. BUSID bit updated.
Set Message Error (ME) status. MERR
CW2 has an error: BCAST bit RTRT bit set.
If RT-RT Command Word 1 is IWA
T/R bit = 0, or CW2 updated. RTRTCWERR bit set.
broadcast (RT31) also set IBR
subaddress equals DPB bit toggles. ILCMD bit reset.
the BCR status bit,
0 or 31 (mode code), (Other error bits reset).
or CW2 has same RT
address as CW1.

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Bits Updated
in Descriptor
Control Word
RT-RT where CW1

MERR bit set.
is a valid non-mode No terminal response.
DBAC bit set. BUSID bit updated.
receive command. Set Message Error (ME) status. MERR
BCAST bit RTRT bit set.
CW2 is valid for If RT-RT Command Word 1 is IWA
updated TMOERR bit set.
different RT but broadcast (RT31), also set IBR
DPB bit toggles. ILCMD bit reset.
transmitting RT does the BCR status bit.
not respond in time.
RT-RT receive
command (CW1 is
valid). The transmitting
RT response has one
MERR bit set.
of these errors:
BUISID bit reset.
invalid word No terminal response.
RTRT bit set.
(Manchester, Set Message Error (ME) status. DBAC bit set. MERR
IWDERR bit set,
(sync, bit count, If RT-RT Command Word 1 is BCAST bit reset. IWA
or WCTERR bit set
parity or word count broadcast (RT31) also set DPB bit toggles. IBR
for Tx RT Busy case.
error). Also includes the BCR status bit.
ILCMD bit reset.
transmitting RT
response with Message
Error or Busy status
followed by no data
words.
RT-RT command
Normal Status Word
where CW2 is a
response. Clear status
valid non-mode Normal CS update:
is transmitted with the
(subaddress 1-30) BUSID bit updated.
commanded number of DBAC bit set.
transmit command. MERR bit reset. IWA
data words. Data words for BCAST bit reset.
CW1 is a non-mode ILCMD bit reset. (IXEQZ)
transmit are read from the DPB bit toggles.
receive command RTRT bit set.
RAM data buffer assigned
for RT31. (Normal (All error bits reset).
in the Descriptor Table entry
broadcast RT-RT
for the transmit subaddress.
transmit)
Valid mode code

command to RT31
(broadcast). The No Message Info Word
the message is ignored. No change None
BCSTINV bit in the RT is written
No Status Word change.
Configuration
Register equals 1.
Valid undefined
mode code
NOTE:
command. The No Message Info Word
This only applies for the No change None
UMCINV bit in the RT is written
undefined mode codes:
Configuration
MC0 to MC15 with T/R = 0
Register equals 1.
MC16,18 & 19 with T/R = 0
MC17,20 & 21 with T/R = 1

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HI-6138
Bits Updated
in Descriptor
Control Word
If MC2 (transmit status)

or MC18 (transmit last
command) status word
from last command is
transmitted. If MC18,
data word transmitted
is read from an internal
register.
OR
If not MC2 or MC18,
normal Status Word
Valid defined mode response. If broadcast,
Normal CS update:
code command assert Status Word
(including reserved BCR bit. IWA
BCAST bit MERR bit reset.
mode code) not IBR
updated. ILCMD bit reset.
“illegalized” by For mode codes 16-31 (IXEQZ)
DPB bit toggles. RTRT bit reset.
Illegalization Table with T/R bit = 1 which
(All error bits reset.)
(table bit equals 0 *) transmit a data word,
the word for transmit
is read from the Mode
Command Data Table.
AND
For all mode commands
with mode data word
(mode codes 16-31),
the transmitted or
received data word is
written to command’s
Descriptor Word 4.
Set Message Error (ME) status.
If not broadcast (RT31),
transmit.
Status Word without a following
mode data word. If broadcast
Valid defined mode (RT31), also assert the BCR ILCMD bit set.
DBAC bit set.
code command that status bit. BUSID bit updated. ILCMD
BCAST bit
is “illegalized” by the AND MERR bit reset. IWA
updated.
IllegalizationTable For mode commands with RTRT bit reset. IBR
DPB bit toggles.
(table bit equals 1 **) a mode data word (Other error bits reset.)
(mode codes 16-31),
no updates are made to
the Mode Command Data
Table or to the command’s
Word 4 in Descriptor Table.

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Bits Updated
in Descriptor
Control Word
If bit in Illegalization Table that DBAC bit set. ILCMD bit set. ILCMD
corresponds to the undefined BCAST bit BUSID bit updated. IWA
mode code command equals updated. MERR bit reset. IBR
1 ** DPB bit toggles. RTRT bit reset.
Set Message Error (ME) status, (Other error bits reset.)
If not broadcast (RT31),
transmit
Status Word without a
following mode data word.
If broadcast (RT31), also
assert the BCR status bit.
OR
If bit in Illegalization Table that DBAC bit set. Normal CS update: IWA
corresponds to the undefined BCAST bit BUSID bit updated. IBR
mode code command equals updated. MERR bit reset. (IXEQZ)
Valid undefined mode
0* DPB bit toggles. ILCMD bit reset.
code command.
Normal Status Word (Clear RTRT bit reset.
The UMCINV bit
Status) response. If command (All error bits reset.)
in the RT Configuration
was broadcast (RT31),
Register equals 0.
assert the BCR status bit.
AND
For mode codes 16-31
with T/R bit = 1 which
transmit a data word,
the word for transmit
is read from the Mode
Command Data Table.
AND
For all mode commands
with mode data word
(mode codes 16-31),
the transmitted or
received data word is
written to command’s
Descriptor Word 4.

227
HI-6138
Bits Updated
in Descriptor
Control Word
MERR bit set.

Valid receive
No terminal response. DBAC bit set. BUSID bit updated.
command followed MERR
Set Status Word ME bit, BCAST bit IWDERR bit set.
by invalid data word IWA
If broadcast, also set updated. ILCMD bit reset.
(Manchester, parity IBR
Status Word BCR bit. DPB bit toggles. RTRT bit updated.
or bit count error).
(Other error bits reset.)
Superseded Message:
No change No Msg Info None for
Terminal receives an
to superseded Word written for super-
incomplete message Terminal aborts processing
command’s the superseded seded
interrupted by a gap for first message and
Control Word. command. command
of at least 3.5 us, responds in full to the
followed by a new second (superseding)
For superseding For superseding IWA
valid command on message. The Status
command’s command’s IBR
the same bus or Word BCR bit reflects
Control Word: data buffer, a (IXEQZ)
on the other bus broadcast status for:
DBAC bit set. normal CS update:
OR the second command,
BCAST bit BUSID bit updated.
Terminal is transacting unless second command
updated MERR bit reset.
a transmit message on is MC2 (transmit status)
DPB bit toggles. ILCMD bit reset.
one bus and receives or MC18 (transmit last
RTRT bit updated.
the start of a valid command).
command on the other
bus.
Busy bit is set in the 1553

Terminal is Busy for a Status Bits register. Status
valid receive command Word is transmitted,
either globally (BUSY unless broadcast. If WASBSY bit set.
bit set in Status Word broadcast, the BCR bit DBAC bit set. BUSID bit updated.
Bits register) or in in Status Word is also BCAST bit MERR bit reset. IWA
response to a particular set. After message updated. ILCMD bit reset. IBR
valid receive command completion, data words DPB bit toggles. RTRT bit updated.
(MKBUSY bit set in the received are stored in (All error bits reset.)
command’s Descriptor the data buffer assigned
Table control word.) by the receive subaddress
Descriptor Table entry.
Terminal is Busy for a

valid transmit
command Busy bit is set in the 1553 DBAC bit set.
WASBSY bit set.
either globally (BUSY Status Bits register. If not BCAST bit
BUSID bit updated.
bit set in Status Word broadcast, Status Word is updated,
MERR bit reset. IWA
Bits register) or in transmitted without data. (mode
ILCMD bit reset. IBR
response to a particular If broadcast, the BCR bit commands
RTRT bit updated.
valid receive command in Status Word is also with T/R = 1)
(MKBUSY bit set in the set. DPB bit toggles
command’s Descriptor
Table control word.)

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Bits Updated
in Descriptor
Control Word
DYNAMIC BUS
See Dynamic Bus Control
CONTROL (MC0):
Enable, DBCENA bit 10 in
Mode code command
“Remote Terminal Configuration
with mode code
Register (0x0017)” on page
00000 and T/R bit
119.
equals 1
RT is not using “illegal DBAC bit set. Normal CS update: IWA

The mode code’s bit command detection.” BCAST bit reset. BUSID bit updated.
in Illegalization Table Respond “in form”: Reset DPB bit toggles. MERR bit reset.
equals 0 * Message Error (ME) status ILCMD bit reset.
and transmit Status Word. RTRT bit reset.
OR OR
The mode code’s bit RT is using “illegal DBAC bit set. ILCMD bit set. ILCMD
in Illegalization Table command detection”and BCAST bit reset. BUSID bit updated. IWA
equals 1 ** mode code is illegalized. DPB bit toggles. MERR bit reset.
Set Message Error (ME) RTRT bit reset.
status and transmit Status (Other error bits reset.)
Word.
MC0 EXCEPTIONS:
MERR bit set.

DBAC bit set.
Broadcast address No Status Word transmit. BUSID bit updated. MERR
BCAST bit set.
RT31 (broadcast not Set the Message Error ILCMD bit reset. IWA
DPB toggles.
allowed) (ME) and BCR status bits. RTRT bit reset. IBR
MERR bit set.

WCTERR bit set.
Mode code command No Status Word transmit. DBAC bit set.
word is followed by a Set the Message Error BCAST bit reset.
ILCMD, RTRT bits IWA
contiguous data word (ME) status bit. DPB bit toggles.
reset.
Invalid command word.
OR
T/R bit equals 0 and No Message Info
No Status Word change. No Change None
UMCINV bit in the RT Word is written
(MC0 is not ndefined
Configuration
when T/R bit equals 0)
Register equals 1 ***
* Command is illegal but terminal is not using “illegal command detection” (in form response).
** Command is illegal and terminal is using “illegal command detection”
*** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”.

229
HI-6138
Bits Updated
in Descriptor
Control Word
T/R bit equals 0 and Normal CS update:

UMCINV bit in the RT Respond “In form”: BUSID bit updated.
DBAC bit set.
Configuration Reset Message Error MERR bit reset. IWA
BCAST bit reset.
Register equals 0. (ME) status and transmit Status ILCMD bit reset. IBR
DPB bit toggles.
Illegalization Table Word. RTRT bit reset.
bit equals 0 * (All error bits reset.)
T/R bit equals 0 and

ILCMD bit set.
UMCINV bit in the RT
Set Message Error DBAC bit set. MERR bit set. ILCMD
Configuration
(ME) status and transmit Status BCAST bit reset. BUSID bit updated. IWA
Register equals 0.
Word. DPB bit toggles. RTRT bit reset. IBR
Illegalization Table
bit equals 1 **

230
HI-6138
Bits Updated
in Descriptor
Control Word
Default response: Reset

SYNCHRONIZE
Message Error (ME) status Normal update:
WITHOUT DATA
then transmit Status Word. DBAC bit set. BUSID bit updated.
(MC1):
If broadcast, set the Status BCAST bit MERR bit reset. IWA
Mode code command
Word BCR bit and suppress updated. ILCMD bit reset. IBR
with mode code
Status Word transmit. DPB bit toggles. RTRT bit reset.
00001 and T/R bit
Reset the Time Tag counter (All error bits reset.)
equals 1
to 0x0000.
MC1 EXCEPTIONS:

OR
(mode code is undefined
Configuration
Respond “In form”: Reset

T/R bit equals 0
Message Error (ME) status. Normal update:
AND
If not broadcast, transmit DBAC bit set. BUSID bit updated.
Status Word. If broadcast, BCAST bit MERR bit reset. IWA
Configuration
set the BCR status bit and updated. ILCMD bit reset. IBR
Register equals 0.
suppress status response. DPB bit toggles. RTRT bit reset.
The Illegalization Table
The Time Tag counter is (All error bits reset.)
bit equals 0 *
not reset.
Set Message Error (ME)

T/R bit equals 0
status. If not broadcast,
AND ILCMD bit set.
transmit Status Word. DBAC bit set.
UMCINV bit in the RT MERR bit set. ILCMD
If broadcast, also set BCAST bit
Configuration BUSID bit updated. IWA
Status Word BCR bit and updated.
Register equals 0. RTRT bit reset. IBR
suppress Status response. DPB bit toggles.
The Illegalization Table (Other error bits reset.)
The Time Tag counter is
bit equals 1 **
not reset.
MERR bit set.

DBAC bit set. WCTERR bit set.
Mode code command No Status Word transmit.
BCAST bit BUSID bit updated. MERR
word is followed by a Set the Message Error
updated. ILCMD bit reset. IWA
contiguous data word (ME) status bit.

231
HI-6138
Bits Updated
in Descriptor
Control Word
No Status Word updates,

TRANSMIT STATUS Normal CS update:
Transmit Status from last
(MC2): BUSID bit updated.
valid command (assuming DBAC bit set.
Mode code command MERR bit reset.
last command was not a BCAST bit reset. IWA
with mode code ILCMD bit reset.
“Transmit Status” or a DPB bit toggles.
00010 RTRT bit reset.
“Transmit last Command”
and T/R bit equals 1 (All error bits reset.)
mode command.
MC2 EXCEPTIONS:
MERR bit set.

Broadcast address No Status Word transmit. DBAC bit set. BUSID bit updated. MERR
RT31 Set the Message Error BCAST bit set. ILCMD bit reset. IWA
(broadcast not allowed) (ME) and BCR status bits. DPB bit toggles. RTRT bit reset. IBR

OR
Configuration
T/R bit equals 0 Respond “In form”: Reset

Normal CS update:
AND Message Error (ME) status.
UMCINV bit in the RT If not broadcast, transmit
BCAST bit MERR bit reset. IWA
Configuration Status Word. If broadcast,
updated. ILCMD bit reset. IBR
Register equals 0 set the BCR status bit and
The Illegalization Table suppress status response.
bit equals 0 * Time Tag counter is not reset.
T/R bit equals 0

AND ILCMD bit set.
status. If not broadcast, DBAC bit set.
transmit Status Word. BCAST bit
If broadcast, also set updated.
Register equals 0 RTRT bit reset. IBR
Status Word BCR bit and DPB bit toggles.
The Illegalization Table. (Other error bits reset.)
suppress Status response.
bit equals 1 **
MERR bit set.

Mode code command No Status Word transmit. DBAC bit set. WCTERR bit set.
MERR
word is followed by a Set the Message Error BCAST bit reset. ILCMD bit reset.
IWA
contiguous data word (ME) status bit. DPB bit toggles. RTRT bit reset.

232
HI-6138
Bits Updated
in Descriptor
Control Word

Message Error (ME) status
then transmit Status Word.
INITIATE Normal CS update:
If broadcast, set the
SELF TEST (MC3): DBAC bit reset. BUSID bit updated.
Status Word BCR bit and
Mode code command BCAST bit MERR bit reset. IWA
suppress status transmit.
with mode code updated. ILCMD bit reset. IBR
Host should initiate self-
00011 DPB bit toggles. RTRT bit reset.
test then update Built-In
Test word at shared RAM
address 0x0093. Resume
terminal execution.
MC3 EXCEPTIONS:

OR
Configuration
T/R bit equals 0

Respond “In form”: Reset Normal CS update:
AND
Message Error (ME) status. DBAC bit set. BUSID bit updated.
If not broadcast, transmit BCAST bit MERR bit reset. IWA
Configuration
Status Word. If broadcast, updated. ILCMD bit reset. IBR
Register equals 0.
set the BCR status bit and DPB bit toggles. RTRT bit reset.
suppress status response. (Other error bits reset.)
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

WCTERR bit set.
ILCMD bit reset. IWA
RTRT bit reset.

233
HI-6138
Bits Updated
in Descriptor
Control Word

TRANSMITTER Normal CS update:
SHUTDOWN (MC4): DBAC bit reset. BUSID bit updated.
then transmit Status Word. If
Mode code command BCAST bit MERR bit reset. IWA
broadcast, set Status Word
with mode code updated. ILCMD bit reset. IBR
BCR bit and suppress status.
00100 DPB bit toggles. RTRT bit reset.
transmit. After Status trans-
mission, inhibit the inactive bus:
The device automatically shuts down either transmit and receive or transmit only for the inactive bus,
depending on the state of the BSDTXO bit in the Master Configuration Register. Refer to the description of the
AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)” for further information. When MC4 results
in transmitter shutdown, the condition is reflected by assertion of a TXASD or TXBSD bit in the corresponding
“Remote Terminal Built-In Test (BIT) Word Register (0x001E)”. If BSDTXO equals logic 0, an RXASD or RXBSD
bit will also be asserted, indicating full bus shutdown (transmit and receive). Once shutdown, the inactive bus
transmitter (or transmitter and receiver) can be reactivated by an “Override Transmitter Shutdown” MC5 or MC21
or “Reset Remote Terminal” MC8 mode code command, or by software reset (initiated by setting the RTRESET
bit in the “Master Status and Reset Register (0x0001)”) or by hardware reset initiated by asserting the MR Master
Reset input pin.
MC4 EXCEPTIONS:

OR
Configuration Register
equals 1 ***
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
Configuration Register BUSID bit updated. IWA
equals 0. RTRT bit reset. IBR
bit equals 1 **
MERR bit set.

WCTERR bit set.
RTRT bit reset.

234
HI-6138
Bits Updated
in Descriptor
Control Word

OVERRIDE
then transmit Status Word. Normal CS update:
TRANSMITTER
If broadcast, set the DBAC bit reset. BUSID bit updated.
SHUTDOWN (MC5):
Status Word BCR bit and BCAST bit MERR bit reset. IWA
Mode code command
suppress status transmit. updated. ILCMD bit reset. IBR
with mode code
This command is only used DPB bit toggles. RTRT bit reset.
00101
with dual redundant buses. (All error bits reset.)
and T/R bit equals 1
After Status transmission,
reactivate inactive bus:
The device automatically re-enables transmit and receive for the inactive bus, without considering BSDTXO bit
status in the Master Configuration Register. The device affirms re-enabled bus status by resetting all four TXASD,
TXBSD, RXASD and RXBSD “shutdown status” bits in the “Remote Terminal Built-In Test (BIT) Word Register
(0x001E)”. Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the resulting
hardware transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain
high. See Built-In Test Register description for further information.
MC5 EXCEPTIONS:

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

WCTERR bit set.
RTRT bit reset.

235
HI-6138
Bits Updated
in Descriptor
Control Word
INHIBIT TERMINAL Default response: Reset Normal CS update:

FLAG BIT (MC6): Message Error (ME) status DBAC bit reset. BUSID bit updated.
Mode code command then transmit Status Word. BCAST bit MERR bit reset. IWA
with mode code If broadcast, set the updated. ILCMD bit reset. IBR
00110 Status Word BCR bit and DPB bit toggles. RTRT bit reset.
and T/R bit equals 1 suppress status transmit. (All error bits reset.)
The device automatically sets the TF Inhibit bit in the “Remote Terminal Built-In Test (BIT) Word Register
(0x001E)”. While the TF inhibit bit is set, the device disregards assertion of the Terminal Flag (TF) bit in the
“Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A)” and only transmits status with the Terminal
Flag status bit reset.
Once the Terminal Flag has been inhibited, it can be reactivated by an “Override Inhibit Terminal Flag” MC7
or “Reset Remote Terminal” MC8 mode command, by software reset (asserting the SRST bit in the “Remote
Terminal Configuration Register (0x0017)”) or by asserting the MR master reset input pin.
MC6 EXCEPTIONS:

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

WCTERR bit set.
RTRT bit reset.

236
HI-6138
Bits Updated
in Descriptor
Control Word
OVERRIDE INHIBIT Default response: Reset Normal CS update:

TERMINAL FLAG BIT Message Error (ME) status DBAC bit reset. BUSID bit updated.
(MC7): then transmit Status Word. BCAST bit MERR bit reset. IWA
Mode code command If broadcast, set the updated. ILCMD bit reset. IBR
with mode code 00111 Status Word BCR bit and DPB bit toggles. RTRT bit reset.
and T/R bit equals 1 suppress status transmit. (All error bits reset.)
The device automatically resets the TF Inhibit bit in the “Remote Terminal Built-In Test (BIT) Word Register
(0x001E)”. While the TF inhibit bit is reset, the device transmits status with the Terminal Flag status bit set if the
Terminal Flag (TF) bit is asserted in the “Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A)”.
MC7 EXCEPTIONS:

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

WCTERR bit set.
RTRT bit reset.

237
HI-6138
Bits Updated
in Descriptor
Control Word
RESET REMOTE Normal CS update:

TERMINAL (MC8): Default response: Reset DBAC bit reset. BUSID bit updated.
Mode code command Message Error (ME) BCAST bit MERR bit reset. IWA
with mode code status. If not broadcast, updated. ILCMD bit reset. IBR
01000 transmit Status Word. DPB bit toggles. RTRT bit reset.
After Status transmission, the device automatically resets the status Message Error (ME) Busy and Broadcast
Command received (BCR) bits in its internal status register. The BIT Word at shared RAM address is reset to
0x0000. If either transmitter was shutdown, the shutdown condition is overridden. If the Terminal Flag (TF) status
bit was inhibited, the inhibit is reset.
This command does not reset any of the host-programmed registers that configure the terminal for operation. To
complete the terminal reset process, the host must assert either MR hardware master reset (with or without auto-
initialization) or assert the SRST bit in the “Remote Terminal Configuration Register (0x0017)” to execute software
reset. See following section entitled Reset and Initialization for additional details. Because MC8 requires host
interaction, most applications will probably utilize the IWA interrupt to alert the host when received.
MC8 EXCEPTIONS:

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

GAPERR bit set.
RTRT bit reset.

238
HI-6138
Bits Updated
in Descriptor
Control Word
RESERVED MODE The reserved mode code

CODES MC9 - MC15: commands do not have
Mode code command defined terminal actions.
with mode codes Host must initialize device
01001 through 01111 to respond using either of
and T/R bit equals 1 the two following methods:
RT is not using “illegal DBAC bit set. Normal CS update: IWA

The mode code’s bit command detection.” BCAST bit BUSID bit reset.
in Illegalization Table Respond “in form”: Reset updated. MERR bit reset.
equals 0 * Message Error (ME) status DPB bit toggles. ILCMD bit reset.
and transmit Status Word. RTRT bit reset.
OR OR
The mode code’s bit RT is using “illegal DBAC bit set. ILCMD bit set. ILCMD
in Illegalization Table command detection”and BCAST bit BUSID bit updated. IWA
equals 1 ** mode code is illegalized. updated. MERR bit set.
Set Message Error (ME) DPB bit toggles. RTRT bit reset.
status and transmit Status (Other error bits reset.)
Word.
MC9 - MC15
EXCEPTIONS:
Invalid command word. No terminal response,

OR the message is ignored.
No Message Info
T/R bit equals 0 and No Status Word change. No Change None
Word is written
UMCINV bit in the RT (mode code is undefined
Config. Reg. equals 1 *** when T/R bit equals 0)
T/R bit equals 0 Respond “In form”: Reset Normal CS update:

AND Message Error (ME) status. DBAC bit set. BUSID bit updated.
UMCINV bit in the RT If not broadcast, transmit BCAST bit MERR bit reset. IWA
Config. Reg. equals 0. Status Word. If broadcast, updated. ILCMD bit reset. IBR
The Illegalization Table set the BCR status bit and DPB bit toggles. RTRT bit reset.
bit equals 0 * suppress status response. (Other error bits reset.)
T/R bit equals 0 Set Message Error (ME)

ILCMD bit set.
AND status. If not broadcast, DBAC bit set.
MERR bit set. ILCMD
UMCINV bit in the RT transmit Status Word. BCAST bit
BUSID bit updated. IWA
Config. Reg. equals 0. If broadcast, also set updated.
RTRT bit reset. IBR
The Illegalization Table Status Word BCR bit and DPB bit toggles.
bit equals 1 ** suppress Status response.
MERR bit set.

WCTERR bit set.
RTRT bit reset.

239
HI-6138
Bits Updated
in Descriptor
Control Word
Default CS response:
Reset Message Error (ME)
TRANSMIT VECTOR and BCR status bits. then Normal CS update:
WORD (MC16): transmit Status Word BUSID bit updated.
DBAC bit reset.
Mode code command followed by the data word MERR bit reset.
BCAST bit reset. IWA
with mode code stored in the assigned index or ILCMD bit reset.
DPB bit toggles.
10000 ping-pong data buffer (or in RTRT bit reset.
and T/R bit equals 1 Descriptor Word 4 for SMCP (All error bits reset.)
Simplified Mode Command
Processing).
MC16 EXCEPTIONS:
MERR bit set.

DBAC bit set.
BCAST bit set.
DPB toggles.
OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

No Status Word transmit. WCTERR bit set.
Mode code command DBAC bit set. MERR
Set the Message Error BUSID bit updated.
word is followed by a BCAST bit reset. IWA
(ME) status bit. If broadcast, ILCMD bit reset.
contiguous data word DPB bit toggles. IBR
set the BCR status bit. RTRT bit reset.

240
HI-6138
Bits Updated
in Descriptor
Control Word
SYNCHRONIZE WITH Default response: Reset Normal CS update:

DATA WORD (MC17): Message Error (ME) BUSID bit updated.
DBAC bit reset.
Mode code command status. and transmit MERR bit reset.
with mode code Status Word. If broadcast, ILCMD bit reset.
DPB bit toggles.
10001 set BCR status bit and RTRT bit reset.
and T/R bit equals 0 suppress Status response. (All error bits reset.)
Device stores received data word in the assigned ping-pong or index data buffer (or in Descriptor Word 4 for
SMCP Simplified Mode Command Processing). “Remote Terminal Configuration Register (0x0017)” MCOPT2
and MCOPT3 bits allow automatic Time-Tag count loading using the data word received. If MCOPT2 equals
1, the received data word is automatically loaded to the Time-Tag counter if the low order bit of the received
data word (bit 0) equals 0. If MCOPT3 equals 1, the received data word is automatically loaded to the Time-Tag
counter if the low order bit of the received data word (bit 0) equals 1. If both bits are set, the received data word
is unconditionally loaded into the Time-Tag counter. For non-broadcast commands, counter load occurs before
status word transmission.
MC17 EXCEPTIONS:

OR
Config. Reg.
equals 1 ***
T/R bit equals 1 Respond “In form”: Reset Normal CS update:

AND Message Error (ME) status. DBAC bit set. BUSID bit updated.
UMCINV bit in the RT If not broadcast, transmit BCAST bit MERR bit reset. IWA
Config. Reg. equals 0. Status Word. If broadcast, updated. ILCMD bit reset. IBR
The Illegalization Table set the BCR status bit and DPB bit toggles. RTRT bit reset.
bit equals 0 * suppress status response. (Other error bits reset.)
T/R bit equals 1

No Status Word transmit. ILCMD bit set.
AND DBAC bit set.
Set the Message Error MERR bit set. ILCMD
UMCINV bit in the RT BCAST bit
(ME) status bit. BUSID bit updated. IWA
Config. Reg. equals 0. updated.
If broadcast, set the RTRT bit reset. IBR
The Illegalization Table DPB bit toggles.
BCR status bit. (Other error bits reset.)
bit equals 1 **
MERR bit set.
Mode code command No Status Word transmit. WCTERR bit set.
DBAC bit set. MERR
word not followed by a Set the Message Error BUSID bit updated.
contiguous data word (ME) status bit. If broadcast, ILCMD bit reset.
DPB bit toggles. IBR
(missing data word) set the BCR status bit. RTRT bit reset.

241
HI-6138
Bits Updated
in Descriptor
Control Word
MERR bit set.

Mode code command No Status Word transmit.
DBAC bit set. IWDERR bit set.
word followed by data Set the Message Error MERR
word with Manchester (ME) status bit. IWA
updated. ILCMD bit reset.
encoding or parity error If broadcast, set the IBR
(bad data word) BCR status bit.

242
HI-6138
Bits Updated
in Descriptor
Control Word
Default response: Status

is not updated. Transmit
TRANSMIT LAST Normal CS update:
Status Word from the previous
COMMAND (MC18): BUSID bit updated.
command, with data word DBAC bit reset.
containing the last valid BCAST bit reset. IWA
command word (assuming it DPB bit toggles.
was not a “Transmit Status” or
a “Transmit Last Command”
mode command.
Transmitted data word is automatically provided from an internal register, and is copied to assigned index or ping-
pong buffer (or to Descriptor Word 4 for SMCP Simplified Mode Command Processing)
MC18 EXCEPTIONS:
MERR bit set.

DBAC bit set.
BCAST bit set.
DPB toggles.

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.


243
HI-6138
Bits Updated
in Descriptor
Control Word

Message Error (ME) and
TRANSMIT BIT WORD Normal CS update:
BCR status bits. then
(MC19): BUSID bit reset.
transmit Status Word DBAC bit reset.
followed by data word from BCAST bit reset. IWA
either BIT Word Register or DPB bit toggles.
Alternate BIT Word Register,
depending on Configuration
Reg. 2 option bit ALTBITW.
Transmitted data word is automatically copied to the assigned index or ping-pong buffer (or to Descriptor Word 4
for SMCP Simplified Mode Command Processing)
MC19 EXCEPTIONS:
MERR bit set.

DBAC bit set.
BCAST bit set.
DPB toggles.

OR
Configuration
T/R bit equals 0

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 0

AND ILCMD bit set.
bit equals 1 **
MERR bit set.


244
HI-6138
Bits Updated
in Descriptor
Control Word

Message Error (ME)
SELECTED
status. and transmit Normal CS update:
TRANSMITTER
Status Word. If broadcast, BUSID bit updated.
SHUTDOWN (MC20): DBAC bit reset.
set BCR status bit and MERR bit reset.
Mode code command BCAST bit reset. IWA
suppress Status response. ILCMD bit reset.
with mode code DPB bit toggles.
This command is intended RTRT bit reset.
10100
for use in 1553 systems (All error bits reset.)
with more than one dual
redundant bus.
After Status Word transmission, the device stores received data word in the assigned index or ping-pong buffer
(or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies).
If the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)” equals 0, the received data word is
compared to the value in the Bus Select Register corresponding to the inactive bus. For example, if the command
is received on Bus A, the comparison uses the Bus B Select Register value. If the compared values match, the
device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on
the state of the BSDTXO bit in the “Master Configuration Register 1 (0x0000)”. See descriptions for the BSDTXO
bit in Master Configuration Register and the AUTOBSD bit in the RT Configuration Register for further information.
When a bus transmitter (or transmitter and receiver) is shut down by this mode command, bus status is reflected
by assertion of a TXASD or TXBSD bit in the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”. If
BSDTXO equals logic 0, an RXASD or RXBSD bit will also be asserted.
If the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)” equals 0, the IWA interrupt is
typically used to alert the host when an MC20 command is received. The host must evaluate whether the
received mode data word matches the bus selection criteria. If bus selection match occurs, the host fulfills bus
shutdown command using one of two options:
1. set the bus shutdown bit RTINHA or RTINHB for the inactive bus in the “Remote Terminal Configuration Regis-
ter (0x0017)” to inhibit both transmit and receive,
OR
2. assert the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to inhibit only transmit. The
inactive bus receiver remains active; all valid commands are heeded without transmit. This option is rarely
applied.
Once shutdown, the inactive bus transmitter (or transmitter and receiver) can be reactivated five ways: an
“Override Transmitter Shutdown” MC5, a MC21 command with data word that matches “bus select” criteria, a
“Reset Remote Terminal” MC8 mode code command, a software reset initiated by setting the RTRESET bit in the
“Master Status and Reset Register (0x0001)”, or by hardware reset initiated by asserting the MR Master Reset
input pin.
MC20 EXCEPTIONS:

OR
Configuration Register
equals 1 ***

245
HI-6138
Bits Updated
in Descriptor
Control Word
T/R bit equals 1

AND
Configuration
Register equals 0.
bit equals 0 *
T/R bit equals 1

AND ILCMD bit set.
bit equals 1 **
MERR bit set.
Mode code command No Status Word transmit. DBAC bit set. WCTERR bit updated.
MERR
word not followed by a Set the Message Error BCAST bit BUSID bit updated.
IWA
contiguous data word (ME) status bit. If broadcast, updated. ILCMD bit reset.
IBR
(missing data word) set the BCR status bit. DPB bit toggles. RTRT bit reset.
MERR bit set.
Mode code command
No Status Word transmit. DBAC bit set. IWDERR bit set.
word followed by data MERR
Set the Message Error BCAST bit BUSID bit updated.
word with Manchester IWA
(ME) status bit. If broadcast, updated. ILCMD bit reset.
encoding or parity error IBR
set the BCR status bit. DPB bit toggles. RTRT bit reset.
(bad data word)

246
HI-6138
Bits Updated
in Descriptor
Control Word
OVERRIDE
SELECTED Default response: Reset Normal CS update:
TRANSMITTER Message Error (ME) BUSID bit updated.
DBAC bit reset.
SHUTDOWN (MC21): status. and transmit MERR bit reset.
Mode code command Status Word. If broadcast, ILCMD bit reset.
DPB bit toggles.
with mode code set the BCR status bit and RTRT bit reset.
10101 suppress Status response. (All error bits reset.)
After Status Word transmission, the device stores the received data word in the assigned index or ping-pong
buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies).
If the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)” equals 0, the received data word is
compared to the value in the Bus Select Register corresponding to the inactive bus. For example, if the command
is received on Bus A, the comparison uses the Bus B Select Register value. If the compared values match, the
device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the BSDTXO
bit in the Master Configuration Register. The device affirms fully re-enabled bus status by resetting all four
TXASD, TXBSD, RXASD and/or RXBSD bits in the “Remote Terminal Built-In Test (BIT) Word Register (0x001E)”.
Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the resulting hardware
transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain high. See
RT Built-In Test Register description for further information.
If the AUTOBSD bit in the “Remote Terminal Configuration Register (0x0017)” equals 0, the IWA interrupt is
typically used to alert the host when an MC21 command is received. The host must evaluate whether the
received mode data word matches the bus selection criteria. If bus selection match occurs, the host fulfills the
“override shutdown” command using one of two options:
1. reset the RTINHA or RTINHB bus shutdown bit corresponding to the inactive bus in the “Remote Terminal
Configuration Register (0x0017)” to re-enable both transmit and receive, if the host used this bit to shut down
transmit and receive for an earlier MC4 or MC20 command. Note: Resetting the RTINHA or RTINHB shutdown
bit cannot restore bus transmit capability if the TXINHA or TXINHB input pin is asserted,
OR
2. reset the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to re-enable transmit if the host
used this pin to shut down transmit only for an earlier MC4 or MC20 command.
MC21 EXCEPTIONS:

OR
Configuration
T/R bit equals 1

AND
Configuration
Register equals 0.
bit equals 0 *

247
HI-6138
Bits Updated
in Descriptor
Control Word
T/R bit equals 1

AND ILCMD bit set.
bit equals 1 **
MERR bit set.

Mode code command No Status Word transmit. DBAC bit set. WCTERR bit set.
MERR
word not followed by a Set the Message Error BCAST bit BUSID bit updated.
IWA
contiguous data word (ME) status bit. If broadcast, updated. ILCMD bit reset.
IBR
(missing data word) set the BCR status bit. DPB bit toggles. RTRT bit reset.
MERR bit set.
Mode code command
No Status Word transmit. DBAC bit set. IWDERR bit set.
word followed by data MERR
Set the Message Error BCAST bit BUSID bit updated.
word with Manchester IWA
(ME) status bit. If broadcast, updated. ILCMD bit reset.
encoding or parity error IBR
set the BCR status bit. DPB bit toggles. RTRT bit reset.
(bad data word)

248
HI-6138
Bits Updated
in Descriptor
Control Word
RESERVED MODE The reserved mode code

CODES MC22 - MC31: commands do not have
Mode code defined actions.
commands Host must initialize device
having mode codes to respond using either of
10110 through 11111 the two following methods:
Mode code is illegalized. DBAC bit set. ILCMD bit set. ILCMD
The mode code’s bit Set Message Error (ME) BCAST bit reset. MERR bit set. IWA
in Illegalization Table status and transmit Status DPB bit toggles. BUSID bit updated.
equals 1 ** Word. If T/R bit equals 1, RTRT bit reset.
(RT is using “illegal suppress data word (Other error bits reset.)
command detection”) transmission.
OR OR
The mode code’s bit If T/R bit equals 1, DBAC bit set. Normal CS update: IWA
in Illegalization Table Reset Message Error (ME) BCAST bit reset. BUSID bit updated.
equals 0 * status. Transmit Status Word DPB bit toggles. MERR bit reset.
(RT not using “illegal with contiguous data word read ILCMD bit reset.
command detection,” from assigned index or ping- RTRT bit reset.
respond “in form”) pong buffer (or from Descriptor (All error bits reset.)
Word 4 if the SMCP option
applies.)
If T/R bit equals 0, DBAC bit reset. Normal CS update: IWA

Reset Message Error (ME) BCAST bit BUSID bit updated. IBR
status and transmit Status. If updated. MERR bit reset.
broadcast, also set BCR status DPB bit toggles. ILCMD bit reset.
and suppress Status transmit. RTRT bit reset
Device stores received data (All error bits reset.)
word in assigned index or ping-
pong buffer (or in Descriptor
Word 4 if SMCP Simplified
Mode Command Processing
applies).
MC22 - MC31
EXCEPTIONS:
No terminal response, the

No Message Info
Invalid command word. message is ignored. No Change None
Word is written
MERR bit set.

T/R bit equals 0 and No Status Word transmit.
DBAC bit set. WCTERR bit set.
mode code command Set the Message Error MERR
word is not followed by (ME) status bit. IWA
updated. ILCMD, RTRT bits
a contiguous data word If broadcast, set the IBR
DPB bit toggles. reset.
(missing data word) BCR status bit.

249
HI-6138
Bits Updated
in Descriptor
Control Word
T/R bit equals 0 and MERR bit set.

No Status Word transmit.
command word is DBAC bit set. IWDERR bit set.
Set the Message Error MERR
followed by data word BCAST bit BUSID bit updated.
(ME) status bit. IWA
with Manchester or updated. ILCMD, RTRT bits
If broadcast, set the IBR
parity error (bad data DPB bit toggles. reset.
BCR status bit.
word) (Other error bits reset.)
MERR, WCTERR bits

T/R bit equals 1 and set.
No Status Word transmit. DBAC bit set.
mode code command BUSID bit updated. MERR
Set the Message Error BCAST bit reset.
word is followed by a ILCMD, RTRT bits IWA
(ME) status bit. DPB bit toggles.
contiguous data word reset.
MERR bit set.

T/R bit equals 1 and No Status Word transmit. DBAC bit set. BUSID bit updated. MERR
mode code command Set the Message Error BCAST bit set. ILCMD, RTRT bits IWA
is addressed to RT31 (ME) and BCR status bits. DPB bit toggles. reset. IBR

250
HI-6138
24. ELECTRICAL CHARACTERISTICS

24.1. Absolute Maximum Ratings
Supply voltage (VDD) -0.3 V to +5.0 V
Logic input voltage range -0.3 V to +3.6 V
Voltage at BUSA/B or BUSA/B pins ±7V
Receiver differential voltage 10 Vp-p
Solder Temperature (reflow) 260oC
Junction Temperature 175oC
Storage Temperature -65oC to +150oC
24.2. Recommended Operating Conditions
Operating Supply voltage 3.3 VDC ± 5%

(VDD)
Operating (Ambient) Temperature Range
Industrial -40oC to +85oC

Extended -55oC to +125oC
NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device.
These are stress ratings only. Operation at the limits is not recommended.
24.3. DC Electrical Characteristics

VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Limits
Parameters Symbol Test Conditions Unit
Min Typ Max
Operating Voltage VDD 3.15 3.3 3.45 V
ICC1 Not Transmitting - 15 25 mA
Power Supply Current Continuous supply current

See Note 1 on next page while one bus transmits
ICC2 - 670 695 mA
@ 100% duty cycle, 78Ω
resistive load
PD1 Not Transmitting - - 86 mW

Power Dissipation
See Note 2 on next page Transmit one bus @ 100%
PD2 - 492 610 mW
duty cycle, 78Ω resistive load
Input Voltage (High) VIH Digital Inputs 70% - - VDD
Input Voltage (Low) VIL Digital Inputs - - 30% VDD
Input Current (High): Digital Inputs (each digital

IIH - - 100 μA
Inputs with pull-down. input pulled high)

251
HI-6138
Limits
Parameters Symbol Test Conditions Unit
Min Typ Max
Input Current (High): Digital Inputs (each digital
IIH +1 - - μA
Inputs with pull-up. input pulled high)
Input Current (Low) Digital Inputs (each digital

IIL - - -100 μA
Inputs with pull-up. input pulled low)
Input Current (Low) Digital Inputs (each digital

IIL -1 - - μA
Inputs with pull-down. input pulled low)
Output Voltage (High) VOH IOUT = -1.0mA, Digital outputs 90% - - VDD
Output Voltage (Low) VOL IOUT = 1.0mA, Digital outputs - - 10% VDD
RECEIVER (Measured at Point “AD” in Figure 29 unless otherwise specified)
Input Resistance RIN Differential 20 - - kΩ
Input Capacitance CIN Differential - - 5 pF
Common Mode Rejection Ratio CMRR 40 - - dB
Input Level VIN Differential - - 9 Vp-p
Input Common Mode Voltage VICM -5 - +5 V-pk
Detect VTHD 1.15 - 20.0 Vp-p

Threshold Voltage 1 MHz Sine Wave (Measured
(Direct-Coupled) at Point “AD“ in Figure 29)
No Detect VTHND - - 0.28 Vp-p
Detect VTHD 0.86 - 14.0 Vp-p

Threshold Voltage 1 MHz Sine Wave (Measured
(Transformer-Coupled) at Point “AT“ in Figure 30)
No Detect VTHND - - 0.2 Vp-p
TRANSMITTER (Measured at Point “AD” in Figure 29 unless otherwise specified)
Direct Coupled VOUT 35Ω Load 6.6 - 9.0 Vp-p

Output Voltage 70Ω Load (Measured at Point
Transformer Coupled VOUT 20.0 - 27.0 Vp-p
“AT“ in Figure 30)
Output Noise VON Differential, inhibited - - 10.0 mVp-p
Direct Coupled VDYN 35Ω Load -90 - 90 mV

Output Dynamic Offset Voltage 70Ω Load (Measured at Point
Transformer Coupled VDYN -250 - 250 mV
“AT“ in Figure 30)
Output Resistance ROUT Differential, not transmitting 10 - - kΩ
Output Capacitance COUT 1 MHz sine wave - - 15 pF
Note 1: In actual use, the highest practical transmit duty cycle is 96%, occurring when a Remote Terminal responds to a series
of 32 data word transmit commands (RT to BC) repeating with minimum intermessage gap of 4μs (2μs dead time) and typical RT
response delay of 5μs.
Note 2: While one bus continuously transmits, the power delivered by the 3.3V power supply is 3.3V × 670mA typical = 2.2W. Of
this, 492mW is dissipated in the device, the remainder in the load.

252
HI-6138
24.4. AC Electrical Characteristics ― Host Bus Interface (SPI) Timing
Limits
Parameters Symbol Units
Min Typ Max
INTERFACE TIMING (SPI Host Bus Interface)
SCK clock Period tCYC 25 - - ns
CE set-up time to first SCK rising edge tCES 15 - - ns
CE hold time after last SCK rising edge tCEH 15 - - ns
CE inactive between SPI instructions tCPH 100 - - ns
SPI SI Data set-up time to SCK rising edge tDS 5 - - ns
SPI SI Data hold time after SCK rising edge tDH 5 - - ns
SO valid after SCK falling edge tDV 0 - 10 ns
SO high-impedance after CE inactive tCHZ - - 90 ns
SERIAL INPUT TIMING DIAGRAM

t CPH
t CEH
t CYC
CE
t CES
SCLK
t DS t DH
SI MSB LSB
SERIAL OUTPUT TIMING DIAGRAM

t CPH
CE
SCLK
t DV t CHZ
SO
MSB LSB
Hi Impedance Hi Impedance
Figure 26. Host Bus Interface Timing Diagram

253
HI-6138
24.5. AC Electrical Characteristics ― Master Reset
Limits
Parameters Symbol Units
Min Typ Max
MASTER RESET MR
Minimum pulse width

PWMR 50 ns
Note: Two rising clock edges are required following the rising edge of MR to complete reset.
Reset complete
PWMR
MR
CLK
Figure 27. Master Reset Timing Diagram

254
HI-6138
25. MIL-STD-1553 BUS INTERFACE

MIL-STD-1553
BUS A
(Direct Coupled)
Isolation
Transformer 55Ω BUSA
Transceiver A
55Ω BUSA
1:2.5 MIL-STD-1553
BUS B
MIL-STD-1553 (Transformer Coupled)
Stub Coupler
Isolation
Transformer BUSB 52.5Ω
Transceiver B
BUSB 52.5Ω
1:2.5 1:1.4
HI-6138 Transceivers
Figure 28. Bus Connection Example using HI-6138
Each Bus
Isolation
BUSA/B Transformer 55Ω
MIL-STD-1553
Transceiver 35Ω
Interface
BUSA/B 55Ω
Point
“AD”
Figure 29. MIL-STD-1553 Direct Coupled Test Circuits
Each Bus
Isolation
BUSA/B Transformer
MIL-STD-1553
Transceiver 70Ω
Interface
BUSA/B
Point
“AT”
Figure 30. MIL-STD-1553 Transformer Coupled Test Circuits

255
HI-6138
26. ADDITIONAL PIN / PACKAGE CONFIGURATIONS

Notes:
1. All VCC, VCCP and GND pins must be connected.
2. See page 1 for HI-6138, 48-Pin QFN Package Configuration.
26.1. HI-6138PQx (48-pin PQFP)
39 - MTSTOFF
48 - BCTRIG
37 - RTMC8
47 - BENDI
41 - VCCP
44 - VCCP
40 - BUSB
42 - BUSB
43 - BUSA
45 - BUSA
38 - EE2K
46 - TEST
MODE - 1 36 - TTCLK
IRQ - 2 35 - ESCLK
ACKIRQ - 3 34 - EECOPY
MODE1760 - 4 33 - ECS
READY - 5 HI-6138PQIF 32 - MOSI
VCC - 6 31 - VCC
GND - 7 HI-6138PQTF 30 - GND
ACTIVE - 8 HI-6138PQMF 29 - MISO
RTSSF - 9 28 - MTTCLK
AUTOEN - 10 27 - LOCK
TXINHA - 11 26 - RTA4
TXINHB - 12 25 - RTA3
RTAP - 13
RTA0 - 14
CE - 15
VCC - 16
SCK - 17
SO - 18
SI - 19
GND - 20
MCLK - 21
RTA1 - 22
MR - 23
RTA2 - 24
48 - Pin Plastic Quad Flat Pack (PQFP)

256
HI-6138
27. ORDERING INFORMATION
HI - 6138 PQ x x
PART NUMBER LEAD FINISH
Blank Tin / Lead (Sn / Pb) Solder
F 100% Matte Tin (Pb-free, RoHS compliant)
PART NUMBER TEMPERATURE RANGE FLOW BURN IN
I -40 C to +85 C
o o
I No
T -55oC to +125oC T No
M -55 C to +125 C
o o
M Yes
PART NUMBER PACKAGE DESCRIPTION
PQ 48 PIN PLASTIC QUAD FLAT PACK, LQFP (48PQS)
HI - 6138 PC x x
PART NUMBER LEAD FINISH
Blank NiPdAu
F NiPdAu (Pb-free, RoHS compliant)
PART NUMBER TEMPERATURE RANGE FLOW BURN IN
I -40 C to +85 C
o o
I No
T -55oC to +125oC T No
M -55 C to +125 C
o o
M Yes
PART NUMBER PACKAGE DESCRIPTION
PC 48 PIN PLASTIC CHIP-SCALE PACKAGE, 6 x 6mm QFN (48PCS6)

257
HI-6138
28. REVISION HISTORY

Revision Date Description of Change
DS6138, Rev. New 7/14/15 Initial Release
In “24.3. DC Electrical Characteristics” on page 251, update Power Supply

Current (Not Transmitting) from 4 mA typ. and 10 mA max. to 10 mA typ. and
15 mA max. respectively. Update Power Supply Current (Transmitting) from 720
mA typ. and 760 mA max. to 875 mA typ. and 975 mA max. respectively. Update
Power Dissipation.
In “24.4. AC Electrical Characteristics ― Host Bus Interface (SPI) Timing” on
page 253, change “SO high-impedance after CE inactive” parameter from 75ns
to 90ns.
Rev. A 9/8/15 Indicate tCYL on SPI Input Timing Diagram.

Correct SPI operation modes in “Serial EEPROM Programming Utility” on page
193.
Functional polarity of AUTOBSD bit in “15.1. Remote Terminal Configuration
Register (0x0017)” on page 119 is reversed. Correct throughout datasheet.
Update READY pin delay time to include EE2K auto-initialization option (see
“Hardware Master Reset and Optional Auto-Initialization” on page 198).
Update MODE1760 bit description in “Master Configuration Register 2 (0x004E)”
on page 31.
Correct Pin Description for RTMC8 (Output).

Rev. B 2/22/16 Correct bit 4 functional description in “Master Configuration Register 2 (0x004E)”
on page 31, RT Terminal Flag Test.
Remove references to BCENA and RTENA pins.

Rev. C 6/29/16 Correct typo in “Table 6. Bus Controller Instruction Op Codes”. Instruction XFG
Op. Code changed from 0x1A to 0x17.
Clarify definition of Word 5 (Message Length Word) in “Table 9. Message Block in

Rev. D 09/16/16
Circular Command Buffer for SMT Monitor using 48-bit Time Tag”.
Correct Interrupt Address Word description in “9.7. Interrupt Log Buffer” on page
Rev. E 11/03/16
37. Correct Descriptor Table Control Word address derivation in Figure 14.
Rev. F 05/23/17 Update Power Dissipation and Power Supply Current parameters.
Clarify sequence of writing “Master Configuration Register 1 (0x0000)” during

Rev. G 08/10/17 configuration, (specifically RTSTEX and BCSTRT bits), to ensure proper terminal
configuration and start.

258
HI-6138
Bit 6 in “Master Status and Reset Register (0x0001)” should be “Reserved”.

Clarify format of Interrupt Information Word (IIW) and Interrupt Address Word
(IAW) in “Interrupt Log Buffer”. See Table 4.
Correct typos in “Hardware Interrupt Registers” description of bit 14.
Bit 5 in “Extended Configuration Register (0x004D)” should be “Reserved”.
Update functionality of BCTTA[1:0] bits in “Time Tag Counter Configuration
Bit 15 in “Memory Address Pointer Registers” is Read-Only.
Rev. H 05/07/18 Correct typo in “BC (Bus Controller) Configuration Register (0x0032)”, bit 4.
Reference to EOF interrupt bit should be BCWDT interrupt bit.
Clarify function of AUTOBSD, bit 4 in “Remote Terminal Configuration Register
(0x0017)”.
Bit 1, MC16OPT, in “Remote Terminal Configuration Register (0x0017)” is
erroneously called MCOPT1. Change throughout document.
Correct “Table 13. Circular Buffer Mode 2 (Initialization factors based on message
block size)” to reflect 8K RAM.
Fix minor typographical errors throughout the document.
Update BC Timeout Selection parameters in “BC (Bus Controller) Configuration

Register (0x0032)” bits [15,14].
Add RT-RT bus dead time for MT Timeout Selection parameters in “SMT
Rev. J 01/17/19
Configuration Register (0x0029)”, bits [15,14].
Update Bus Dead Time and RT-RT Timeout values in “Remote Terminal
Configuration Register (0x0017)”, bits [15,14].
Correct errors in Hard Reset Default values in “Table 3. Register Summary”.

Bits [13,12] in “Master Configuration Register 2 (0x004E)” are read-only.
Bits [4,3] in “Hardware Interrupt Output Enable Register (0x0013)” are read-only.
Clarify how to clear bits [12,11], LBFA and LBFB respectively in “Hardware
Correct text typo in “10.4.4. BC Block Status Word”, bit 7, MSTATSET.
List minimum instruction set that must be supported by external EEPROM in
section “Serial EEPROM Programming Utility”.
Update “Table 17. Registers not included in checksum” to reflect correct list of
registers.
Rev. K 05/28/19
Correct EEPROM auto-initialization time from 63 ms to 16 ms and other minor
typos in “20.1. Hardware Master Reset and Optional Auto-Initialization”.
Add clarification for digital loopback testing in “21.2.6. Host-Directed RT-Mode
Loopback Testing (On-Line Analog or Off-Line Digital)”.
Specify maximum voltage at BUSA/B or BUSA/B pins in “Absolute Maximum
Ratings”.
Change SPI set-up and hold times from 10ns to 5ns in “AC Electrical
Characteristics ― Host Bus Interface (SPI) Timing”.
Add new section “AC Electrical Characteristics ― Master Reset” (minimum pulse
width for MR).
Correct typos and add minor clarifications.

259
HI-6138
Remove note in “Figure 2. Address Mapping for Registers and RAM” regarding
unused memory space.
Clarify RW status of bits in “11.9. Bus Controller (BC) General Purpose Queue
Pointer Register (0x0038)”.
Update “Remote Terminal MIL-STD-1553 Status Word Bits Register (0x001A)”
Rev. L 03/24/2020 to reflect correct function of MC16OPT bit (refers to resetting SVCREQ status bit
and not SSYSF bit).
Correct typo in Read-Write descriptions of “Remote Terminal Bus A Select
Register (0x001C)” and “Remote Terminal Bus B Select Register (0x001D)”.
Correct typographical errors in “Figure 15. Illustration of Ping-Pong Buffer Mode”.
Update QFN lead finish to NiPdAu.

260
HI-6138

Remove statement in “15.7. Remote Terminal Current Message Information
Word Register (0x001B)” description regarding update 5μs after ACTIVE output
assertion.
Correct typo in “Bus Controller Instruction Op Codes”. CFT should be
unconditional.
Clarify conditions for assertion of bit 10, BCTRAP in “Bus Controller (BC) Pending
Interrupt Register (0x0007)”.
Clarify response of the STATSET and the MSTATSET bits in the “BC Block
Status Word” and the MSTATSET bit in the “Bus Controller (BC) Condition Code
Register (Read 0x0037)”.
Add description for “Bus Controller (BC) Last Message Block Address (0x004F)”.
Clarify operation of Terminal Flag status bit in “Remote Terminal MIL-STD-1553
Status Word Bits Register (0x001A)”, bit 0.
In “SMT Block Status Word (BSW) Description”, clarify when bit 14 is set to logic
“1” after message completion.
Add note to “BC (Bus Controller) Configuration Register (0x0032)”, bit 13, and
“BC Block Status Word”, bit 12, outlining additional conditions for when MBCE bit
is set in “BC Block Status Word”.
Correct description of “BC Control Word”, bit 4.
Rev. M 02/08/2021 Clarify function of BC Interrupt Address Word in “Table 4. Format of IIW and IAW
in Interrupt Log Buffer”.
Correct minor errors in description of bits 14, 9 and 4 in “Bus Controller (BC)
Interrupt Enable Register (0x0010)”.
Clarify response of BCENA bit 12 in “Master Configuration Register 1 (0x0000)”.
In “SMT Block Status Word (BSW) Description” clarify conditions when EO bit 12
is set.
In “BC (Bus Controller) Configuration Register (0x0032)” clarify operation of bit 6,
BSYNDV.
In “BC (Bus Controller) Configuration Register (0x0032)” clarify operation of bit 7,
MENDV.
Add note to “Self-Test Control Register (0x0028)” stating that registers 0x4F and
0x50 are expected to be modified during the RAM BIST but registers 0x0000-
0x004e (with the exception of Self-Test Register) retain their original values.
“SMT Configuration Register (0x0029)” updated to clarify Time Tag Event when
bits 9:8 = [11].
Add note to Section “Writing the Auto-Initialization EEPROM” regarding rewriting
address pointer prior to second unlock code.
Add note to “21.2.7. Programmed BC-Mode Digital Loopback Testing (Off-Line)”
regarding setting of bit 0, BCLBK in “Master Configuration Register 2 (0x004E)”.
In “SMT Block Status Word (BSW) Description”, add condition when EO bit 12 is
set.
Rev. N 03/08/2021
In “SMT Bus Monitor Pending Interrupt Register (0x0008)”, clarify when MTMERR
bit is set.
Clarify typos in “Appendix: RT messages responses, options & exceptions” for
Rev. P 06/01/2021
descriptions of MC17, MC20 and MC21.
Clarify use of MAP1 register for EEPROM programming in “19.1. Writing the
Rev. Q 08/23/2021
Auto-Initialization EEPROM”.

261
HI-6138
29. PACKAGE DIMENSIONS
48-PIN PLASTIC QUAD FLAT PACK (PQFP) millimeters (inches)

Package Type: 48PQS
0.155 ± 0.065
(0.006 ± 0.003)
0.50
BSC
(0.0197)
9.00 7.00 0.220 ± 0.05
BSC sq. BSC sq.
(0.354) (0.276) (0.009 ± 0.002)
0.60 ± 0.150
(0.024 ± 0.006)
See Detail A Detail A
1.60 1.40 ± 0.05

max
(0.063) (0.055 ± 0.002)
0° ≤ Θ ≤ 7°
BSC = “Basic Spacing between Centers” 0.100 ± 0.05

is theoretical true position dimension and (0.004 ± 0.002)
has no tolerance. (JEDEC Standard 95)
48-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) millimeters (inches)

Package Type: 48PCS6
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
4.000 ± 0.100
6.000 (0.157 ± 0.004)
BSC
(0.236)
0.40 BSC
(0.016)
6.000
BSC Top View 4.000 ± 0.100 Bottom
(0.236) (0.157 ± 0.004) View 0.200
typ
(0.008)
0.400 ± 0.100
1.00
max 0.200 (0.016 ± 0.004)
(0.039) typ
(0.008)
BSC = “Basic Spacing between Centers”

is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

262

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MAMBATM: HI-6138

3.3V BC / MT / RT MIL-STD-1553 / MIL-STD-1760

GENERAL DESCRIPTION • 64-Word Interrupt Log Buffer queues the most

The HI-6138 can be configured for automatic self- MODE - 1 36 - TTCLK

HOLT INTEGRATED CIRCUITS

6. HARDWARE FEATURES ............................................................................... 22

HOLT INTEGRATED CIRCUITS

6.6. MIL-STD-1760 Mode................................................................................................. 22

7. REGISTER & MEMORY ADDRESSING........................................................ 23

10. BUS CONTROLLER − CONFIGURATION AND OPERATION.................... 54

11. BUS CONTROLLER REGISTER DESCRIPTION ....................................... 78

HOLT INTEGRATED CIRCUITS

11.5. Bus Controller (BC) Frame Time Remaining Register (0x0035)................................ 88

12. SIMPLE MONITOR TERMINAL (SMT).......................................................... 98

13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION......... 108

HOLT INTEGRATED CIRCUITS

13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011).......................................... 116

14. REMOTE TERMINAL − OVERVIEW ............................................................118

16. REMOTE TERMINAL CONFIGURATION AND OPERATION.................... 138

HOLT INTEGRATED CIRCUITS

16.4.5. Transmit Mode Control Word................................................................................ 158

17. REMOTE TERMINAL MESSAGE DATA BUFFERS................................... 161

18. REMOTE TERMINAL MODE COMMAND PROCESSING......................... 188

19. SERIAL EEPROM PROGRAMMING UTILITY............................................ 193

20. RESET AND INITIALIZATION...................................................................... 198

HOLT INTEGRATED CIRCUITS

20.5. MIL-STD-1760: Busy Status Assertion After Power-Up........................................... 204

21. SELF-TEST.................................................................................................... 205

22. HOST SERIAL PERIPHERAL INTERFACE (SPI)....................................... 212

23. APPENDIX: RT MESSAGES RESPONSES, OPTIONS &

25. MIL-STD-1553 BUS INTERFACE................................................................. 255

HOLT INTEGRATED CIRCUITS

27. ORDERING INFORMATION......................................................................... 257

HOLT INTEGRATED CIRCUITS

HOLT INTEGRATED CIRCUITS

Figure 2. Address Mapping for Registers and RAM..................................................................... 19

Figure 3. Fixed Address Mapping for Interrupt Log Buffer............................................................ 40

Figure 4. Bus Controller Message Sequence Structures............................................................. 55

Figure 5. Bus Controller Flag Operation....................................................................................... 66

Figure 7. Simple Monitor Terminal (SMT) Data Storage............................................................. 102

Figure 9. MIL-STD-1553 Command Word Structure.................................................................. 138

Figure 11. Address Mapping for Illegalization Table .................................................................. 143

Figure 13. Address Mapping for RT Descriptor Table ................................................................ 147

Figure 15. Illustration of Ping-Pong Buffer Mode ....................................................................... 172

Figure 17. Illustration of Indexed Buffer Mode ........................................................................... 177

Figure 19. Illustration of Circular Buffer Mode 1......................................................................... 181

Figure 21. Illustration of Circular Buffer Mode 2......................................................................... 186

Figure 23. Generalized Single-Byte Transfer Using SPI Protocol.

Figure 24. Single-Word (2-Byte) Read From RAM or a Register............................................... 214

Figure 25. Single-Word (2-Byte) Write To RAM or a Register ................................................... 215

HOLT INTEGRATED CIRCUITS

Figure 26. Host Bus Interface Timing Diagram........................................................................... 253

Figure 27. Master Reset Timing Diagram................................................................................... 254

Figure 28. Bus Connection Example using HI-6138................................................................... 255

Figure 29. MIL-STD-1553 Direct Coupled Test Circuits.............................................................. 255

Figure 30. MIL-STD-1553 Transformer Coupled Test Circuits.................................................... 255

HOLT INTEGRATED CIRCUITS

Table 2. Host Interface Pins.......................................................................................................... 18

Table 3. Register Summary.......................................................................................................... 24