THGBMTG5D1LBAIL

e-MMC Module
4GB THGBMTG5D1LBAIL
INTRODUCTION
THGBMTG5D1LBAIL is 4GB density of e-MMC Module product housed in 153 ball BGA package. This unit is utilized
advanced NAND flash device(s) and controller chip assembled as Multi Chip Module. THGBMTG5D1LBAIL has an
industry standard MMC protocol for easy use.

FEATURES
THGBMTG5D1LBAIL Interface
THGBMTG5D1LBAIL has the JEDEC / MMCA Version 5.0 interface with 1-I/O, 4-I/O and 8-I/O mode.

Pin Connection
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm(max.) package)

14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

11 NC NC NC NC NC NC

10 NC NC NC VSF VSF RFU VSS VCC RFU NC NC RFU

9 NC NC NC VSF VCC NC NC NC

8 NC NC NC RFU VSS NC NC NC

7 RFU NC NC VSS Top View RFU NC NC RFU

6 VSS DAT7 V CCQ VCC RFU CLK NC V SSQ

5 DAT2 DAT6 NC RFU VCC VSS DS VSS RST_n CMD V SSQ V CCQ

V SSQ NC index V CCQ V CCQ

4 DAT1 DAT5 V SSQ

3 DAT0 DAT4 NC NC NC NC RFU NC NC NC NC NC NC V CCQ

VDDi V SSQ
2 NC DAT3 NC NC NC NC NC NC NC NC NC NC

1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

A B C D E F G H J K L M N P

Pin Number Name Pin Number Name Pin Number Name Pin Number Name

A3 DAT0 C2 VDDi J5 VSS N4 VCCQ

A4 DAT1 C4 VSSQ J10 VCC N5 VSSQ
A5 DAT2 C6 VCCQ K5 RST_n P3 VCCQ
A6 VSS E6 VCC K8 VSS P4 VSSQ
B2 DAT3 E7 VSS K9 VCC P5 VCCQ
B3 DAT4 F5 VCC M4 VCCQ P6 VSSQ
B4 DAT5 G5 VSS M5 CMD
B5 DAT6 H5 DS M6 CLK
B6 DAT7 H10 VSS N2 VSSQ
NC: No Connect, shall be connected to ground or left floating.
RFU: Reserved for Future Use, shall be left floating for future use.
VSF: Vendor Specific Function, shall be left floating.

© 2021 KIOXIA Corporation 1 October 7th, 2021

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Part Numbers
Available e-MMC Module Products – Part Numbers

Part Number Density Package Size NAND Flash Type Weight

THGBMTG5D1LBAIL 4GB 11.5mm x 13mm x 0.8mm(max.) 1 x 32Gbit 15nm 0.18g(typ.)

Temperature
Characteristics min. max. Unit

Operating temperature -25 85 °C

Storage temperature -40 85 °C
Note: Avoid locations where e-MMC devices may be exposed to water (wet, rain, dew condensation, etc.).

Performance
X8 mode / Sequential access

typ. Performance
Interleave [MB/s]
Part Number Density NAND Flash Type Frequency / Mode VCCQ
Operation
Read Write

1.8V 46 14
52MHz / SDR
3.3V 46 14
1.8V 88 14
THGBMTG5D1LBAIL 4GB 1 x 32Gbit 15nm Non Interleave 52MHz / DDR
3.3V 88 14
HS200 1.8V 152 14
HS400 1.8V 152 14

Power Supply
VCC = 2.7V to 3.6V
VCCQ = 1.7V to 1.95V / 2.7V to 3.6V

Operating Current (RMS)

The measurement for max. RMS current is done as average RMS current consumption over a period of 100ms.

max. Operating
Interleave Current [mA]
Part Number Density NAND Flash Type Frequency / Mode VCCQ
Operation
ICCQ ICC

1.8V 60 25
52MHz / SDR
3.3V 70 25
1.8V 70 30
THGBMTG5D1LBAIL 4GB 1 x 32Gbit 15nm Non Interleave 52MHz / DDR
3.3V 85 30
HS200 1.8V 90 30
HS400 1.8V 100 30

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Sleep Mode Current
ICCQS [μA] ICCQS + ICCS [μA]
Interleave
Part Number Density NAND Flash Type
Operation
typ. Note 1 max. Note 2 typ. Note 1 max. Note 2

THGBMTG5D1LBAIL 4GB 1 x 32Gbit 15nm Non Interleave 100 510 120 560

Note 1: The conditions of typical values are 25°C and VCCQ = 3.3V or 1.8V.
Note 2: The conditions of maximum values are 85°C and VCCQ = 3.6V or 1.95V.

Product Architecture
The diagram in Figure 1 illustrates the main functional blocks of the THGBMTG5D1LBAIL.
Specification of the CREG and recommended values of the CVCC, and CVCCQ in the Figure 1 are as follows.

Parameter Symbol Unit min. typ. max. Remark

μF 0.10 ― 2.2 Note 1 Except HS400

VDDi capacitor value CREG
μF 1.00 ― 2.2 Note 1 HS400

VCC capacitor value CVCC μF ― 2.2 + 0.1 ―

VCCQ capacitor value CVCCQ μF ― 2.2 + 0.1 ―

Note 1: KIOXIA recommends that the value should be usually applied as the value of C REG.

Package

VCC (3.3V)
CVCC
VCCQ (1.8V / 3.3V)
CVCCQ
NAND
NAND I/O BLOCK

REGULATOR
MMC I/O BLOCK

Control signal
I/O BLOCK

VDDi
CREG
NAND
CORE LOGIC
x11
MMC I/F (1.8V / 3.3V) NAND I/O

Figure 1 THGBMTG5D1LBAIL Block Diagram

© 2021 KIOXIA Corporation 3 October 7th, 2021

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PRODUCT SPECIFICATIONS
Package Dimensions
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm(max.) package) Unit: mm

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Density Specifications
Interleave User Area Density Note 1 SEC_COUNT in
Density Part Number
Operation [Bytes] Extended CSD

4GB THGBMTG5D1LBAIL Non Interleave 3,959,422,976 0x00760000

Note 1: User area density shall be reduced if enhanced user data area is defined.

Register Informations
OCR Register

OCR bit VDD Voltage Window Value

[6:0] Reserved 000 0000b

[7] 1.70 - 1.95V 1b
[14:8] 2.0 - 2.6V 000 0000b
[23:15] 2.7 - 3.6V 1 1111 1111b
[28:24] Reserved 0 0000b
[30:29] Access Mode 10b
[31] (card power up status bit (busy)) Note 1
Note 1: This bit is set to LOW if the Device has not finished the power up routine.

CID Register

CID-slice Name Field Width Value

[127:120] Manufacturer ID MID 8 0001 0001b

[119:114] Reserved ― 6 0b
[113:112] Device/BGA CBX 2 01b
[111:104] OEM/Application ID OID 8 0b
[103:56] Product name PNM 48 0x30 30 34 47 41 31 (004GA1)
[55:48] Product revision PRV 8 0x02
[47:16] Product serial PSN 32 Serial number
[15:8] Manufacturing date MDT 8 Refer to JEDEC Specification
[7:1] CRC7 checksum CRC 7 CRC7
[0] Not used, always ‘1’ ― 1 1b

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CSD Register

CSD-slice Name Field Width Cell Type Value

[127:126] CSD structure CSD_STRUCTURE 2 R 0x3

[125:122] System specification version SPEC_VERS 4 R 0x4
[121:120] Reserved ― 2 R 0x0
[119:112] Data read access-time 1 TAAC 8 R 0x5E
Data read access-time 2 in CLK cycles
[111:104] NSAC 8 R 0x00
(NSAC x 100)
[103:96] Max. bus clock frequency TRAN_SPEED 8 R 0x32
[95:84] Device command classes CCC 12 R 0x0F5
[83:80] Max. read data block length READ_BL_LEN 4 R 0x9
[79:79] Partial blocks for read allowed READ_BL_PARTIAL 1 R 0x0
[78:78] Write block misalignment WRITE_BLK_MISALIGN 1 R 0x0
[77:77] Read block misalignment READ_BLK_MISALIGN 1 R 0x0
[76:76] DSR implemented DSR_IMP 1 R 0x0
[75:74] Reserved ― 2 R 0x0
[73:62] Device size C_SIZE 12 R 0xFFF
[61:59] Max. read current at VDD min. VDD_R_CURR_MIN 3 R 0x7
[58:56] Max. read current at VDD max. VDD_R_CURR_MAX 3 R 0x7
[55:53] Max. write current at VDD min. VDD_W_CURR_MIN 3 R 0x7
[52:50] Max. write current at VDD max. VDD_W_CURR_MAX 3 R 0x7
[49:47] Device size multiplier C_SIZE_MULT 3 R 0x7
[46:42] Erase group size ERASE_GRP_SIZE 5 R 0x1F
[41:37] Erase group size multiplier ERASE_GRP_MULT 5 R 0x1F
[36:32] Write protect group size WP_GRP_SIZE 5 R 0x07
[31:31] Write protect group enable WP_GRP_ENABLE 1 R 0x1
[30:29] Manufacturer default ECC DEFAULT_ECC 2 R 0x0
[28:26] Write speed factor R2W_FACTOR 3 R 0x4
[25:22] Max. write data block length WRITE_BL_LEN 4 R 0x9
[21:21] Partial blocks for write allowed WRITE_BL_PARTIAL 1 R 0x0
[20:17] Reserved ― 4 R 0x0
[16:16] Content protection application CONTENT_PROT_APP 1 R 0x0
[15:15] File format group FILE_FORMAT_GRP 1 R/W 0x0
[14:14] Copy flag (OTP) COPY 1 R/W 0x0
[13:13] Permanent write protection PERM_WRITE_PROTECT 1 R/W 0x0
[12:12] Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 0x0
[11:10] File format FILE_FORMAT 2 R/W 0x0
[9:8] ECC code ECC 2 R/W/E 0x0
[7:1] CRC CRC 7 R/W/E CRC
[0] Not used, always ‘1’ ― 1 ― 0x1

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Extended CSD Register

Size
CSD-slice Name Field Cell Type Value
(Bytes)

[511:506] Reserved ― 6 ― All ‘0’

[505] Extended Security Commands Error EXT_SECURITY_ERR 1 R 0x00
[504] Supported Command Sets S_CMD_SET 1 R 0x01
[503] HPI features HPI_FEATURES 1 R 0x01
[502] Background operations support BKOPS_SUPPORT 1 R 0x01
[501] Max._packed read commands MAX_PACKED_READS 1 R 0x3F
[500] Max._packed write commands MAX_PACKED_WRITES 1 R 0x3F
[499] Data Tag Support DATA_TAG_SUPPORT 1 R 0x01
[498] Tag Unit Size TAG_UNIT_SIZE 1 R 0x03
[497] Tag Resource Size TAG_RES_SIZE 1 R 0x00
[496] Context management capabilities CONTEXT_CAPABILITIES 1 R 0x7F
[495] Large Unit size LARGE_UNIT_SIZE_M1 1 R 0x00
[494] Extended partitions attribute support EXT_SUPPORT 1 R 0x03
[493] Supported modes SUPPORTED_MODES 1 R 0x01
[492] FFU features FFU_FEATURES 1 R 0x00
[491] Operation codes timeout OPERATION_CODES_TIMEOUT 1 R 0x00
[490:487] FFU Argument FFU_ARG 4 R 0xFFFFFFFF
[486] Barrier support BARRIER_SUPPORT 1 R 0x00
[485:309] Reserved ― 177 ― All ‘0’
[308] CMD Queuing Support CMDQ_SUPPORT 1 R 0x00
[307] CMD Queuing Depth CMDQ_DEPTH 1 R 0x00
[306] Reserved ― 1 ― 0x00
Number of FW sectors correctly NUMBER_OF_FW_SECTORS
[305:302] 4 R All ‘0’
programmed _CORRECTLY_PROGRAMMED
VENDOR_PROPRIETARY
[301:270] Vendor proprietary health report 32 R All ‘0’
_HEALTH_REPORT
[269] Device life time estimation type B DEVICE_LIFE_TIME_EST_TYP_B 1 R 0x00
[268] Device life time estimation type A DEVICE_LIFE_TIME_EST_TYP_A 1 R 0x01
[267] Pre EOL information PRE_EOL_INFO 1 R 0x01
[266] Optimal read size OPTIMAL_READ_SIZE 1 R 0x04
[265] Optimal write size OPTIMAL_WRITE_SIZE 1 R 0x04
[264] Optimal trim unit size OPTIMAL_TRIM_UNIT_SIZE 1 R 0x01
[263:262] Device version DEVICE_VERSION 2 R 0x00
[261:254] Firmware version FIRMWARE_VERSION 8 R 0x01
Power class for 200MHz,
[253] PWR_CL_DDR_200_360 1 R 0xAA
DDR at VCC = 3.6V

[252:249] Cache size CACHE_SIZE 4 R 0x00001000

[248] Generic CMD6 timeout GENERIC_CMD6_TIME 1 R 0x05
[247] Power off notification(long) timeout POWER_OFF_LONG_TIME 1 R 0x32
[246] Background operations status BKOPS_STATUS 1 R 0x00
CORRECTLY
[245:242] Number of correctly programmed sectors 4 R 0x00000000
_PRG_SECTORS_NUM
[241] 1st initialization time after partitioning INI_TIMEOUT_AP 1 R 0x1E

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Size
CSD-slice Name Field Cell Type Value
(Bytes)

[240] Cache Flushing Policy CACHE_FLUSH_POLICY 1 R 0x00

[239] Power class for 52MHz, DDR at 3.6V PWR_CL_DDR_52_360 1 R 0x22
[238] Power class for 52MHz, DDR at 1.95V PWR_CL_DDR_52_195 1 R 0x77
Power class for 200MHz,
[237] PWR_CL_200_195 1 R 0x88
at VCCQ = 1.95V, VCC = 3.6V
Power class for 200MHz,
[236] PWR_CL_200_130 1 R 0x88
at VCCQ = 1.3V, VCC = 3.6V
Minimum Write Performance for 8bit
[235] MIN_PERF_DDR_W_8_52 1 R 0x00
at 52MHz in DDR mode
Minimum Read Performance for 8bit
[234] MIN_PERF_DDR_R_8_52 1 R 0x50
at 52MHz in DDR mode

[233] Reserved ― 1 ― 0x00

[232] TRIM Multiplier TRIM_MULT 1 R 0x01
[231] Secure Feature support SEC_FEATURE_SUPPORT 1 R 0x55
[230] Secure Erase Multiplier SEC_ERASE_MULT 1 R 0xDC
[229] Secure TRIM Multiplier SEC_TRIM_MULT 1 R 0xFF
[228] Boot information BOOT_INFO 1 R 0x07
[227] Reserved ― 1 R 0x00
[226] Boot partition size BOOT_SIZE_MULTI 1 R 0x10
[225] Access size ACC_SIZE 1 R 0x08
[224] High-capacity erase unit size HC_ERASE_GRP_SIZE 1 R 0x08
[223] High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R 0x07
[222] Reliable write sector count REL_WR_SEC_C 1 R 0x01
[221] High-capacity write protect group size HC_WP_GRP_SIZE 1 R 0x01
[220] Sleep current (VCC) S_C_VCC 1 R 0x06
[219] Sleep current (VCCQ) S_C_VCCQ 1 R 0x0A
PRODUCTION_STATE
[218] Production state awareness timeout 1 R 0x0A
_AWARENESS_TIMEOUT
[217] Sleep / awake timeout S_A_TIMEOUT 1 R 0x10
[216] Sleep Notification Timeout SLEEP_NOTIFICATION_TIME 1 R 0x10
[215:212] Sector Count SEC_COUNT 4 R 0x00760000
[211] Secure Write Protection Information SECURE_WP_INFO 1 R 0x00
Minimum Write Performance for 8bit
[210] MIN_PERF_W_8_52 1 R 0x00
at 52MHz
Minimum Read Performance 8bit
[209] MIN_PERF_R_8_52 1 R 0x64
at 52MHz
Minimum Write Performance for 8bit
[208] MIN_PERF_W_8_26_4_52 1 R 0x00
at 26MHz, for 4bit at 52MHz
Minimum Read Performance for 8bit
[207] MIN_PERF_R_8_26_4_52 1 R 0x3C
at 26MHz, for 4bit at 52MHz
Minimum Write Performance for 4bit
[206] MIN_PERF_W_4_26 1 R 0x00
at 26MHz
Minimum Read Performance for 4bit
[205] MIN_PERF_R_4_26 1 R 0x1E
at 26MHz

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Size
CSD-slice Name Field Cell Type Value
(Bytes)

[204] Reserved ― 1 ― 0x00

[203] Power class for 26MHz at 3.6V PWR_CL_26_360 1 R 0x22
[202] Power class for 52MHz at 3.6V PWR_CL_52_360 1 R 0x22
[201] Power class for 26MHz at 1.95V PWR_CL_26_195 1 R 0x66
[200] Power class for 52MHz at 1.95V PWR_CL_52_195 1 R 0x66
[199] Partition switching timing PARTITION_SWITCH_TIME 1 R 0x01
[198] Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME 1 R 0x0A
[197] I/O Driver Strength DRIVER_STRENGTH 1 R 0x1F
[196] Device Type DEVICE_TYPE 1 R 0x57
[195] Reserved ― 1 ― 0x00
[194] CSD structure CSD_STRUCTURE 1 R 0x02
[193] Reserved ― 1 ― 0x00
[192] Extended CSD revision EXT_CSD_REV 1 R 0x07
[191] Command Set CMD_SET 1 R/W/E_P 0x00
[190] Reserved ― 1 ― 0x00
[189] Command set revision CMD_SET_REV 1 R 0x00
[188] Reserved ― 1 ― 0x00
[187] Power class Note 1 POWER_CLASS 1 R/W/E_P 0x00
[186] Reserved ― 1 ― 0x00
[185] High-speed interface timing HS_TIMING 1 R/W/E_P 0x00
[184] Strobe Support STROBE_SUPPORT 1 R 0x00
[183] Bus width mode BUS_WIDTH 1 W/E_P 0x00
[182] Reserved ― 1 ― 0x00
[181] Erased memory content ERASED_MEM_CONT 1 R 0x00
[180] Reserved ― 1 ― 0x00
R/W/E &
[179] Partition configuration PARTITION_CONFIG 1 0x00
R/W/E_P
R/W &
[178] Boot config protection BOOT_CONFIG_PROT 1 0x00
R/W/C_P
[177] Boot bus Conditions BOOT_BUS_CONDITIONS 1 R/W/E 0x00
[176] Reserved ― 1 ― 0x00
[175] High-density erase group definition ERASE_GROUP_DEF 1 R/W/E_P 0x00
[174] Boot write protection status registers BOOT_WP_STATUS 1 R 0x00
R/W &
[173] Boot area write protection register BOOT_WP 1 0x00
R/W/C_P
[172] Reserved ― 1 ― 0x00
R/W,
[171] User area write protection register USER_WP 1 R/W/C_P & 0x00
R/W/E_P
[170] Reserved ― 1 ― 0x00
[169] FW configuration FW_CONFIG 1 R/W 0x00

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Size
CSD-slice Name Field Cell Type Value
(Bytes)

[168] RPMB Size RPMB_SIZE_MULT 1 R 0x04

[167] Write reliability setting register WR_REL_SET 1 R/W 0x1F
[166] Write reliability parameter register WR_REL_PARAM 1 R 0x05
[165] Start Sanitize operation SANITIZE_START 1 W/E_P 0x00
[164] Manually start background operations BKOPS_START 1 W/E_P 0x00
R/W &
[163] Enable background operations handshake BKOPS_EN 1 0x00
R/W/E
[162] H/W reset function RST_n_FUNCTION 1 R/W 0x00
[161] HPI management HPI_MGMT 1 R/W/E_P 0x00
[160] Partitioning Support PARTITIONING_SUPPORT 1 R 0x07
Note 2
[159:157] Max. Enhanced Area Size MAX_ENH_SIZE_MULT 3 R 0x0001D8
[156] Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W 0x00
PARTITION_SETTING
[155] Partitioning Setting 1 R/W 0x00
_COMPLETED
[154:143] General Purpose Partition Size Note 3 GP_SIZE_MULT 12 R/W 0x00
Note 4
[142:140] Enhanced User Data Area Size ENH_SIZE_MULT 3 R/W 0x00
[139:136] Enhanced User Data Start Address ENH_START_ADDR 4 R/W 0x00
[135] Reserved ― 1 ― 0x00
[134] Bad Block Management mode SEC_BAD_BLK_MGMNT 1 R/W 0x00
PRODUCTION_STATE
[133] Production state awareness Note 6 1 R/W/E 0x00
_AWARENESS
[132] Package Case Temperature is controlled Note 1 TCASE_SUPPORT 1 W/E_P 0x00
Note 1
[131] Periodic Wake-up PERIODIC_WAKEUP 1 R/W/E 0x00
PROGRAM_CID_CSD_DDR
[130] Program CID / CSD in DDR mode support 1 R 0x01
_SUPPORT
[129:128] Reserved ― 2 ― All ‘0’
[127:64] Vendor Specific Fields VENDOR_SPECIFIC_FIELD 64 ― ―

[63] Native sector size NATIVE_SECTOR_SIZE 1 R 0x01

[62] Sector size emulation USE_NATIVE_SECTOR 1 R/W 0x00
[61] Sector size DATA_SECTOR_SIZE 1 R 0x00
1st initialization
[60] after disabling sector size emulation INI_TIMEOUT_EMU 1 R 0x0A

[59] Class 6 commands control CLASS_6_CTRL 1 R/W/E_P 0x00

[58] Number of addressed group to be Released DYNCAP_NEEDED 1 R 0x00
[57:56] Exception events control EXCEPTION_EVENTS_CTRL 2 R/W/E_P 0x0000
[55:54] Exception events status EXCEPTION_EVENTS_STATUS 2 R 0x0000
Note 1
[53:52] Extended partitions attribute EXT_PARTITIONS_ATTRIBUTE 2 R/W 0x0000
[51:37] Context configuration CONTEXT_CONF 15 R/W/E_P 0x00
[36] Packed command status PACKED_COMMAND_STATUS 1 R 0x00
[35] Packed command failure index PACKED_FAILURE_INDEX 1 R 0x00
[34] Power Off Notification Note 5 POWER_OFF_NOTIFICATION 1 R/W/E_P 0x00
[33] Control to turn the Cache ON/OFF CACHE_CTRL 1 R/W/E_P 0x00

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Size
CSD-slice Name Field Cell Type Value
(Bytes)

[32] Flushing of the cache FLUSH_CACHE 1 W/E_P 0x00

[31] Control to turn the Barrier ON/OFF BARRIER_CTRL 1 R/W 0x00
[30] Mode config MODE_CONFIG 1 R/W/E_P 0x00
[29] Mode operation codes MODE_OPERATION_CODES 1 W/E_P 0x00
[28:27] Reserved ― 2 ― All ‘0’
[26] FFU status FFU_STATUS 1 R 0x00
Note 6
[25:22] Pre loading data size PRE_LOADING_DATA_SIZE 4 R/W/E_P 0x00760000
MAX_PRE_LOADING_DATA
[21:18] Max. pre loading data size 4 R 0x00760000
_SIZE
PRODUCT_STATE
[17] Product state awareness enablement Note 6 1 R/W/E & R 0x03
_AWARENESS_ENABLEMENT
[16] Secure Removal Type SECURE_REMOVAL_TYPE 1 R/W & R 0x09
[15] Command Queue Mode Enable CMDQ_MODE_EN 1 R/W/E_P 0x00
[14:0] Reserved ― 15 ― All ‘0’

Note 1: Although these fields can be re-written by host, e-MMC does not support.

Note 2: Max. Enhanced Area Size (MAX_ENH_SIZE_MULT [159:157]) has to be calculated by following formula.
Max. Enhanced Area = MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes
4

∑ Enhanced general partition size(i) + Enhanced user data area ≤ Max. enhanced area
i=1

Note 3: General Purpose Partition Size (GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143]) has to be calculated
by following formula.

General_Purpose_Partition_X Size = (GP_SIZE_MULT_X_2 x 2 16 + GP_SIZE_MULT_X_1 x 28

+ GP_SIZE_MULT_X_0 x 20) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes

Note 4: Enhanced User Data Area Size (ENH_SIZE_MULT [142:140]) has to be calculated by following formula.

Enhanced User Data Area x Size = (ENH_SIZE_MULT_2 x 216 + ENH_SIZE_MULT_1 x 28

+ ENH_SIZE_MULT_0 x 20) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes

Note 5: KIOXIA recommends to issue the Power Off Notification before turning off the device, especially when
cache is on or AUTO_EN (BKOPS_EN [163]:bit1) is set to ‘1b’.

Note 6: Pre loading data size = PRE_LOADING_DATA_SIZE x Sector Size

Pre loading data size should be multiple of 4KB and the pre loading data should be written by multiple of 4KB
chunk size, aligned with 4KB address. This is because the valid data size will be treated as 4KB when host writes
data less than 4KB.

If the host continues to write data in Normal state (after it wrote PRE_LOADING_DATA_SIZE amount of data)
and before soldering, the pre loading data might be corrupted after soldering.

If a power cycle is occurred during the data transfer, the amount of data written to device is not clear.
Therefore in this case, host should erase the entire pre loaded data and set again
PRE_LOADING_DATA_SIZE [25:22], PRODUCTION_STATE_AWARENESS [133], and
PRODUCT_STATE_AWARENESS_ENABLEMENT [17].

© 2021 KIOXIA Corporation 11 October 7th, 2021

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ELECTRICAL CHARACTERISTICS
DC Characteristics
Absolute Maximum Ratings
The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must
not be exceeded during operation, even for an instant.
If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably
altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with
exceeded ratings may cause break down, damage, and/or degradation to any other equipment. Applications using
the device should be designed such that each maximum rating will never be exceeded in any operating conditions.
Before using, creating, and/or producing designs, refer to and comply with the precautions and conditions set forth
in this document.
Parameter Symbol Test Conditions min. max. Unit

Supply voltage 1 VCC ― -0.5 4.1 V

Supply voltage 2 VCCQ ― -0.5 4.1 V

Voltage Input VIO ― -0.5 VCCQ + 0.5(≤ 4.1) V

General
Parameter Symbol Test Conditions min. max. Unit
Peak voltage on all lines ― ― -0.5 VCCQ + 0.5 V
All Inputs

Input Leakage Current (before initialization sequence Note 1

― ― -100 100 μA
and/or the internal pull up resistors connected)

Input Leakage Current (after initialization sequence and

― ― -2 2 μA
the internal pull up resistors disconnected)

All Outputs

Output Leakage Current (before initialization sequence) ― ― -100 100 μA

Output Leakage Current (after initialization sequence) ― ― -2 2 μA

Note 1: Initialization sequence is defined in Power-Up chapter of JEDEC / MMCA Standard.

Power Supply Voltage

Parameter Symbol Test Conditions min. max. Unit

Supply voltage 1 Note 1 VCC ― 2.7 3.6 V

1.7 1.95 V
Supply voltage 2 Note 1, 2 VCCQ ―
2.7 3.6 V

Note 1: Once the power supply VCC or VCCQ falls below the minimum guaranteed voltage (for example, upon sudden
power fail), the voltage level of VCC or VCCQ shall be kept less than 0.5V for at least 1ms before it goes
beyond 0.5V again.
Note 2: The host and device I/O power (VCCQ) shall be provided from same power supply.

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Supply Current
Interleave min. max.
Parameter Symbol Frequency / Mode VCCQ Unit
Operation ICCQ ICC ICCQ ICC
1.8V ― ― 60 10
52MHz / SDR mA
3.3V ― ― 70 15

1.8V ― ― 70 20
Read IROP Non Interleave 52MHz / DDR mA
3.3V ― ― 85 20

HS200 1.8V ― ― 90 30 mA

HS400 1.8V ― ― 100 30 mA

Operation
(RMS) 1.8V ― ― 50 25
52MHz / SDR mA
3.3V ― ― 55 25

1.8V ― ― 50 30
Write IWOP Non Interleave 52MHz / DDR mA
3.3V ― ― 55 30

HS200 1.8V ― ― 55 30 mA

HS400 1.8V ― ― 60 30 mA

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Internal resistance and Device capacitance
Parameter Symbol Test Conditions min. max. Unit

Single device capacitance CDEVICE ― ― 6 pF

Internal pull up resistance DAT1 - DAT7 RINT ― 10 150 kΩ

Bus Signal Levels

VCCQ
Output
Input VOH
high level
high level
VIH
undefined
VIL
Input Output
VOL
low level low level
VSS t
Open-Drain Mode Bus Signal Level
Parameter Symbol min. max. Unit Conditions

Output HIGH voltage VOH VCCQ - 0.2 ― V Note 1

Output LOW voltage VOL ― 0.3 V IOL = 2mA

Note 1: Because VOH depends on external resistance value (including outside the package), this value does not apply
as device specification. Host is responsible to choose the external pull-up and open drain resistance value to
meet VOH(min.) value.

Push-Pull Mode Bus Signal Level (High-Voltage)

Parameter Symbol min. max. Unit Conditions

Output HIGH voltage VOH 0.75 x VCCQ ― V IOH = -100μA at VCCQ min.

Output LOW voltage VOL ― 0.125 x VCCQ V IOL = 100μA at VCCQ min.

Input HIGH voltage VIH 0.625 x VCCQ VCCQ + 0.3 V ―

Input LOW voltage VIL VSS - 0.3 0.25 x VCCQ V ―

Push-Pull Mode Bus Signal Level (Dual-Voltage)

Parameter Symbol min. max. Unit Conditions

Output HIGH voltage VOH VCCQ - 0.45 ― V IOH = -2mA

Output LOW voltage VOL ― 0.45 V IOL = 2mA

Input HIGH voltage VIH 0.65 x VCCQ VCCQ + 0.3 V ―

Input LOW voltage VIL VSS - 0.3 0.35 x VCCQ V ―

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Driver Types Definition
In JEDEC, Driver Type-0 is defined as mandatory for e-MMC HS200 & HS400 Device. While four additional Driver
Types (1, 2, 3 and 4) are defined as optional, to allow the support of wider Host loads. The Host may select the most
appropriate Driver Type of the Device (if supported) to achieve optimal signal integrity performance.

Driver Type-0 is targeted for transmission line, based distributed system with 50Ω nominal line impedance.
Therefore, it is defined as 50Ω nominal driver. The nominal line impedance should be kept as 50Ω even if Driver Type
would be changed.
For HS200, when tested with CL = 15pF Driver Type-0 shall meet all AC characteristics and HS200 Device output
timing requirements. The test circuit defined in section 10.5.4.3 of JEDEC / MMCA Standard 5.0 is used for testing of
Driver Type-0.
For HS400, when tested with the reference load defined in Figure 3 HS400 reference load figure, Driver Type-0,
Driver Type-1 or Driver Type-4 shall meet all AC characteristics and HS400 Device output timing requirements.

Driver Nominal Impedance Note 1 Approximated driving capability

e-MMC Remark
Type (Driver strength) compared to Type-0

0 Supported 50Ω (18mA) x1 Default Driver Type

Recommendation at HS400 under the

1 Supported 33Ω (27mA) x 1.5 condition of JEDEC standard
reference load

2 Supported 66Ω (14mA) x 0.75

3 Supported 100Ω (9mA) x 0.5

Recommendation at HS400 under the

4 Supported 40Ω (23mA) x 1.2 condition of JEDEC standard
reference load

Note 1: Nominal impedance is defined by I-V characteristics of output driver at 0.9V when VCCQ = 1.8V.

* The most suitable setting for user’s operating environment should be selected.
At HS400, KIOXIA recommends Driver Type-1 and Type-4. This is because they meet all AC
characteristics and Device output timing requirements under the condition of JEDEC standard reference
load.

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Bus Timing
tPP
tWH
min.(VIH)
CLK 50% VCCQ tWL
50% VCCQ
tIH max.(VIL)
tISU tTHL tTLH

min.(VIH)
Input Data Invalid Data
max.(VIL)
tODLY tOSU tOH
min.(VOH)
Output Data Invalid Data
max.(VOL)

Data must always be sampled on the rising edge of the clock.

Device Interface Timings (High-speed interface timing)

Parameter Symbol min. max. Unit Remark

Clock CLK Note 1

CL ≤ 30pF
Clock frequency Data Transfer Mode (PP) Note 2 fPP 0 52 Note 3 MHz
Tolerance: + 100kHz
Clock frequency Identification Mode (OD) fOD 0 400 kHz Tolerance: + 20kHz
Clock high time tWH 6.5 ― ns CL ≤ 30pF
Clock low time tWL 6.5 ― ns CL ≤ 30pF
Note 4
Clock rise time tTLH ― 3 ns CL ≤ 30pF
Clock fall time tTHL ― 3 ns CL ≤ 30pF

Inputs CMD, DAT (referenced to CLK)

Input set-up time tISU 3 ― ns CL ≤ 30pF

Input hold time tIH 3 ― ns CL ≤ 30pF
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer tODLY ― 13.7 ns CL ≤ 30pF
Output hold time tOH 2.5 ― ns CL ≤ 30pF
Note 5
Signal rise time tRISE ― 3 ns CL ≤ 30pF
Signal fall time tFALL ― 3 ns CL ≤ 30pF
Note 1: CLK timing is measured at 50% of VCCQ.
Note 2: This product shall support the full frequency range from 0MHz - 26MHz, or 0MHz - 52MHz.
Note 3: Device can operate as high-speed interface timing at 26MHz clock frequency.
Note 4: CLK rise and fall times are measured by min.(VIH) and max.(VIL).
Note 5: Inputs CMD, DAT rise and fall times area measured by min.(VIH) and max.(VIL), and outputs CMD, DAT rise
and fall times are measured by min.(VOH) and max.(VOL).

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Device Interface Timings (Backward-compatible interface timing)
Parameter Symbol min. max. Unit Remark Note 1

Clock CLK Note 2

Clock frequency Data Transfer Mode (PP) Note 3 fPP 0 26 MHz CL ≤ 30pF

Clock frequency Identification Mode (OD) fOD 0 400 kHz

Clock high time tWH 10 ― ns CL ≤ 30pF

Clock low time tWL 10 ― ns CL ≤ 30pF

Clock rise time Note 4 tTLH ― 10 ns CL ≤ 30pF

Clock fall time tTHL ― 10 ns CL ≤ 30pF

Inputs CMD, DAT (referenced to CLK)

Input set-up time tISU 3 ― ns CL ≤ 30pF

Input hold time tIH 3 ― ns CL ≤ 30pF

Outputs CMD, DAT (referenced to CLK)

Output set-up time Note 5 tOSU 11.7 ― ns CL ≤ 30pF

Output hold time Note 5 tOH 8.3 ― ns CL ≤ 30pF

Note 1: The e-MMC must always start with the backward-compatible interface timing. The timing mode can be
switched to high-speed interface timing by the host sending the SWITCH command (CMD6) with the
argument for high-speed interface select.
Note 2: CLK timing is measured at 50% of VCCQ.
Note 3: For compatibility with e-MMCs that support the v4.2 standard or earlier, host should not use > 26MHz before
switching to high-speed interface timing.
Note 4: CLK rise and fall times are measured by min.(VIH) and max.(VIL).
Note 5: tOSU and tOH are defined as values from clock rising edge. However, the e-MMC device will utilize clock falling
edge to output data in backward compatibility mode. Therefore, it is recommended for hosts either to set t WL
value as long as possible within the range which will not go over tCK - tOH(min.) in the system or to use slow
clock frequency, so that host could have data set up margin for the device.
e-MMC device utilize clock falling edge to output data in backward compatibility mode.
Host should optimize the timing in order to have data set up margin as follows.

tWL

CLK

tODLY tOSU tOH

Output Invalid Data

tOSU(min.) = tWL(min.) - tODLY(max. 8ns)

Figure 2 Output timing

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Bus Timing for DAT signals for during 2x data rate operation
These timings applies to the DAT [7:0] signals only when the device is configured for dual data mode operation. In
this dual data mode, the DAT signals operates synchronously of both the rising and the falling edges of CLK. The
CMD signal still operates synchronously of the rising edge of CLK and therefore complies with the bus timing
specified in High-speed interface timing or Backward-compatible interface timing.

tPP

min.(VIH)
CLK 50% VCCQ 50% VCCQ
max.(VIL)
tIHddr
tIHddr
tISUddr tISUddr
min.(VIH)
Input DATA DATA DATA Invalid
max.(VIL)

tODLYddr(max.) tODLYddr(max.)
tODLYddr(min.) tODLYddr(min.)

min.(VOH)
Output DATA DATA DATA Invalid
max.(VOL)

In DDR mode data on DAT [7:0] lines are sampled on both edges of the clock.
(Not applicable for CMD line.)

High-speed dual data rate interface timings

Parameter Symbol min. max. Unit Remark

Input CLK Note 1

Clock duty cycle ― 45 55 % Includes jitter, phase noise

Clock rise time tTLH ― 3 ns CL ≤ 30pF

Clock fall time tTHL ― 3 ns CL ≤ 30pF

Input CMD (referenced to CLK-SDR mode)

Input set-up time tISUddr 3 ― ns CL ≤ 20pF

Input hold time tIHddr 3 ― ns CL ≤ 20pF

Output CMD (referenced to CLK-SDR mode)

Output delay time during data transfer tODLY ― 13.7 ns CL ≤ 20pF

Output hold time tOH 2.5 ― ns CL ≤ 20pF

Signal rise time tRISE ― 3 ns CL ≤ 20pF

Signal fall time tFALL ― 3 ns CL ≤ 20pF

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Parameter Symbol min. max. Unit Remark

Input DAT (referenced to CLK-DDR mode)

Input set-up time tISUddr 2.5 ― ns CL ≤ 20pF

Input hold time tIHddr 2.5 ― ns CL ≤ 20pF

Output DAT (referenced to CLK-DDR mode)

Output delay time during data transfer tODLYddr 1.5 7 ns CL ≤ 20pF

Signal rise time (all signals) Note 2 tRISE ― 2 ns CL ≤ 20pF

Signal fall time (all signals) tFALL ― 2 ns CL ≤ 20pF

Note 1: CLK timing is measured at 50% of VCCQ.

Note 2: Inputs DAT rise and fall times are measured by min.(VIH) and max.(VIL), and outputs DAT rise and fall times
are measured by min.(VOH) and max.(VOL).

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Bus Timing Specification in HS200 mode

HS200 Clock Timing

Host CLK Timing in HS200 mode shall conform to the timing specified in following figure and Table. CLK input shall
satisfy the clock timing over all possible operation and environment conditions. CLK input parameters should be
measured while CMD and DAT lines are stable high or low, as close as possible to the Device. The maximum
frequency of HS200 is 200 MHz. Hosts can use any frequency up to the maximum that HS200 mode allows.

VCCQ tPERIOD

VIH
CLOCK VT
INPUT
VIL
VSS tTHL
tTLH

Note 1: VIH denote VIH(min.) and VIL denotes VIL(max.).

Note 2: VT = 50% of VCCQ indicates clock reference point for timing measurements.

Symbol min. max. Unit Remark

tPERIOD 5 ― ns 200MHz(max.), between rising edges

tTLH, tTHL < 1ns(max.) at 200MHz, CDEVICE = 6pF,
tTLH, tTHL ― 0.2 x tPERIOD ns The absolute maximum value of tTLH, tTHL is 10ns regardless of
clock frequency
Duty Cycle 30 70 %

HS200 Device Input Timing

VCCQ tPERIOD

CLOCK VT
INPUT

VSS

VCCQ tISU tIH

VIH VIH
CMD, DAT [7 - 0] VALID
INPUT VIL WINDOW VIL
VSS

Note 1: tISU and tIH are measured at VIL(max.) and VIH(min.).

Note 2: VIH denote VIH(min.) and VIL denotes VIL(max.).

Symbol min. max. Unit Remark

tISU 1.40 ― ns CDEVICE ≤ 6pF

tIH 0.8 ― ns CDEVICE ≤ 6pF

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HS200 Device Output Timing
tPH parameter is defined to allow device output delay to be longer than t PERIOD. After initialization, the tPH may have
random phase relation to the clock. The Host is responsible to find the optimal sampling point for the Device outputs,
while switching to the HS200 mode.
While setting the sampling point of data, a long term drift, which mainly depends on temperature drift, should be
considered. The temperature drift is expressed by ΔTPH. Output valid data window (tVW) is available regardless of the
drift (ΔTPH) but position of data window varies by the drift.

tPERIO
VCCQ D

CLOCK VT
INPUT

VSS

tPH tVW VCCQ

VOH VOH
CMD, DAT [7 - 0] VALID
OUTPUT VOL WINDOW VOL

VSS
Note: VOH denotes VOH(min.) and VOL denotes VOL(max.).

Symbol min. max. Unit Remark Note 1

Device output momentary phase from CLK input to CMD or

tPH 0 2 UI DAT lines output.
Does not include a long term temperature drift.
Delay variation due to temperature change after tuning.
-350 +1550 Total allowable shift of output valid window (tVW) from last
ΔTPH ps
(ΔT = -20°C) (ΔT = 90°C) system Tuning procedure.
ΔTPH is 2600ps for ΔT from -25°C to 125°C during operation.
tVW = 2.88ns at 200MHz
Using test circuit in following figure including skew among
tVW 0.575 ― UI CMD and DAT lines created by the Device.
Host path may add Signal Integrity induced noise, skews, etc.
Expected tVW at Host input is larger than 0.475UI.

Note 1: Unit Interval (UI) is one bit nominal time. For example, UI = 5ns at 200MHz.

Meas. Location
Driver

CL = 15pF

Note 1: CL is total equivalent lumped capacitance for each Driver.

Note 2: CL incorporates device die load, device package load and equivalent lumped load external to the device.
Note 3: In distributed transmission lines only part of the line capacitance considered as load for the Driver.

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ΔTPH consideration

ΔTPH = -350ps ΔTPH = 1550ps

Sampling point

VALID
WINDOW Sampling point after tuning

VALID Sampling point after junction heated to +90°C

WINDOW

VALID
WINDOW Sampling point after junction cooled to -20°C

Implementation Guide:
Host should design to avoid sampling errors that may be caused by the ΔTPH drift.
It is recommended to perform tuning procedure while Device wakes up, after sleep.
One simple way to overcome the ΔTPH drift is by reduction of operating frequency.

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Bus Timing Specification in HS400 mode

HS400 Input Timing

The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode.

tPERIOD
VCCQ
tCKDCD
CLOCK
INPUT
VT tCKMPW tCKMPW
tCKDCD
VSS

VCCQ tISU tIH tISU tIH

VIH VIH
DAT [7 - 0] VALID VALID
INPUT WINDOW WINDOW
VIL VIL
VSS

Note: VT = 50% of VCCQ indicates clock reference point for timing measurements.

Parameter Symbol min. max. Unit Remark

Input CLK
200MHz(max.), between rising edges
Cycle time data transfer mode tPERIOD 5 ― ns
With respect to VT
Slew rate SR 1.125 ― V/ns With respect to VIH / VIL
Allowable deviation from an ideal 50% duty cycle
Duty cycle distortion tCKDCD 0.0 0.3 ns With respect to VT
Includes jitter, phase noise
Minimum pulse width tCKMPW 2.2 ― ns With respect to VT
Input DAT (referenced to CLK)
CDEVICE ≤ 6pF
Input set-up time tISUddr 0.4 ― ns
With respect to VIH / VIL
CDEVICE ≤ 6pF
Input hold time tIHddr 0.4 ― ns
With respect to VIH / VIL
Slew rate SR 1.125 ― V/ns With respect to VIH / VIL

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HS400 Device Output Timing
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC
status response.

tPERIOD
VCCQ
tDSDCD
Data Strobe
VT tDSMPW tDSMPW
tDSDCD
VSS

tRQ tRQH
VCCQ
VOH VOH
DAT [7 - 0] VALID VALID
OUTPUT WINDOW WINDOW
VOL VOL
VSS

Note: VT = 50% of VCCQ indicates clock reference point for timing measurements.

Parameter Symbol min. max. Unit Remark

Data Strobe
200MHz(max.), between rising edges
Cycle time data transfer mode tPERIOD 5 ― ns
With respect to VT
Slew rate SR 1.125 ― V/ns With respect to VOH / VOL and HS400 reference load
Allowable deviation from the input CLK duty cycle
distortion(tCKDCD)
Duty cycle distortion tDSDCD 0.0 0.2 ns
With respect to VT
Includes jitter, phase noise
Minimum pulse width tDSMPW 2.0 ― ns With respect to VT
Output DAT (referenced to Data Strobe)
Output skew tRQ ― 0.4 ns With respect to VOH / VOL and HS400 reference load
Output hold skew tRQH ― 0.4 ns With respect to VOH / VOL and HS400 reference load
Slew rate SR 1.125 ― V/ns With respect to VOH / VOL and HS400 reference load

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Driver
Device I/O Measurement Point
Z0 = 50Ω
Td = 350ps CREFERENCE = 4pF

Reference Load

Figure 3 HS400 reference load

HS400 Capacitance
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or
CRC status response.
Parameter Symbol min. typ. max. Unit Remark

Pull-up resistance for CMD RCMD 4.7 ― 100 Note 1 kΩ

Pull-up resistance for DAT0 - DAT7 RDAT 10 ― 100 Note 1 kΩ
Pull-down resistance for Data Strobe RDS 10 ― 100 Note 1 kΩ
Internal pull up resistance DAT1 - DAT7 RINT 10 ― 150 kΩ
Single Device capacitance CDEVICE ― ― 6 pF

Note 1: Recommended maximum value is 50kΩ for 1.8V interface supply voltages.

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Overshoot / Undershoot Specification
VCCQ
Unit
1.70V - 1.95V

Maximum peak amplitude allowed for overshoot area

max. 0.9 V
(Refer to Figure 4 Overshoot / Undershoot definition)
Maximum peak amplitude allowed for undershoot area
max. 0.9 V
(Refer to Figure 4 Overshoot / Undershoot definition)
Maximum area above VCCQ
max. 1.5 V-ns
(Refer to Figure 4 Overshoot / Undershoot definition)
Maximum area below VSSQ
max. 1.5 V-ns
(Refer to Figure 4 Overshoot / Undershoot definition)

Maximum Amplitude
Overshoot Area

VCCQ
Volts
(V) VSSQ

Undershoot Area
Maximum Amplitude
Time (ns)

Figure 4 Overshoot / Undershoot definition

H/W Reset Operation

CLK
Note 1

RST_n
tRSTW tRSTH
tRSCA
Host can issue boot
initiation or CMD1
Device starts a reset sequence
at the RST_n rising edge Do not care

Note 1: Device will detect the rising edge of RST_n signal to trigger internal reset sequence.

H/W Reset Timings

Symbol Parameter min. max. Unit
tRSTW RST_n pulse width 1 ― μs
Note 1
tRSCA RST_n to Command time 200 ― μs
tRSTH RST_n high period (interval time) 1 ― μs

Note 1: 74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.
Note 2: During the device internal initialization sequence right after power on, device may not be able to detect
RST_n signal, because the device may not complete loading RST_n_ENABLE bits of the extended CSD
register into the controller yet.

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Power-up sequence

Supply voltage

VCC max.

VCC min.

VCCQ max.

VCCQ min.

0.5V
time

VCCQ Power up time VCC Power up time VCCQ Power up time

tPRUL tPRUH tPRUL

Figure 5 Power up sequence

Power-up parameter
Parameter Symbol min. max. Remark

Supply power-up for 3.3V tPRUH 5μs 35ms

Supply power-up for 1.8V tPRUL 5μs 25ms

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FUNCTIONAL RESTRICTIONS
- Pre loading data size is limited to MAX_PRE_LOADING_DATA_SIZE [21-18] regardless of using Production
State Awareness function.
- MAX_PRE_LOADING_DATA_SIZE [21-18] value will change when host sets Enhanced User area Partition.

RELIABILITY GUIDANCE
This reliability guidance is intended to notify some guidance related to using raw NAND flash. Although random bit errors
may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad
when a program status failure or erase status failure is detected. The other failure modes may be recovered by a block
erase. ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.

-Write / Erase Endurance

Write / Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either
an auto program or auto block erase operation. The cumulative bad block count will increase along with the number of
write / erase cycles.

-Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After
block erasure and reprogramming, the block may become usable again. Also write / erase Endurance deteriorates data
retention capability. The figure below shows a generic trend of relationship between write / erase Endurance and data
retention.

Data
Retention

Write / Erase Endurance

-Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors occur on
other pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny
charge may build up and can cause a cell to be soft programmed to another state. After block erasure and
reprogramming, the block may become usable again.

Considering the above failure modes, KIOXIA recommends following usage:

- Please avoid any excessive iteration of resets and initialization sequences (Device identification mode) as far as
possible after power-on, which may result in read disturb failure. The resets include hardware resets and software
resets.

e.g. 1) Iteration of the following command sequence, CMD0 - CMD1 ---

The assertion of CMD1 implies a count of internal read operation in Raw NAND.
CMD0: Reset command, CMD1: Send operation command

e.g. 2) Iteration of the following commands, CMD30 and/or CMD31

CMD30: Send status of write protection bits, CMD31: Send type of write protection

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DOCUMENT REVISION HISTORY

Rev.1.0 Oct. 7th, 2021 - Released as first revision

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RESTRICTIONS ON PRODUCT USE
KIOXIA Corporation and its subsidiaries and affiliates are collectively referred to as “KIOXIA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
 KIOXIA reserves the right to make changes to the information in this document and related Product without notice.
 This document and any information herein may not be reproduced without prior written permission from KIOXIA. Even with KIOXIA's
written permission, reproduction is permissible only if reproduction is without alteration/omission.
 Though KIOXIA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant KIOXIA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "Reliability Information" in KIOXIA Corporation’s website and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
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parameters for such designs and applications. KIOXIA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
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 PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without
limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical
equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to
control combustions or explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE
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limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the
U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
 Please contact your KIOXIA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. KIOXIA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING
AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.

© 2021 KIOXIA Corporation 30 October 7th, 2021